OpenCores
URL https://opencores.org/ocsvn/w11/w11/trunk

Subversion Repositories w11

[/] [w11/] [tags/] [w11a_V0.61/] [rtl/] [bplib/] [fx2lib/] [fx2lib.vhd] - Blame information for rev 26

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 17 wfjm 
-- $Id: fx2lib.vhd 453 2012-01-15 17:51:18Z mueller $
2 
--
3 
-- Copyright 2011-2012 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4 
--
5 
-- This program is free software; you may redistribute and/or modify it under
6 
-- the terms of the GNU General Public License as published by the Free
7 
-- Software Foundation, either version 2, or at your option any later version.
8 
--
9 
-- This program is distributed in the hope that it will be useful, but
10 
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
11 
-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
12 
-- for complete details.
13 
--
14 
------------------------------------------------------------------------------
15 
-- Package Name:   fx2lib
16 
-- Description:    Cypress ez-usb fx2 support
17 
--
18 
-- Dependencies:   -
19 
-- Tool versions:  xst 12.1, 13.1, 13.3; ghdl 0.26-0.29
20 
--
21 
-- Revision History:
22 
-- Date         Rev Version  Comment
23 
-- 2012-01-14   453   1.3    use afull/aempty logic instead of exporting size
24 
-- 2012-01-03   449   1.2.1  reorganize fx2ctl_moni; hardcode ep's
25 
-- 2012-01-01   448   1.2    add fx2_2fifoctl_ic
26 
-- 2011-12-25   445   1.1    change pktend iface in fx2_2fifoctl_as
27 
-- 2011-07-17   394   1.0.1  add c_fifo_epx and fx2ctl_moni_type
28 
-- 2011-07-07   389   1.0    Initial version
29 
------------------------------------------------------------------------------
30 
 
31 
library ieee;
32 
use ieee.std_logic_1164.all;
33 
 
34 
use work.slvtypes.all;
35 
 
36 
package fx2lib is
37 
 
38 
  constant c_fifo_ep2   : slv2 := "00";   -- fifo address: end point 2
39 
  constant c_fifo_ep4   : slv2 := "01";   -- fifo address: end point 4
40 
  constant c_fifo_ep6   : slv2 := "10";   -- fifo address: end point 6
41 
  constant c_fifo_ep8   : slv2 := "11";   -- fifo address: end point 8
42 
 
43 
  type fx2ctl_moni_type is record       -- fx2ctl monitor port
44 
    fifo_ep4 : slbit;                   -- fifo 1 (ep4) active;
45 
    fifo_ep6 : slbit;                   -- fifo 2 (ep6) active;
46 
    fifo_ep8 : slbit;                   -- fifo 3 (ep8) active;
47 
    flag_ep4_empty  : slbit;            -- ep4 empty flag        (latched);
48 
    flag_ep4_almost : slbit;            -- ep4 almost empty flag (latched);
49 
    flag_ep6_full   : slbit;            -- ep6 full flag         (latched);
50 
    flag_ep6_almost : slbit;            -- ep6 almost full flag  (latched);
51 
    flag_ep8_full   : slbit;            -- ep8 full flag         (latched);
52 
    flag_ep8_almost : slbit;            -- ep8 almost full flag  (latched);
53 
    slrd : slbit;                       -- read strobe
54 
    slwr : slbit;                       -- write strobe
55 
    pktend : slbit;                     -- pktend strobe
56 
  end record fx2ctl_moni_type;
57 
 
58 
  constant fx2ctl_moni_init : fx2ctl_moni_type := (
59 
    '0','0','0',                        -- fifo_ep[468]
60 
    '0','0',                            -- flag_ep4_(empty|almost)
61 
    '0','0',                            -- flag_ep6_(full|almost)
62 
    '0','0',                            -- flag_ep8_(full|almost)
63 
    '0','0','0'                         -- slrd, slwr, pktend
64 
  );
65 
 
66 
 
67 
-- -------------------------------------
68 
component fx2_2fifoctl_as is            -- EZ-USB FX2 driver (2 fifo; async)
69 
  generic (
70 
    RXFAWIDTH : positive :=  5;         -- receive  fifo address width
71 
    TXFAWIDTH : positive :=  5;         -- transmit fifo address width
72 
    PETOWIDTH : positive :=  7;         -- packet end time-out counter width
73 
    CCWIDTH :   positive :=  5;         -- chunk counter width
74 
    RXAEMPTY_THRES : natural := 1;      -- threshold for rx aempty flag
75 
    TXAFULL_THRES  : natural := 1;      -- threshold for tx afull flag
76 
    RDPWLDELAY : positive := 5;         -- slrd low  delay in clock cycles
77 
    RDPWHDELAY : positive := 5;         -- slrd high delay in clock cycles
78 
    WRPWLDELAY : positive := 5;         -- slwr low  delay in clock cycles
79 
    WRPWHDELAY : positive := 7;         -- slwr high delay in clock cycles
80 
    FLAGDELAY  : positive := 2);        -- flag delay in clock cycles
81 
  port (
82 
    CLK : in slbit;                     -- clock
83 
    CE_USEC : in slbit;                 -- 1 usec clock enable
84 
    RESET : in slbit := '0';            -- reset
85 
    RXDATA : out slv8;                  -- receive data out
86 
    RXVAL : out slbit;                  -- receive data valid
87 
    RXHOLD : in slbit;                  -- receive data hold
88 
    RXAEMPTY : out slbit;               -- receive almost empty flag
89 
    TXDATA : in slv8;                   -- transmit data in
90 
    TXENA : in slbit;                   -- transmit data enable
91 
    TXBUSY : out slbit;                 -- transmit data busy
92 
    TXAFULL : out slbit;                -- transmit almost full flag
93 
    MONI : out fx2ctl_moni_type;        -- monitor port data
94 
    I_FX2_IFCLK : in slbit;             -- fx2: interface clock
95 
    O_FX2_FIFO : out slv2;              -- fx2: fifo address
96 
    I_FX2_FLAG : in slv4;               -- fx2: fifo flags
97 
    O_FX2_SLRD_N : out slbit;           -- fx2: read enable    (act.low)
98 
    O_FX2_SLWR_N : out slbit;           -- fx2: write enable   (act.low)
99 
    O_FX2_SLOE_N : out slbit;           -- fx2: output enable  (act.low)
100 
    O_FX2_PKTEND_N : out slbit;         -- fx2: packet end     (act.low)
101 
    IO_FX2_DATA : inout slv8            -- fx2: data lines
102 
  );
103 
end component;
104 
 
105 
component fx2_2fifoctl_ic is            -- EZ-USB FX2 driver (2 fifo; int clk)
106 
  generic (
107 
    RXFAWIDTH : positive :=  5;         -- receive  fifo address width
108 
    TXFAWIDTH : positive :=  5;         -- transmit fifo address width
109 
    PETOWIDTH : positive :=  7;         -- packet end time-out counter width
110 
    CCWIDTH :   positive :=  5;         -- chunk counter width
111 
    RXAEMPTY_THRES : natural := 1;      -- threshold for rx aempty flag
112 
    TXAFULL_THRES  : natural := 1);     -- threshold for tx afull flag
113 
  port (
114 
    CLK : in slbit;                     -- clock
115 
    RESET : in slbit := '0';            -- reset
116 
    RXDATA : out slv8;                  -- receive data out
117 
    RXVAL : out slbit;                  -- receive data valid
118 
    RXHOLD : in slbit;                  -- receive data hold
119 
    RXAEMPTY : out slbit;               -- receive almost empty flag
120 
    TXDATA : in slv8;                   -- transmit data in
121 
    TXENA : in slbit;                   -- transmit data enable
122 
    TXBUSY : out slbit;                 -- transmit data busy
123 
    TXAFULL : out slbit;                -- transmit almost full flag
124 
    MONI : out fx2ctl_moni_type;        -- monitor port data
125 
    I_FX2_IFCLK : in slbit;             -- fx2: interface clock
126 
    O_FX2_FIFO : out slv2;              -- fx2: fifo address
127 
    I_FX2_FLAG : in slv4;               -- fx2: fifo flags
128 
    O_FX2_SLRD_N : out slbit;           -- fx2: read enable    (act.low)
129 
    O_FX2_SLWR_N : out slbit;           -- fx2: write enable   (act.low)
130 
    O_FX2_SLOE_N : out slbit;           -- fx2: output enable  (act.low)
131 
    O_FX2_PKTEND_N : out slbit;         -- fx2: packet end     (act.low)
132 
    IO_FX2_DATA : inout slv8            -- fx2: data lines
133 
  );
134 
end component;
135 
 
136 
component fx2_3fifoctl_ic is            -- EZ-USB FX2 driver (3 fifo; int clk)
137 
  generic (
138 
    RXFAWIDTH : positive :=  5;         -- receive  fifo address width
139 
    TXFAWIDTH : positive :=  5;         -- transmit fifo address width
140 
    PETOWIDTH : positive :=  7;         -- packet end time-out counter width
141 
    CCWIDTH :   positive :=  5;         -- chunk counter width
142 
    RXAEMPTY_THRES : natural := 1;      -- threshold for rx aempty flag
143 
    TXAFULL_THRES  : natural := 1;      -- threshold for tx afull flag
144 
    TX2AFULL_THRES : natural := 1);     -- threshold for tx2 afull flag
145 
  port (
146 
    CLK : in slbit;                     -- clock
147 
    RESET : in slbit := '0';            -- reset
148 
    RXDATA : out slv8;                  -- receive data out
149 
    RXVAL : out slbit;                  -- receive data valid
150 
    RXHOLD : in slbit;                  -- receive data hold
151 
    RXAEMPTY : out slbit;               -- receive almost empty flag
152 
    TXDATA : in slv8;                   -- transmit 1 data in
153 
    TXENA : in slbit;                   -- transmit 1 data enable
154 
    TXBUSY : out slbit;                 -- transmit 1 data busy
155 
    TXAFULL : out slbit;                -- transmit 1 almost full flag
156 
    TX2DATA : in slv8;                  -- transmit 2 data in
157 
    TX2ENA : in slbit;                  -- transmit 2 data enable
158 
    TX2BUSY : out slbit;                -- transmit 2 data busy
159 
    TX2AFULL : out slbit;               -- transmit 2 almost full flag
160 
    MONI : out fx2ctl_moni_type;        -- monitor port data
161 
    I_FX2_IFCLK : in slbit;             -- fx2: interface clock
162 
    O_FX2_FIFO : out slv2;              -- fx2: fifo address
163 
    I_FX2_FLAG : in slv4;               -- fx2: fifo flags
164 
    O_FX2_SLRD_N : out slbit;           -- fx2: read enable    (act.low)
165 
    O_FX2_SLWR_N : out slbit;           -- fx2: write enable   (act.low)
166 
    O_FX2_SLOE_N : out slbit;           -- fx2: output enable  (act.low)
167 
    O_FX2_PKTEND_N : out slbit;         -- fx2: packet end     (act.low)
168 
    IO_FX2_DATA : inout slv8            -- fx2: data lines
169 
  );
170 
end component;
171 
 
172 
end package fx2lib;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.