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-- $Id: sys_tst_snhumanio_n3.vhd 433 2011-11-27 22:04:39Z mueller $

--

-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>

--

-- This program is free software; you may redistribute and/or modify it under

-- the terms of the GNU General Public License as published by the Free

-- Software Foundation, either version 2, or at your option any later version.

--

-- This program is distributed in the hope that it will be useful, but

-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY

-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

-- for complete details.

--

------------------------------------------------------------------------------

-- Module Name:    sys_tst_snhumanio_n3 - syn

-- Description:    snhumanio tester design for nexys3

--

-- Dependencies:   vlib/genlib/clkdivce

--                 bplib/bpgen/sn_humanio

--                 tst_snhumanio

--                 vlib/nxcramlib/nx_cram_dummy

--

-- Test bench:     -

--

-- Target Devices: generic

-- Tool versions:  xst 13.1; ghdl 0.29

--

-- Synthesized (xst):

-- Date         Rev  ise         Target      flop lutl lutm slic t peri

-- 2011-11-27   433 13.1    O40d xc3s1200e-4  151  195    -   65 t  6.1

--

-- Revision History: 

-- Date         Rev Version  Comment

-- 2011-11-27   433   1.0    Initial version

------------------------------------------------------------------------------

-- Usage of Nexys 2 Switches, Buttons, LEDs:

--

library ieee;

use ieee.std_logic_1164.all;

use work.slvtypes.all;

use work.genlib.all;

use work.bpgenlib.all;

use work.nxcramlib.all;

use work.sys_conf.all;

-- ----------------------------------------------------------------------------

entity sys_tst_snhumanio_n3 is          -- top level

                                        -- implements nexys3_aif

  port (

    I_CLK100 : in slbit;                -- 100  MHz clock

    I_RXD : in slbit;                   -- receive data (board view)

    O_TXD : out slbit;                  -- transmit data (board view)

    I_SWI : in slv8;                    -- n3 switches

    I_BTN : in slv5;                    -- n3 buttons

    O_LED : out slv8;                   -- n3 leds

    O_ANO_N : out slv4;                 -- 7 segment disp: anodes   (act.low)

    O_SEG_N : out slv8;                 -- 7 segment disp: segments (act.low)

    O_MEM_CE_N : out slbit;             -- cram: chip enable   (act.low)

    O_MEM_BE_N : out slv2;              -- cram: byte enables  (act.low)

    O_MEM_WE_N : out slbit;             -- cram: write enable  (act.low)

    O_MEM_OE_N : out slbit;             -- cram: output enable (act.low)

    O_MEM_ADV_N  : out slbit;           -- cram: address valid (act.low)

    O_MEM_CLK : out slbit;              -- cram: clock

    O_MEM_CRE : out slbit;              -- cram: command register enable

    I_MEM_WAIT : in slbit;              -- cram: mem wait

    O_MEM_ADDR  : out slv23;            -- cram: address lines

    IO_MEM_DATA : inout slv16;          -- cram: data lines

    O_PPCM_CE_N : out slbit;            -- ppcm: ...

    O_PPCM_RST_N : out slbit            -- ppcm: ...

  );

end sys_tst_snhumanio_n3;

architecture syn of sys_tst_snhumanio_n3 is

  signal CLK :   slbit := '0';

  signal SWI     : slv8  := (others=>'0');

  signal BTN     : slv5  := (others=>'0');

  signal LED     : slv8  := (others=>'0');

  signal DSP_DAT : slv16 := (others=>'0');

  signal DSP_DP  : slv4  := (others=>'0');

  signal RESET   : slbit := '0';

  signal CE_MSEC : slbit := '0';

begin

  RESET <= '0';                         -- so far not used

  CLK <= I_CLK100;

  CLKDIV : clkdivce

    generic map (

      CDUWIDTH => 7,

      USECDIV  => 100,

      MSECDIV  => 1000)

    port map (

      CLK     => CLK,

      CE_USEC => open,

      CE_MSEC => CE_MSEC

    );

  HIO : sn_humanio

    generic map (

      BWIDTH   => 5,

      DEBOUNCE => sys_conf_hio_debounce)

    port map (

      CLK     => CLK,

      RESET   => RESET,

      CE_MSEC => CE_MSEC,

      SWI     => SWI,

      BTN     => BTN,

      LED     => LED,

      DSP_DAT => DSP_DAT,

      DSP_DP  => DSP_DP,

      I_SWI   => I_SWI,

      I_BTN   => I_BTN,

      O_LED   => O_LED,

      O_ANO_N => O_ANO_N,

      O_SEG_N => O_SEG_N

    );

  HIOTEST : entity work.tst_snhumanio

    generic map (

      BWIDTH => 5)

    port map (

      CLK     => CLK,

      RESET   => RESET,

      CE_MSEC => CE_MSEC,

      SWI     => SWI,

      BTN     => BTN,

      LED     => LED,

      DSP_DAT => DSP_DAT,

      DSP_DP  => DSP_DP

    );

  O_TXD <= I_RXD;

  SRAM_PROT : nx_cram_dummy            -- connect CRAM to protection dummy

    port map (

      O_MEM_CE_N  => O_MEM_CE_N,

      O_MEM_BE_N  => O_MEM_BE_N,

      O_MEM_WE_N  => O_MEM_WE_N,

      O_MEM_OE_N  => O_MEM_OE_N,

      O_MEM_ADV_N => O_MEM_ADV_N,

      O_MEM_CLK   => O_MEM_CLK,

      O_MEM_CRE   => O_MEM_CRE,

      I_MEM_WAIT  => I_MEM_WAIT,

      O_MEM_ADDR  => O_MEM_ADDR,

      IO_MEM_DATA => IO_MEM_DATA

    );

  O_PPCM_CE_N  <= '1';                  -- keep parallel PCM memory disabled

  O_PPCM_RST_N <= '1';                  --

end syn;