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-- $Id: xlib.vhd 314 2010-07-09 17:38:41Z mueller $
--
-- Copyright 2007-2008 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name:   xlib
-- Description:    Xilinx specific components
--
-- Dependencies:   -
-- Tool versions:  xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History: 
-- Date         Rev Version  Comment
-- 2008-05-23   149   1.0.4  add iob_io(_gen)
-- 2008-05-22   148   1.0.3  add iob_keeper(_gen);
-- 2008-05-18   147   1.0.2  add PULL generic to iob_reg_io(_gen)
-- 2007-12-16   101   1.0.1  add INIT generic ports
-- 2007-12-08   100   1.0    Initial version 
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
 
package xlib is
 
component iob_reg_i is                  -- registered IOB, input
  generic (
    INIT : slbit := '0');               -- initial state
  port (
    CLK  : in slbit;                    -- clock
    CE   : in slbit := '1';             -- clock enable
    DI   : out slbit;                   -- input data
    PAD  : in slbit                     -- i/o pad
  );
end component;
 
component iob_reg_i_gen is              -- registered IOB, input, vector
  generic (
    DWIDTH : positive := 16;            -- data port width
    INIT : slbit := '0');               -- initial state
  port (
    CLK  : in slbit;                    -- clock
    CE   : in slbit := '1';             -- clock enable
    DI   : out slv(DWIDTH-1 downto 0);  -- input data
    PAD  : in slv(DWIDTH-1 downto 0)    -- i/o pad
  );
end component;
 
component iob_reg_o is                  -- registered IOB, output
  generic (
    INIT : slbit := '0');               -- initial state
  port (
    CLK  : in slbit;                    -- clock
    CE   : in slbit := '1';             -- clock enable
    DO   : in slbit;                    -- output data
    PAD  : out slbit                    -- i/o pad
  );
end component;
 
component iob_reg_o_gen is              -- registered IOB, output, vector
  generic (
    DWIDTH : positive := 16;            -- data port width
    INIT : slbit := '0');               -- initial state
  port (
    CLK  : in slbit;                    -- clock
    CE   : in slbit := '1';             -- clock enable
    DO   : in slv(DWIDTH-1 downto 0);   -- output data
    PAD  : out slv(DWIDTH-1 downto 0)   -- i/o pad
  );
end component;
 
component iob_reg_io is                 -- registered IOB, in/output
  generic (
    INITI : slbit := '0';               -- initial state ( in flop)
    INITO : slbit := '0';               -- initial state (out flop)
    INITE : slbit := '0';               -- initial state ( oe flop)
    PULL : string := "NONE");           -- pull-up,-down or keeper
  port (
    CLK  : in slbit;                    -- clock
    CEI  : in slbit := '1';             -- clock enable ( in flops)
    CEO  : in slbit := '1';             -- clock enable (out flops)
    OE   : in slbit;                    -- output enable
    DI   : out slbit;                   -- input data   (read from pad)
    DO   : in slbit;                    -- output data  (write  to pad)
    PAD  : inout slbit                  -- i/o pad
  );
end component;
 
component iob_reg_io_gen is             -- registered IOB, in/output, vector
  generic (
    DWIDTH : positive := 16;            -- data port width
    INITI : slbit := '0';               -- initial state ( in flop)
    INITO : slbit := '0';               -- initial state (out flop)
    INITE : slbit := '0';               -- initial state ( oe flop)
    PULL : string := "NONE");           -- pull-up,-down or keeper
  port (
    CLK  : in slbit;                    -- clock
    CEI  : in slbit := '1';             -- clock enable ( in flops)
    CEO  : in slbit := '1';             -- clock enable (out flops)
    OE   : in slbit;                    -- output enable
    DI   : out slv(DWIDTH-1 downto 0);  -- input data   (read from pad)
    DO   : in slv(DWIDTH-1 downto 0);   -- output data  (write  to pad)
    PAD  : inout slv(DWIDTH-1 downto 0)  -- i/o pad
  );
end component;
 
component iob_io is                     -- un-registered IOB, in/output
  generic (
    PULL : string := "NONE");           -- pull-up,-down or keeper
  port (
    OE   : in slbit;                    -- output enable
    DI   : out slbit;                   -- input data   (read from pad)
    DO   : in slbit;                    -- output data  (write  to pad)
    PAD  : inout slbit                  -- i/o pad
  );
end component;
 
component iob_io_gen is                 -- un-registered IOB, in/output, vector
  generic (
    DWIDTH : positive := 16;            -- data port width
    PULL : string := "NONE");           -- pull-up,-down or keeper
  port (
    OE   : in slbit;                    -- output enable
    DI   : out slv(DWIDTH-1 downto 0);  -- input data   (read from pad)
    DO   : in slv(DWIDTH-1 downto 0);   -- output data  (write  to pad)
    PAD  : inout slv(DWIDTH-1 downto 0)  -- i/o pad
  );
end component;
 
component iob_keeper is                 -- keeper for IOB
  port (
    PAD  : inout slbit                  -- i/o pad
  );
end component;
 
component iob_keeper_gen is             -- keeper for IOB, vector
  generic (
    DWIDTH : positive := 16);           -- data port width
  port (
    PAD  : inout slv(DWIDTH-1 downto 0)  -- i/o pad
  );
end component;
 
end xlib;

Line No.	Rev	Author	Line
1	2	wfjm	`-- $Id: xlib.vhd 314 2010-07-09 17:38:41Z mueller $`
2			`--`
3			`-- Copyright 2007-2008 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>`
4			`--`
5			`-- This program is free software; you may redistribute and/or modify it under`
6			`-- the terms of the GNU General Public License as published by the Free`
7			`-- Software Foundation, either version 2, or at your option any later version.`
8			`--`
9			`-- This program is distributed in the hope that it will be useful, but`
10			`-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY`
11			`-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
12			`-- for complete details.`
13			`--`
14			`------------------------------------------------------------------------------`
15			`-- Package Name: xlib`
16			`-- Description: Xilinx specific components`
17			`--`
18			`-- Dependencies: -`
19			`-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25`
20			`-- Revision History:`
21			`-- Date Rev Version Comment`
22			`-- 2008-05-23 149 1.0.4 add iob_io(_gen)`
23			`-- 2008-05-22 148 1.0.3 add iob_keeper(_gen);`
24			`-- 2008-05-18 147 1.0.2 add PULL generic to iob_reg_io(_gen)`
25			`-- 2007-12-16 101 1.0.1 add INIT generic ports`
26			`-- 2007-12-08 100 1.0 Initial version`
27			`------------------------------------------------------------------------------`
28
29			`library ieee;`
30			`use ieee.std_logic_1164.all;`
31
32			`use work.slvtypes.all;`
33
34			`package xlib is`
35
36			`component iob_reg_i is -- registered IOB, input`
37			`generic (`
38			`INIT : slbit := '0'); -- initial state`
39			`port (`
40			`CLK : in slbit; -- clock`
41			`CE : in slbit := '1'; -- clock enable`
42			`DI : out slbit; -- input data`
43			`PAD : in slbit -- i/o pad`
44			`);`
45			`end component;`
46
47			`component iob_reg_i_gen is -- registered IOB, input, vector`
48			`generic (`
49			`DWIDTH : positive := 16; -- data port width`
50			`INIT : slbit := '0'); -- initial state`
51			`port (`
52			`CLK : in slbit; -- clock`
53			`CE : in slbit := '1'; -- clock enable`
54			`DI : out slv(DWIDTH-1 downto 0); -- input data`
55			`PAD : in slv(DWIDTH-1 downto 0) -- i/o pad`
56			`);`
57			`end component;`
58
59			`component iob_reg_o is -- registered IOB, output`
60			`generic (`
61			`INIT : slbit := '0'); -- initial state`
62			`port (`
63			`CLK : in slbit; -- clock`
64			`CE : in slbit := '1'; -- clock enable`
65			`DO : in slbit; -- output data`
66			`PAD : out slbit -- i/o pad`
67			`);`
68			`end component;`
69
70			`component iob_reg_o_gen is -- registered IOB, output, vector`
71			`generic (`
72			`DWIDTH : positive := 16; -- data port width`
73			`INIT : slbit := '0'); -- initial state`
74			`port (`
75			`CLK : in slbit; -- clock`
76			`CE : in slbit := '1'; -- clock enable`
77			`DO : in slv(DWIDTH-1 downto 0); -- output data`
78			`PAD : out slv(DWIDTH-1 downto 0) -- i/o pad`
79			`);`
80			`end component;`
81
82			`component iob_reg_io is -- registered IOB, in/output`
83			`generic (`
84			`INITI : slbit := '0'; -- initial state ( in flop)`
85			`INITO : slbit := '0'; -- initial state (out flop)`
86			`INITE : slbit := '0'; -- initial state ( oe flop)`
87			`PULL : string := "NONE"); -- pull-up,-down or keeper`
88			`port (`
89			`CLK : in slbit; -- clock`
90			`CEI : in slbit := '1'; -- clock enable ( in flops)`
91			`CEO : in slbit := '1'; -- clock enable (out flops)`
92			`OE : in slbit; -- output enable`
93			`DI : out slbit; -- input data (read from pad)`
94			`DO : in slbit; -- output data (write to pad)`
95			`PAD : inout slbit -- i/o pad`
96			`);`
97			`end component;`
98
99			`component iob_reg_io_gen is -- registered IOB, in/output, vector`
100			`generic (`
101			`DWIDTH : positive := 16; -- data port width`
102			`INITI : slbit := '0'; -- initial state ( in flop)`
103			`INITO : slbit := '0'; -- initial state (out flop)`
104			`INITE : slbit := '0'; -- initial state ( oe flop)`
105			`PULL : string := "NONE"); -- pull-up,-down or keeper`
106			`port (`
107			`CLK : in slbit; -- clock`
108			`CEI : in slbit := '1'; -- clock enable ( in flops)`
109			`CEO : in slbit := '1'; -- clock enable (out flops)`
110			`OE : in slbit; -- output enable`
111			`DI : out slv(DWIDTH-1 downto 0); -- input data (read from pad)`
112			`DO : in slv(DWIDTH-1 downto 0); -- output data (write to pad)`
113			`PAD : inout slv(DWIDTH-1 downto 0) -- i/o pad`
114			`);`
115			`end component;`
116
117			`component iob_io is -- un-registered IOB, in/output`
118			`generic (`
119			`PULL : string := "NONE"); -- pull-up,-down or keeper`
120			`port (`
121			`OE : in slbit; -- output enable`
122			`DI : out slbit; -- input data (read from pad)`
123			`DO : in slbit; -- output data (write to pad)`
124			`PAD : inout slbit -- i/o pad`
125			`);`
126			`end component;`
127
128			`component iob_io_gen is -- un-registered IOB, in/output, vector`
129			`generic (`
130			`DWIDTH : positive := 16; -- data port width`
131			`PULL : string := "NONE"); -- pull-up,-down or keeper`
132			`port (`
133			`OE : in slbit; -- output enable`
134			`DI : out slv(DWIDTH-1 downto 0); -- input data (read from pad)`
135			`DO : in slv(DWIDTH-1 downto 0); -- output data (write to pad)`
136			`PAD : inout slv(DWIDTH-1 downto 0) -- i/o pad`
137			`);`
138			`end component;`
139
140			`component iob_keeper is -- keeper for IOB`
141			`port (`
142			`PAD : inout slbit -- i/o pad`
143			`);`
144			`end component;`
145
146			`component iob_keeper_gen is -- keeper for IOB, vector`
147			`generic (`
148			`DWIDTH : positive := 16); -- data port width`
149			`port (`
150			`PAD : inout slv(DWIDTH-1 downto 0) -- i/o pad`
151			`);`
152			`end component;`
153
154			`end xlib;`

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[/] [w11/] [tags/] [w11a_V0.61/] [rtl/] [vlib/] [xlib/] [xlib.vhd] - Blame information for rev 2