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-- $Id: tb_pdp11core.vhd 444 2011-12-25 10:04:58Z mueller $
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--
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-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: tb_pdp11core - sim
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-- Description: Test bench for pdp11_core
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--
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-- Dependencies: simlib/simclk
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-- tbd_pdp11core [UUT]
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-- pdp11_intmap
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--
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-- To test: pdp11_core
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--
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-- Target Devices: generic
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-- Tool versions: ghdl 0.18-0.29; ISim 11.3
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--
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-- Verified (with tb_pdp11core_stim.dat):
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-- Date Rev Code ghdl ise Target Comment
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-- 2010-12-30 351 - 0.29 - - u:ok
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-- 2010-12-30 351 _ssim 0.29 12.1 M53d xc3s1000 u:ok
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-- 2010-06-20 308 - 0.29 - - u:ok
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-- 2009-11-22 252 - 0.26 - - u:ok
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-- 2007-12-30 107 - 0.25 - - u:ok
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-- 2007-10-26 92 _tsim 0.26 8.1.03 I27 xc3s1000 c:fail -> blog_ghdl
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-- 2007-10-26 92 _tsim 0.26 9.2.02 J39 xc3s1000 d:ok (full tsim!)
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-- 2007-10-26 92 _tsim 0.26 9.1 J30 xc3s1000 d:ok (full tsim!)
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-- 2007-10-26 92 _tsim 0.26 8.2.03 I34 xc3s1000 d:ok (full tsim!)
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-- 2007-10-26 92 _fsim 0.26 8.2.03 I34 xc3s1000 d:ok
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-- 2007-10-26 92 _ssim 0.26 8.2.03 I34 xc3s1000 d:ok
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-- 2007-10-08 88 _ssim 0.18 8.2.03 I34 xc3s1000 d:ok
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-- 2007-10-08 88 _ssim 0.18 9.1 J30 xc3s1000 d:ok
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-- 2007-10-08 88 _ssim 0.18 9.2.02 J39 xc3s1000 d:ok
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-- 2007-10-07 88 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok
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-- 2007-10-07 88 _ssim 0.26 8.1 I24 xc3s1000 c:fail -> blog_webpack
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-- 2007-10-07 88 - 0.26 - - c:ok
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2011-12-23 444 1.4 use new simclk/simclkcnt
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-- 2011-11-18 427 1.3.2 now numeric_std clean
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-- 2011-01-02 352 1.3.1 rename .cpmon->.rlmon
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-- 2010-12-30 351 1.3 rename tb_pdp11_core -> tb_pdp11core
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-- 2010-06-20 308 1.2.2 add wibrb, ribr, wibr commands for ibr accesses
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-- 2010-06-20 307 1.2.1 add CP_ADDR_racc, CP_ADDR_be to tbd interface
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-- 2010-06-13 305 1.2 add CP_CNTL_rnum and CP_ADDR_...; emulate old
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-- 'sta' behaviour with new 'stapc' command; rename
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-- lal,lah -> wal,wah and implement locally; new
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-- output format with cpfunc name
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-- 2010-06-05 301 1.1.14 renamed .rpmon -> .rbmon
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-- 2010-04-24 281 1.1.13 use direct instatiation for tbd_
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-- 2009-11-28 253 1.1.12 add hack for ISim 11.3
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-- 2009-05-10 214 1.1.11 add .scntl command (set/clear SB_CNTL bits)
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-- 2008-08-29 163 1.1.10 allow, but ignore, the wtlam command
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-- 2008-05-03 143 1.1.9 rename _cpursta->_cpurust
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-- 2008-04-27 140 1.1.8 use cpursta interface, remove cpufail
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-- 2008-04-19 137 1.1.7 use SB_CLKCYCLE now
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-- 2008-03-24 129 1.1.6 CLK_CYCLE now 31 bits
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-- 2008-03-02 121 1.1.5 redo sta,cont,wtgo commands; sta,cont now wait for
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-- command completion, wtgo waits for CPU to halt.
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-- added .cerr,.merr directive, check cmd(m)err state
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-- added .sdef as ignored directive
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-- 2008-02-24 119 1.1.4 added lah,rps,wps command
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-- 2008-01-26 114 1.1.3 add handling of d=val,msk
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-- 2008-01-06 111 1.1.2 remove .eireq, EI's now handled in tbd_pdp11_core
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-- 2007-10-26 92 1.0.2 use DONE timestamp at end of execution
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-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
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-- 2007-09-02 79 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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use work.slvtypes.all;
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use work.simlib.all;
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use work.simbus.all;
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use work.pdp11_sim.all;
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use work.pdp11.all;
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entity tb_pdp11core is
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end tb_pdp11core;
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architecture sim of tb_pdp11core is
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signal CLK : slbit := '0';
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signal RESET : slbit := '0';
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signal UNUSEDSIGNAL : slbit := '0'; -- FIXME: hack to make ISim 11.3 happy
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signal CP_CNTL_req : slbit := '0';
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signal CP_CNTL_func : slv5 := (others=>'0');
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signal CP_CNTL_rnum : slv3 := (others=>'0');
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signal CP_ADDR_addr : slv22_1 := (others=>'0');
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signal CP_ADDR_racc : slbit := '0';
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signal CP_ADDR_be : slv2 := "11";
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signal CP_ADDR_ena_22bit : slbit := '0';
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signal CP_ADDR_ena_ubmap : slbit := '0';
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signal CP_DIN : slv16 := (others=>'0');
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signal CP_STAT_cmdbusy : slbit := '0';
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signal CP_STAT_cmdack : slbit := '0';
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signal CP_STAT_cmderr : slbit := '0';
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signal CP_STAT_cmdmerr : slbit := '0';
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signal CP_STAT_cpugo : slbit := '0';
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signal CP_STAT_cpustep : slbit := '0';
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signal CP_STAT_cpuhalt : slbit := '0';
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signal CP_STAT_cpurust : slv4 := (others=>'0');
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signal CP_DOUT : slv16 := (others=>'0');
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signal CLK_STOP : slbit := '0';
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signal CLK_CYCLE : integer := 0;
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signal R_CHKDAT : slv16 := (others=>'0');
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signal R_CHKMSK : slv16 := (others=>'0');
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signal R_CHKREQ : slbit := '0';
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signal R_WAITCMD : slbit := '0';
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signal R_WAITSTEP : slbit := '0';
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signal R_WAITGO : slbit := '0';
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signal R_WAITOK : slbit := '0';
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signal R_CP_STAT : cp_stat_type := cp_stat_init;
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signal R_CP_DOUT : slv16 := (others=>'0');
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begin
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CLKGEN : simclk
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generic map (
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PERIOD => clock_period,
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OFFSET => clock_offset)
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port map (
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CLK => CLK,
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CLK_STOP => CLK_STOP
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);
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CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
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UUT: entity work.tbd_pdp11core
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port map (
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CLK => CLK,
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RESET => RESET,
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CP_CNTL_req => CP_CNTL_req,
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CP_CNTL_func => CP_CNTL_func,
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CP_CNTL_rnum => CP_CNTL_rnum,
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CP_ADDR_addr => CP_ADDR_addr,
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CP_ADDR_racc => CP_ADDR_racc,
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CP_ADDR_be => CP_ADDR_be,
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CP_ADDR_ena_22bit => CP_ADDR_ena_22bit,
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CP_ADDR_ena_ubmap => CP_ADDR_ena_ubmap,
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CP_DIN => CP_DIN,
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CP_STAT_cmdbusy => CP_STAT_cmdbusy,
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CP_STAT_cmdack => CP_STAT_cmdack,
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CP_STAT_cmderr => CP_STAT_cmderr,
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CP_STAT_cmdmerr => CP_STAT_cmdmerr,
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CP_STAT_cpugo => CP_STAT_cpugo,
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CP_STAT_cpustep => CP_STAT_cpustep,
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CP_STAT_cpuhalt => CP_STAT_cpuhalt,
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CP_STAT_cpurust => CP_STAT_cpurust,
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CP_DOUT => CP_DOUT
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);
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proc_stim: process
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file ifile : text open read_mode is "tb_pdp11core_stim";
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variable iline : line;
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variable oline : line;
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variable idelta : integer := 0;
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variable idummy : integer := 0;
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variable dcycle : integer := 0;
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variable irqline : integer := 0;
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variable ireq : boolean := false;
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variable ifunc : slv5 := (others=>'0');
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variable irnum : slv3 := (others=>'0');
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variable idin : slv16 := (others=>'0');
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variable imsk : slv16 := (others=>'1');
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variable ichk : boolean := false;
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variable idosta: slbit := '0';
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variable ok : boolean;
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variable dname : string(1 to 6) := (others=>' ');
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variable rind : integer := 0;
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variable nblk : integer := 0;
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variable xmicmd : string(1 to 3) := (others=>' ');
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variable iwtstp : boolean := false;
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variable iwtgo : boolean := false;
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variable icerr : integer := 0;
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variable imerr : integer := 0;
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variable to_cmd : integer := 50;
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variable to_stp : integer := 100;
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variable to_go : integer := 5000;
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variable ien : slbit := '0';
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variable ibit : integer := 0;
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variable imemi : boolean := false;
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variable ioff : slv6 := (others=>'0');
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variable idoibr : boolean := false;
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variable r_addr : slv22_1 := (others=>'0');
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variable r_ena_22bit : slbit := '0';
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variable r_ena_ubmap : slbit := '0';
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variable r_ibrbase : slv(c_ibrb_ibf_base) := (others=>'0');
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variable r_ibrbe : slv2 := (others=>'0');
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begin
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| 213 |
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SB_CNTL <= (others=>'L');
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wait for clock_offset - setup_time;
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| 217 |
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RESET <= '1';
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wait for clock_period;
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| 220 |
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RESET <= '0';
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wait for 9*clock_period;
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| 223 |
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file_loop: while not endfile(ifile) loop
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| 224 |
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| 225 |
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-- this logic is a quick hack to implement the 'stapc' command
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| 226 |
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if idosta = '0' then
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| 227 |
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readline (ifile, iline);
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| 228 |
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| 229 |
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iwtstp := false;
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| 230 |
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iwtgo := false;
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| 231 |
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| 232 |
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if nblk>0 and -- outstanding [rw]mi lines ?
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| 233 |
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iline'length>=3 and -- and 3 leading blanks
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| 234 |
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iline(iline'left to iline'left+2)=" " then
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| 235 |
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nblk := nblk - 1; -- than fill [rw]mi command in again
|
| 236 |
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iline(iline'left to iline'left+2) := xmicmd;
|
| 237 |
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end if;
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| 238 |
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| 239 |
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readcomment(iline, ok);
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| 240 |
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next file_loop when ok;
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| 241 |
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| 242 |
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readword(iline, dname, ok);
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| 243 |
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| 244 |
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else
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| 245 |
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idosta := '0';
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| 246 |
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dname := "sta ";
|
| 247 |
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ok := true;
|
| 248 |
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end if;
|
| 249 |
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|
| 250 |
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if ok then
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| 251 |
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| 252 |
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case dname is
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| 253 |
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when "rsp " => dname := "rr6 "; -- rsp -> rr6
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| 254 |
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when "rpc " => dname := "rr7 "; -- rpc -> rr7
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| 255 |
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when "wsp " => dname := "wr6 "; -- wsp -> wr6
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| 256 |
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when "wpc " => dname := "wr7 "; -- wpc -> wr7
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| 257 |
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when others => null;
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| 258 |
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end case;
|
| 259 |
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| 260 |
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rind := character'pos(dname(3)) - character'pos('0');
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| 261 |
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| 262 |
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if (dname(1)='r' or dname(1)='w') and -- check for [rw]r[0-7]
|
| 263 |
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dname(2)='r' and
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| 264 |
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(rind>=0 and rind<=7) then
|
| 265 |
|
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dname(3) := '|'; -- replace with [rw]r|
|
| 266 |
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end if;
|
| 267 |
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|
| 268 |
|
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if dname(1) = '.' then
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| 269 |
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case dname is
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| 270 |
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when ".mode " => -- .mode
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| 271 |
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readword_ea(iline, dname);
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| 272 |
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assert dname="pdpcp "
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| 273 |
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report "assert .mode == pdpcp" severity failure;
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| 274 |
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| 275 |
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when ".reset" => -- .reset
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| 276 |
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write(oline, string'(".reset"));
|
| 277 |
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writeline(output, oline);
|
| 278 |
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RESET <= '1';
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| 279 |
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wait for clock_period;
|
| 280 |
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| 281 |
|
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RESET <= '0';
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| 282 |
|
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wait for 9*clock_period;
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| 283 |
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| 284 |
|
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when ".wait " => -- .wait
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| 285 |
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read_ea(iline, idelta);
|
| 286 |
|
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wait for idelta*clock_period;
|
| 287 |
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| 288 |
|
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when ".tocmd" => -- .tocmd
|
| 289 |
|
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read_ea(iline, idelta);
|
| 290 |
|
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to_cmd := idelta;
|
| 291 |
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| 292 |
|
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when ".tostp" => -- .tostp
|
| 293 |
|
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read_ea(iline, idelta);
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| 294 |
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to_stp := idelta;
|
| 295 |
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| 296 |
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when ".togo " => -- .togo
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| 297 |
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read_ea(iline, idelta);
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| 298 |
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to_go := idelta;
|
| 299 |
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| 300 |
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when ".sdef " => -- .sdef (ignore it)
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| 301 |
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readempty(iline);
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| 302 |
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| 303 |
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when ".cerr " => -- .cerr
|
| 304 |
|
|
read_ea(iline, icerr);
|
| 305 |
|
|
when ".merr " => -- .merr
|
| 306 |
|
|
read_ea(iline, imerr);
|
| 307 |
|
|
|
| 308 |
|
|
when ".anena" => -- .anena (ignore it)
|
| 309 |
|
|
readempty(iline);
|
| 310 |
9 |
wfjm |
when ".rlmon" => -- .rlmon (ignore it)
|
| 311 |
2 |
wfjm |
readempty(iline);
|
| 312 |
|
|
when ".rbmon" => -- .rbmon (ignore it)
|
| 313 |
|
|
readempty(iline);
|
| 314 |
|
|
|
| 315 |
|
|
when ".scntl" => -- .scntl
|
| 316 |
|
|
read_ea(iline, ibit);
|
| 317 |
|
|
read_ea(iline, ien);
|
| 318 |
|
|
assert (ibit>=SB_CNTL'low and ibit<=SB_CNTL'high)
|
| 319 |
|
|
report "assert bit number in range of SB_CNTL"
|
| 320 |
|
|
severity failure;
|
| 321 |
|
|
if ien = '1' then
|
| 322 |
|
|
SB_CNTL(ibit) <= 'H';
|
| 323 |
|
|
else
|
| 324 |
|
|
SB_CNTL(ibit) <= 'L';
|
| 325 |
|
|
end if;
|
| 326 |
|
|
|
| 327 |
|
|
when others => -- bad directive
|
| 328 |
|
|
write(oline, string'("?? unknown directive: "));
|
| 329 |
|
|
write(oline, dname);
|
| 330 |
|
|
writeline(output, oline);
|
| 331 |
|
|
report "aborting" severity failure;
|
| 332 |
|
|
end case;
|
| 333 |
|
|
|
| 334 |
|
|
testempty_ea(iline);
|
| 335 |
|
|
next file_loop;
|
| 336 |
|
|
|
| 337 |
|
|
else
|
| 338 |
|
|
|
| 339 |
|
|
ireq := true;
|
| 340 |
|
|
ifunc := c_cpfunc_noop;
|
| 341 |
|
|
irnum := "000";
|
| 342 |
|
|
ichk := false;
|
| 343 |
|
|
idin := (others=>'0');
|
| 344 |
|
|
imsk := (others=>'1');
|
| 345 |
|
|
imemi := false;
|
| 346 |
|
|
idoibr := false;
|
| 347 |
|
|
|
| 348 |
|
|
case dname is
|
| 349 |
|
|
when "brm " => -- brm
|
| 350 |
|
|
read_ea(iline, nblk);
|
| 351 |
|
|
xmicmd := "rmi";
|
| 352 |
|
|
next file_loop;
|
| 353 |
|
|
when "bwm " => -- bwm
|
| 354 |
|
|
read_ea(iline, nblk);
|
| 355 |
|
|
xmicmd := "wmi";
|
| 356 |
|
|
next file_loop;
|
| 357 |
|
|
|
| 358 |
|
|
when "rr| " => -- rr[0-7]
|
| 359 |
|
|
ifunc := c_cpfunc_rreg;
|
| 360 |
13 |
wfjm |
irnum := slv(to_unsigned(rind, 3));
|
| 361 |
2 |
wfjm |
readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
|
| 362 |
|
|
|
| 363 |
|
|
when "wr| " => -- wr[0-7]
|
| 364 |
|
|
ifunc := c_cpfunc_wreg;
|
| 365 |
13 |
wfjm |
irnum := slv(to_unsigned(rind, 3));
|
| 366 |
2 |
wfjm |
readoct_ea(iline, idin);
|
| 367 |
|
|
|
| 368 |
|
|
-- Note: there are no field definitions for wal, wah, wibrb because
|
| 369 |
|
|
-- there is no corresponding cp command. Therefore the
|
| 370 |
|
|
-- rbus field definitions are used here
|
| 371 |
|
|
when "wal " => -- wal
|
| 372 |
|
|
readoct_ea(iline, idin);
|
| 373 |
|
|
r_addr := (others=>'0'); -- write to al clears ah !!
|
| 374 |
|
|
r_ena_22bit := '0';
|
| 375 |
|
|
r_ena_ubmap := '0';
|
| 376 |
|
|
r_addr(c_al_rbf_addr) := idin(c_al_rbf_addr);
|
| 377 |
|
|
testempty_ea(iline);
|
| 378 |
|
|
next file_loop;
|
| 379 |
|
|
|
| 380 |
|
|
when "wah " => -- wah
|
| 381 |
|
|
readoct_ea(iline, idin);
|
| 382 |
|
|
r_addr(21 downto 16) := idin(c_ah_rbf_addr);
|
| 383 |
|
|
r_ena_22bit := idin(c_ah_rbf_ena_22bit);
|
| 384 |
|
|
r_ena_ubmap := idin(c_ah_rbf_ena_ubmap);
|
| 385 |
|
|
testempty_ea(iline);
|
| 386 |
|
|
next file_loop;
|
| 387 |
|
|
|
| 388 |
|
|
when "wibrb " => -- wibrb
|
| 389 |
|
|
readoct_ea(iline, idin);
|
| 390 |
|
|
r_ibrbase := idin(c_ibrb_ibf_base);
|
| 391 |
|
|
if idin(c_ibrb_ibf_be) /= "00" then
|
| 392 |
|
|
r_ibrbe := idin(c_ibrb_ibf_be);
|
| 393 |
|
|
else
|
| 394 |
|
|
r_ibrbe := "11";
|
| 395 |
|
|
end if;
|
| 396 |
|
|
testempty_ea(iline);
|
| 397 |
|
|
next file_loop;
|
| 398 |
|
|
|
| 399 |
|
|
when "rm " => -- rm
|
| 400 |
|
|
ifunc := c_cpfunc_rmem;
|
| 401 |
|
|
readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
|
| 402 |
|
|
when "rmi " => -- rmi
|
| 403 |
|
|
ifunc := c_cpfunc_rmem;
|
| 404 |
|
|
imemi := true;
|
| 405 |
|
|
readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
|
| 406 |
|
|
|
| 407 |
|
|
when "wm " => -- wm
|
| 408 |
|
|
ifunc := c_cpfunc_wmem;
|
| 409 |
|
|
readoct_ea(iline, idin);
|
| 410 |
|
|
when "wmi " => -- wmi
|
| 411 |
|
|
ifunc := c_cpfunc_wmem;
|
| 412 |
|
|
imemi := true;
|
| 413 |
|
|
readoct_ea(iline, idin);
|
| 414 |
|
|
|
| 415 |
|
|
when "ribr " => -- ribr
|
| 416 |
|
|
ifunc := c_cpfunc_rmem;
|
| 417 |
|
|
idoibr := true;
|
| 418 |
|
|
readoct_ea(iline, ioff);
|
| 419 |
|
|
readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
|
| 420 |
|
|
when "wibr " => -- wibr
|
| 421 |
|
|
ifunc := c_cpfunc_wmem;
|
| 422 |
|
|
idoibr := true;
|
| 423 |
|
|
readoct_ea(iline, ioff);
|
| 424 |
|
|
readoct_ea(iline, idin);
|
| 425 |
|
|
|
| 426 |
|
|
when "rps " => -- rps
|
| 427 |
|
|
ifunc := c_cpfunc_rpsw;
|
| 428 |
|
|
readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
|
| 429 |
|
|
when "wps " => -- wps
|
| 430 |
|
|
ifunc := c_cpfunc_wpsw;
|
| 431 |
|
|
readoct_ea(iline, idin);
|
| 432 |
|
|
|
| 433 |
|
|
-- Note: in old version 'sta addr' was an atomic operation, loading
|
| 434 |
|
|
-- the pc and starting the cpu. Now this is action is two step
|
| 435 |
|
|
-- first a wpc followed by a 'sta'.
|
| 436 |
|
|
when "stapc " => -- stapc
|
| 437 |
|
|
ifunc := c_cpfunc_wreg;
|
| 438 |
|
|
irnum := c_gpr_pc;
|
| 439 |
|
|
readoct_ea(iline, idin);
|
| 440 |
|
|
idosta := '1'; -- request 'sta' to be done next
|
| 441 |
|
|
|
| 442 |
|
|
when "sta " => -- sta
|
| 443 |
|
|
ifunc := c_cpfunc_sta;
|
| 444 |
|
|
when "sto " => -- sto
|
| 445 |
|
|
ifunc := c_cpfunc_sto;
|
| 446 |
|
|
when "cont " => -- cont
|
| 447 |
|
|
ifunc := c_cpfunc_cont;
|
| 448 |
|
|
when "step " => -- step
|
| 449 |
|
|
ifunc := c_cpfunc_step;
|
| 450 |
|
|
iwtstp := true;
|
| 451 |
|
|
when "rst " => -- rst
|
| 452 |
|
|
ifunc := c_cpfunc_rst;
|
| 453 |
|
|
|
| 454 |
|
|
when "wtgo " => -- wtgo
|
| 455 |
|
|
iwtgo := true;
|
| 456 |
|
|
ireq := false; -- no cp request !
|
| 457 |
|
|
|
| 458 |
|
|
when "wtlam " => -- wtlam (ignore it)
|
| 459 |
|
|
readempty(iline);
|
| 460 |
|
|
next file_loop;
|
| 461 |
|
|
|
| 462 |
|
|
when others => -- bad directive
|
| 463 |
|
|
write(oline, string'("?? unknown directive: "));
|
| 464 |
|
|
write(oline, dname);
|
| 465 |
|
|
writeline(output, oline);
|
| 466 |
|
|
report "aborting" severity failure;
|
| 467 |
|
|
end case;
|
| 468 |
|
|
|
| 469 |
|
|
end if;
|
| 470 |
|
|
testempty_ea(iline);
|
| 471 |
|
|
|
| 472 |
|
|
end if;
|
| 473 |
|
|
|
| 474 |
|
|
if idoibr then
|
| 475 |
|
|
CP_ADDR_addr(15 downto 13) <= "111";
|
| 476 |
|
|
CP_ADDR_addr(c_ibrb_ibf_base) <= r_ibrbase;
|
| 477 |
|
|
CP_ADDR_addr(5 downto 1) <= ioff(5 downto 1);
|
| 478 |
|
|
CP_ADDR_racc <= '1';
|
| 479 |
|
|
CP_ADDR_be <= r_ibrbe;
|
| 480 |
|
|
CP_ADDR_ena_22bit <= '0';
|
| 481 |
|
|
CP_ADDR_ena_ubmap <= '0';
|
| 482 |
|
|
else
|
| 483 |
|
|
CP_ADDR_addr <= r_addr;
|
| 484 |
|
|
CP_ADDR_racc <= '0';
|
| 485 |
|
|
CP_ADDR_be <= "11";
|
| 486 |
|
|
CP_ADDR_ena_22bit <= r_ena_22bit;
|
| 487 |
|
|
CP_ADDR_ena_ubmap <= r_ena_ubmap;
|
| 488 |
|
|
end if;
|
| 489 |
|
|
|
| 490 |
|
|
if ireq then
|
| 491 |
|
|
CP_CNTL_req <= '1';
|
| 492 |
|
|
CP_CNTL_func <= ifunc;
|
| 493 |
|
|
CP_CNTL_rnum <= irnum;
|
| 494 |
|
|
end if;
|
| 495 |
|
|
|
| 496 |
|
|
if ichk then
|
| 497 |
|
|
CP_DIN <= (others=>'0');
|
| 498 |
|
|
R_CHKDAT <= idin;
|
| 499 |
|
|
R_CHKMSK <= imsk;
|
| 500 |
|
|
R_CHKREQ <= '1';
|
| 501 |
|
|
else
|
| 502 |
|
|
CP_DIN <= idin;
|
| 503 |
|
|
R_CHKREQ <= '0';
|
| 504 |
|
|
end if;
|
| 505 |
|
|
|
| 506 |
|
|
R_WAITCMD <= '0';
|
| 507 |
|
|
R_WAITSTEP <= '0';
|
| 508 |
|
|
R_WAITGO <= '0';
|
| 509 |
|
|
if iwtgo then
|
| 510 |
|
|
idelta := to_go;
|
| 511 |
|
|
R_WAITGO <= '1';
|
| 512 |
|
|
elsif iwtstp then
|
| 513 |
|
|
idelta := to_stp;
|
| 514 |
|
|
R_WAITSTEP <= '1';
|
| 515 |
|
|
else
|
| 516 |
|
|
idelta := to_cmd;
|
| 517 |
|
|
R_WAITCMD <= '1';
|
| 518 |
|
|
end if;
|
| 519 |
|
|
|
| 520 |
|
|
wait for clock_period;
|
| 521 |
|
|
CP_CNTL_req <= '0';
|
| 522 |
|
|
|
| 523 |
|
|
dcycle := 1;
|
| 524 |
|
|
while idelta>0 and R_WAITOK='0' loop
|
| 525 |
|
|
wait for clock_period;
|
| 526 |
|
|
dcycle := dcycle + 1;
|
| 527 |
|
|
idelta := idelta - 1;
|
| 528 |
|
|
end loop;
|
| 529 |
|
|
|
| 530 |
|
|
if imemi then -- rmi or wmi seen ? then inc ar
|
| 531 |
13 |
wfjm |
r_addr := slv(unsigned(r_addr) + 1);
|
| 532 |
2 |
wfjm |
end if;
|
| 533 |
|
|
|
| 534 |
|
|
write(oline, dcycle, right, 4);
|
| 535 |
|
|
write(oline, string'(" "));
|
| 536 |
|
|
if ireq then
|
| 537 |
|
|
case ifunc is
|
| 538 |
|
|
when c_cpfunc_rreg => write(oline, string'("rreg"));
|
| 539 |
|
|
when c_cpfunc_wreg => write(oline, string'("wreg"));
|
| 540 |
|
|
when c_cpfunc_rpsw => write(oline, string'("rpsw"));
|
| 541 |
|
|
when c_cpfunc_wpsw => write(oline, string'("wpsw"));
|
| 542 |
|
|
when c_cpfunc_rmem =>
|
| 543 |
|
|
if idoibr then
|
| 544 |
|
|
write(oline, string'("ribr"));
|
| 545 |
|
|
else
|
| 546 |
|
|
write(oline, string'("rmem"));
|
| 547 |
|
|
end if;
|
| 548 |
|
|
when c_cpfunc_wmem =>
|
| 549 |
|
|
if idoibr then
|
| 550 |
|
|
write(oline, string'("wibr"));
|
| 551 |
|
|
else
|
| 552 |
|
|
write(oline, string'("wmem"));
|
| 553 |
|
|
end if;
|
| 554 |
|
|
when c_cpfunc_sta => write(oline, string'("sta "));
|
| 555 |
|
|
when c_cpfunc_sto => write(oline, string'("sto "));
|
| 556 |
|
|
when c_cpfunc_cont => write(oline, string'("cont"));
|
| 557 |
|
|
when c_cpfunc_step => write(oline, string'("step"));
|
| 558 |
|
|
when c_cpfunc_rst => write(oline, string'("rst "));
|
| 559 |
|
|
when others =>
|
| 560 |
|
|
write(oline, string'("?"));
|
| 561 |
|
|
writeoct(oline, ifunc, right, 2);
|
| 562 |
|
|
write(oline, string'("?"));
|
| 563 |
|
|
end case;
|
| 564 |
|
|
writeoct(oline, irnum, right, 2);
|
| 565 |
|
|
writeoct(oline, idin, right, 8);
|
| 566 |
|
|
else
|
| 567 |
|
|
write(oline, string'("---- - ------"));
|
| 568 |
|
|
end if;
|
| 569 |
|
|
|
| 570 |
|
|
write(oline, R_CP_STAT.cmdbusy, right, 3);
|
| 571 |
|
|
write(oline, R_CP_STAT.cmdack, right, 2);
|
| 572 |
|
|
write(oline, R_CP_STAT.cmderr, right, 2);
|
| 573 |
|
|
write(oline, R_CP_STAT.cmdmerr, right, 2);
|
| 574 |
|
|
writeoct(oline, R_CP_DOUT, right, 8);
|
| 575 |
|
|
write(oline, R_CP_STAT.cpugo, right, 3);
|
| 576 |
|
|
write(oline, R_CP_STAT.cpustep, right, 2);
|
| 577 |
|
|
write(oline, R_CP_STAT.cpuhalt, right, 2);
|
| 578 |
|
|
writeoct(oline, R_CP_STAT.cpurust, right, 3);
|
| 579 |
|
|
|
| 580 |
|
|
if R_WAITOK = '1' then
|
| 581 |
|
|
if R_CP_STAT.cmderr='1' or icerr=1 then
|
| 582 |
|
|
if R_CP_STAT.cmderr='1' and icerr=0 then
|
| 583 |
|
|
write(oline, string'(" FAIL CMDERR"));
|
| 584 |
|
|
elsif R_CP_STAT.cmderr='1' and icerr=1 then
|
| 585 |
|
|
write(oline, string'(" CHECK CMDERR SEEN"));
|
| 586 |
|
|
elsif R_CP_STAT.cmderr='0' and icerr=1 then
|
| 587 |
|
|
write(oline, string'(" FAIL CMDERR EXPECTED,MISSED"));
|
| 588 |
|
|
end if;
|
| 589 |
|
|
elsif R_CP_STAT.cmdmerr='1' or imerr=1 then
|
| 590 |
|
|
if R_CP_STAT.cmdmerr='1' and imerr=0 then
|
| 591 |
|
|
write(oline, string'(" FAIL CMDMERR"));
|
| 592 |
|
|
elsif R_CP_STAT.cmdmerr='1' and imerr=1 then
|
| 593 |
|
|
write(oline, string'(" CHECK CMDMERR SEEN"));
|
| 594 |
|
|
elsif R_CP_STAT.cmdmerr='0' and imerr=1 then
|
| 595 |
|
|
write(oline, string'(" FAIL CMDMERR EXPECTED,MISSED"));
|
| 596 |
|
|
end if;
|
| 597 |
|
|
elsif R_CHKREQ='1' then
|
| 598 |
|
|
if unsigned((R_CP_DOUT xor R_CHKDAT) and (not R_CHKMSK))=0 then
|
| 599 |
|
|
write(oline, string'(" CHECK OK"));
|
| 600 |
|
|
else
|
| 601 |
|
|
write(oline, string'(" CHECK FAILED, d="));
|
| 602 |
|
|
writeoct(oline, R_CHKDAT, right, 7);
|
| 603 |
|
|
if unsigned(R_CHKMSK)/=0 then
|
| 604 |
|
|
write(oline, string'(","));
|
| 605 |
|
|
writeoct(oline, R_CHKMSK, right, 7);
|
| 606 |
|
|
end if;
|
| 607 |
|
|
end if;
|
| 608 |
|
|
end if;
|
| 609 |
|
|
|
| 610 |
|
|
if iwtgo then
|
| 611 |
|
|
write(oline, string'(" WAIT GO OK "));
|
| 612 |
|
|
elsif iwtstp then
|
| 613 |
|
|
write(oline, string'(" WAIT STEP OK"));
|
| 614 |
|
|
end if;
|
| 615 |
|
|
|
| 616 |
|
|
else
|
| 617 |
|
|
write(oline, string'(" WAIT FAILED (will reset)"));
|
| 618 |
|
|
RESET <= '1';
|
| 619 |
|
|
wait for clock_period;
|
| 620 |
|
|
|
| 621 |
|
|
RESET <= '0';
|
| 622 |
|
|
wait for 9*clock_period;
|
| 623 |
|
|
|
| 624 |
|
|
end if;
|
| 625 |
|
|
writeline(output, oline);
|
| 626 |
|
|
|
| 627 |
|
|
end loop;
|
| 628 |
|
|
|
| 629 |
|
|
wait for 4*clock_period;
|
| 630 |
|
|
CLK_STOP <= '1';
|
| 631 |
|
|
|
| 632 |
17 |
wfjm |
writetimestamp(oline, CLK_CYCLE, ": DONE ");
|
| 633 |
2 |
wfjm |
writeline(output, oline);
|
| 634 |
|
|
|
| 635 |
|
|
wait; -- suspend proc_stim forever
|
| 636 |
|
|
-- clock is stopped, sim will end
|
| 637 |
|
|
|
| 638 |
|
|
end process proc_stim;
|
| 639 |
|
|
|
| 640 |
|
|
proc_moni: process
|
| 641 |
|
|
begin
|
| 642 |
|
|
|
| 643 |
|
|
loop
|
| 644 |
13 |
wfjm |
wait until rising_edge(CLK);
|
| 645 |
2 |
wfjm |
wait for c2out_time;
|
| 646 |
|
|
|
| 647 |
|
|
R_WAITOK <= '0';
|
| 648 |
|
|
if R_WAITCMD = '1' then
|
| 649 |
|
|
if CP_STAT_cmdack = '1' then
|
| 650 |
|
|
R_WAITOK <= '1';
|
| 651 |
|
|
end if;
|
| 652 |
|
|
elsif R_WAITGO = '1' then
|
| 653 |
|
|
if CP_STAT_cmdbusy='0' and CP_STAT_cpugo='0' then
|
| 654 |
|
|
R_WAITOK <= '1';
|
| 655 |
|
|
end if;
|
| 656 |
|
|
elsif R_WAITSTEP = '1' then
|
| 657 |
|
|
if CP_STAT_cmdbusy='0' and CP_STAT_cpustep='0' then
|
| 658 |
|
|
R_WAITOK <= '1';
|
| 659 |
|
|
end if;
|
| 660 |
|
|
end if;
|
| 661 |
|
|
|
| 662 |
|
|
R_CP_STAT.cmdbusy <= CP_STAT_cmdbusy;
|
| 663 |
|
|
R_CP_STAT.cmdack <= CP_STAT_cmdack;
|
| 664 |
|
|
R_CP_STAT.cmderr <= CP_STAT_cmderr;
|
| 665 |
|
|
R_CP_STAT.cmdmerr <= CP_STAT_cmdmerr;
|
| 666 |
|
|
R_CP_STAT.cpugo <= CP_STAT_cpugo;
|
| 667 |
|
|
R_CP_STAT.cpustep <= CP_STAT_cpustep;
|
| 668 |
|
|
R_CP_STAT.cpuhalt <= CP_STAT_cpuhalt;
|
| 669 |
|
|
R_CP_STAT.cpurust <= CP_STAT_cpurust;
|
| 670 |
|
|
R_CP_DOUT <= CP_DOUT;
|
| 671 |
|
|
|
| 672 |
|
|
end loop;
|
| 673 |
|
|
|
| 674 |
|
|
end process proc_moni;
|
| 675 |
|
|
|
| 676 |
|
|
end sim;
|
