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[/] [w11/] [tags/] [w11a_V0.61/] [tools/] [fx2/] [src/] [hw_nexys2.c] - Blame information for rev 26

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/* $Id: hw_nexys2.c 447 2011-12-31 19:41:32Z mueller $ */
/*
 * Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 * Code was forked from ixo-jtag.svn.sourceforge.net on 2011-07-17
 *
 * - original copyright and licence disclaimer --------------------------------
 * - Copyright (C) 2007 Kolja Waschk, ixo.de
 * - This code is part of usbjtag. usbjtag is free software;
 * - This code was copied from hw_basic.c and adapted for the Digilent Nexys(2)
 * - boards by Sune Mai (Oct 2008) with minor cleanups by Hauke Daempfling
 * - (May 2010). See http://www.fpga4fun.com/forum/viewtopic.php?t=483&start=50
 * ----------------------------------------------------------------------------
 *
 * This program is free software; you may redistribute and/or modify it under
 * the terms of the GNU General Public License as published by the Free
 * Software Foundation, either version 2, or at your option any later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for complete details.
 *
 * ----------------------------------------------------------------------------
 * Hardware-dependent code for usb_jtag
 *
 * Revision History:
 *
 * Date         Rev Version  Comment
 * 2011-12-30   447   1.2.1  move JTAG pin OE intoProgIO_Set_State()
 * 2011-12-29   446   1.2    clean-out all code not relevant for nexys2
 * 2011-07-23   397   1.1    move IFCONFIG and CPUCS init to usb_fifo_init
 * 2011-07-17   394   1.0    Initial version (from ixo-jtag/usb_jtag Rev 204)
 *
 *-----------------------------------------------------------------------------
 */
 
#include <fx2regs.h>
#include "hardware.h"
#include "delay.h"
 
//-----------------------------------------------------------------------------
 
/* JTAG TCK, AS/PS DCLK */
 
sbit at 0xB4          TCK; /* Port D.4 */
#define bmTCKOE       bmBIT4
#define SetTCK(x)     do{TCK=(x);}while(0)
 
/* JTAG TDI, AS ASDI, PS DATA0 */
 
sbit at 0xB2          TDI; /* Port D.2 */
#define bmTDIOE       bmBIT2
#define SetTDI(x)     do{TDI=(x);}while(0)
 
/* JTAG TMS, AS/PS nCONFIG */
 
sbit at 0xB3          TMS; /* Port D.3 */
#define bmTMSOE       bmBIT3
#define SetTMS(x)     do{TMS=(x);}while(0)
 
/* JTAG TDO, AS/PS CONF_DONE */
 
sbit at 0xB0          TDO; /* Port D.0 */
#define bmTDOOE       bmBIT0 
#define GetTDO(x)     TDO
 
/* USB Power-On (Nexys2 specific !!) */
 
sbit at 0xB7          USBPOW; /* Port D.7 */
#define bmUSBPOWOE    bmBIT7
#define SetUSBPOW(x)  do{USBPOW=(x);}while(0)
 
//-----------------------------------------------------------------------------
 
#define bmPROGOUTOE (bmTCKOE|bmTDIOE|bmTMSOE)
#define bmPROGINOE  (bmTDOOE)
 
//-----------------------------------------------------------------------------
 
void ProgIO_Poll(void)    {}
void ProgIO_Enable(void)  {}
// These aren't called anywhere in usbjtag.c so far, might come...
void ProgIO_Disable(void) {}
void ProgIO_Deinit(void)  {}
 
 
void ProgIO_Init(void)
{
  /* The following code depends on your actual circuit design.
     Make required changes _before_ you try the code! */
 
  // power on the onboard FPGA:
  //   output enable and set to 1 the Nexys2 USB-Power-enable signal
  SetUSBPOW(1);
  OED=bmUSBPOWOE;
  // Note: JTAG signal output enables are in ProgIO_Set_State() below.
 
  mdelay(500);                              // wait for supply to come up
}
 
void ProgIO_Set_State(unsigned char d)
{
  /* Set state of output pins:
   *
   * d.0 => TCK
   * d.1 => TMS
   * d.4 => TDI
   */
 
  // JTAG signal output enables done at first request:
  //   this allows to use the JTAG connector with another JTAG cable
  //   alternatively.
  OED=(OED&~bmPROGINOE) | bmPROGOUTOE; // Output enable
 
  SetTCK((d & bmBIT0) ? 1 : 0);
  SetTMS((d & bmBIT1) ? 1 : 0);
  SetTDI((d & bmBIT4) ? 1 : 0);
}
 
//-----------------------------------------------------------------------------
// dummied AS/PS code
#define GetASDO(x)  1
 
unsigned char ProgIO_Set_Get_State(unsigned char d)
{
  /* Set state of output pins (s.a.)
   * then read state of input pins:
   *
   * TDO => d.0
   * DATAOUT => d.1 (only #ifdef HAVE_AS_MODE)
   */
 
  ProgIO_Set_State(d);
  return (GetASDO()<<1)|GetTDO();
}
 
//-----------------------------------------------------------------------------
 
void ProgIO_ShiftOut(unsigned char c)
{
  /* Shift out byte C:
   *
   * 8x {
   *   Output least significant bit on TDI
   *   Raise TCK
   *   Shift c right
   *   Lower TCK
   * }
   */
 
  (void)c; /* argument passed in DPL */
 
  _asm
        MOV  A,DPL
        ;; Bit0
        RRC  A
        MOV  _TDI,C
        SETB _TCK
        ;; Bit1
        RRC  A
        CLR  _TCK
        MOV  _TDI,C
        SETB _TCK
        ;; Bit2
        RRC  A
        CLR  _TCK
        MOV  _TDI,C
        SETB _TCK
        ;; Bit3
        RRC  A
        CLR  _TCK
        MOV  _TDI,C
        SETB _TCK
        ;; Bit4
        RRC  A
        CLR  _TCK
        MOV  _TDI,C
        SETB _TCK
        ;; Bit5
        RRC  A
        CLR  _TCK
        MOV  _TDI,C
        SETB _TCK
        ;; Bit6
        RRC  A
        CLR  _TCK
        MOV  _TDI,C
        SETB _TCK
        ;; Bit7
        RRC  A
        CLR  _TCK
        MOV  _TDI,C
        SETB _TCK
        NOP
        CLR  _TCK
        ret
  _endasm;
}
 
/*
;; For ShiftInOut, the timing is a little more
;; critical because we have to read _TDO/shift/set _TDI
;; when _TCK is low. But 20% duty cycle at 48/4/5 MHz
;; is just like 50% at 6 Mhz, and that's still acceptable
*/
 
unsigned char ProgIO_ShiftInOut(unsigned char c)
{
  /* Shift out byte C, shift in from TDO:
   *
   * 8x {
   *   Read carry from TDO
   *   Output least significant bit on TDI
   *   Raise TCK
   *   Shift c right, append carry (TDO) at left
   *   Lower TCK
   * }
   * Return c.
   */
 
   (void)c; /* argument passed in DPL */
 
  _asm
        MOV  A,DPL
 
        ;; Bit0
        MOV  C,_TDO
        RRC  A
        MOV  _TDI,C
        SETB _TCK
        CLR  _TCK
        ;; Bit1
        MOV  C,_TDO
        RRC  A
        MOV  _TDI,C
        SETB _TCK
        CLR  _TCK
        ;; Bit2
        MOV  C,_TDO
        RRC  A
        MOV  _TDI,C
        SETB _TCK
        CLR  _TCK
        ;; Bit3
        MOV  C,_TDO
        RRC  A
        MOV  _TDI,C
        SETB _TCK
        CLR  _TCK
        ;; Bit4
        MOV  C,_TDO
        RRC  A
        MOV  _TDI,C
        SETB _TCK
        CLR  _TCK
        ;; Bit5
        MOV  C,_TDO
        RRC  A
        MOV  _TDI,C
        SETB _TCK
        CLR  _TCK
        ;; Bit6
        MOV  C,_TDO
        RRC  A
        MOV  _TDI,C
        SETB _TCK
        CLR  _TCK
        ;; Bit7
        MOV  C,_TDO
        RRC  A
        MOV  _TDI,C
        SETB _TCK
        NOP
        CLR  _TCK
 
        MOV  DPL,A
        ret
  _endasm;
 
  /* return value in DPL */
 
  return c;
}
 

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[/] [w11/] [tags/] [w11a_V0.61/] [tools/] [fx2/] [src/] [hw_nexys2.c] - Blame information for rev 26

Line No.	Rev	Author	Line
1	17	wfjm	`/* $Id: hw_nexys2.c 447 2011-12-31 19:41:32Z mueller $ */`
2			`/*`
3			`* Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>`
4			`* Code was forked from ixo-jtag.svn.sourceforge.net on 2011-07-17`
5			`*`
6			`* - original copyright and licence disclaimer --------------------------------`
7			`* - Copyright (C) 2007 Kolja Waschk, ixo.de`
8			`* - This code is part of usbjtag. usbjtag is free software;`
9			`* - This code was copied from hw_basic.c and adapted for the Digilent Nexys(2)`
10			`* - boards by Sune Mai (Oct 2008) with minor cleanups by Hauke Daempfling`
11			`* - (May 2010). See http://www.fpga4fun.com/forum/viewtopic.php?t=483&start=50`
12			`* ----------------------------------------------------------------------------`
13			`*`
14			`* This program is free software; you may redistribute and/or modify it under`
15			`* the terms of the GNU General Public License as published by the Free`
16			`* Software Foundation, either version 2, or at your option any later version.`
17			`*`
18			`* This program is distributed in the hope that it will be useful, but`
19			`* WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY`
20			`* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
21			`* for complete details.`
22			`*`
23			`* ----------------------------------------------------------------------------`
24			`* Hardware-dependent code for usb_jtag`
25			`*`
26			`* Revision History:`
27			`*`
28			`* Date Rev Version Comment`
29			`* 2011-12-30 447 1.2.1 move JTAG pin OE intoProgIO_Set_State()`
30			`* 2011-12-29 446 1.2 clean-out all code not relevant for nexys2`
31			`* 2011-07-23 397 1.1 move IFCONFIG and CPUCS init to usb_fifo_init`
32			`* 2011-07-17 394 1.0 Initial version (from ixo-jtag/usb_jtag Rev 204)`
33			`*`
34			`*-----------------------------------------------------------------------------`
35			`*/`
36
37			`#include <fx2regs.h>`
38			`#include "hardware.h"`
39			`#include "delay.h"`
40
41			`//-----------------------------------------------------------------------------`
42
43			`/* JTAG TCK, AS/PS DCLK */`
44
45			`sbit at 0xB4 TCK; /* Port D.4 */`
46			`#define bmTCKOE bmBIT4`
47			`#define SetTCK(x) do{TCK=(x);}while(0)`
48
49			`/* JTAG TDI, AS ASDI, PS DATA0 */`
50
51			`sbit at 0xB2 TDI; /* Port D.2 */`
52			`#define bmTDIOE bmBIT2`
53			`#define SetTDI(x) do{TDI=(x);}while(0)`
54
55			`/* JTAG TMS, AS/PS nCONFIG */`
56
57			`sbit at 0xB3 TMS; /* Port D.3 */`
58			`#define bmTMSOE bmBIT3`
59			`#define SetTMS(x) do{TMS=(x);}while(0)`
60
61			`/* JTAG TDO, AS/PS CONF_DONE */`
62
63			`sbit at 0xB0 TDO; /* Port D.0 */`
64			`#define bmTDOOE bmBIT0`
65			`#define GetTDO(x) TDO`
66
67			`/* USB Power-On (Nexys2 specific !!) */`
68
69			`sbit at 0xB7 USBPOW; /* Port D.7 */`
70			`#define bmUSBPOWOE bmBIT7`
71			`#define SetUSBPOW(x) do{USBPOW=(x);}while(0)`
72
73			`//-----------------------------------------------------------------------------`
74
75			`#define bmPROGOUTOE (bmTCKOE\|bmTDIOE\|bmTMSOE)`
76			`#define bmPROGINOE (bmTDOOE)`
77
78			`//-----------------------------------------------------------------------------`
79
80			`void ProgIO_Poll(void) {}`
81			`void ProgIO_Enable(void) {}`
82			`// These aren't called anywhere in usbjtag.c so far, might come...`
83			`void ProgIO_Disable(void) {}`
84			`void ProgIO_Deinit(void) {}`
85
86
87			`void ProgIO_Init(void)`
88			`{`
89			`/* The following code depends on your actual circuit design.`
90			`Make required changes _before_ you try the code! */`
91
92			`// power on the onboard FPGA:`
93			`// output enable and set to 1 the Nexys2 USB-Power-enable signal`
94			`SetUSBPOW(1);`
95			`OED=bmUSBPOWOE;`
96			`// Note: JTAG signal output enables are in ProgIO_Set_State() below.`
97
98			`mdelay(500); // wait for supply to come up`
99			`}`
100
101			`void ProgIO_Set_State(unsigned char d)`
102			`{`
103			`/* Set state of output pins:`
104			`*`
105			`* d.0 => TCK`
106			`* d.1 => TMS`
107			`* d.4 => TDI`
108			`*/`
109
110			`// JTAG signal output enables done at first request:`
111			`// this allows to use the JTAG connector with another JTAG cable`
112			`// alternatively.`
113			`OED=(OED&~bmPROGINOE) \| bmPROGOUTOE; // Output enable`
114
115			`SetTCK((d & bmBIT0) ? 1 : 0);`
116			`SetTMS((d & bmBIT1) ? 1 : 0);`
117			`SetTDI((d & bmBIT4) ? 1 : 0);`
118			`}`
119
120			`//-----------------------------------------------------------------------------`
121			`// dummied AS/PS code`
122			`#define GetASDO(x) 1`
123
124			`unsigned char ProgIO_Set_Get_State(unsigned char d)`
125			`{`
126			`/* Set state of output pins (s.a.)`
127			`* then read state of input pins:`
128			`*`
129			`* TDO => d.0`
130			`* DATAOUT => d.1 (only #ifdef HAVE_AS_MODE)`
131			`*/`
132
133			`ProgIO_Set_State(d);`
134			`return (GetASDO()<<1)\|GetTDO();`
135			`}`
136
137			`//-----------------------------------------------------------------------------`
138
139			`void ProgIO_ShiftOut(unsigned char c)`
140			`{`
141			`/* Shift out byte C:`
142			`*`
143			`* 8x {`
144			`* Output least significant bit on TDI`
145			`* Raise TCK`
146			`* Shift c right`
147			`* Lower TCK`
148			`* }`
149			`*/`
150
151			`(void)c; /* argument passed in DPL */`
152
153			`_asm`
154			`MOV A,DPL`
155			`;; Bit0`
156			`RRC A`
157			`MOV _TDI,C`
158			`SETB _TCK`
159			`;; Bit1`
160			`RRC A`
161			`CLR _TCK`
162			`MOV _TDI,C`
163			`SETB _TCK`
164			`;; Bit2`
165			`RRC A`
166			`CLR _TCK`
167			`MOV _TDI,C`
168			`SETB _TCK`
169			`;; Bit3`
170			`RRC A`
171			`CLR _TCK`
172			`MOV _TDI,C`
173			`SETB _TCK`
174			`;; Bit4`
175			`RRC A`
176			`CLR _TCK`
177			`MOV _TDI,C`
178			`SETB _TCK`
179			`;; Bit5`
180			`RRC A`
181			`CLR _TCK`
182			`MOV _TDI,C`
183			`SETB _TCK`
184			`;; Bit6`
185			`RRC A`
186			`CLR _TCK`
187			`MOV _TDI,C`
188			`SETB _TCK`
189			`;; Bit7`
190			`RRC A`
191			`CLR _TCK`
192			`MOV _TDI,C`
193			`SETB _TCK`
194			`NOP`
195			`CLR _TCK`
196			`ret`
197			`_endasm;`
198			`}`
199
200			`/*`
201			`;; For ShiftInOut, the timing is a little more`
202			`;; critical because we have to read _TDO/shift/set _TDI`
203			`;; when _TCK is low. But 20% duty cycle at 48/4/5 MHz`
204			`;; is just like 50% at 6 Mhz, and that's still acceptable`
205			`*/`
206
207			`unsigned char ProgIO_ShiftInOut(unsigned char c)`
208			`{`
209			`/* Shift out byte C, shift in from TDO:`
210			`*`
211			`* 8x {`
212			`* Read carry from TDO`
213			`* Output least significant bit on TDI`
214			`* Raise TCK`
215			`* Shift c right, append carry (TDO) at left`
216			`* Lower TCK`
217			`* }`
218			`* Return c.`
219			`*/`
220
221			`(void)c; /* argument passed in DPL */`
222
223			`_asm`
224			`MOV A,DPL`
225
226			`;; Bit0`
227			`MOV C,_TDO`
228			`RRC A`
229			`MOV _TDI,C`
230			`SETB _TCK`
231			`CLR _TCK`
232			`;; Bit1`
233			`MOV C,_TDO`
234			`RRC A`
235			`MOV _TDI,C`
236			`SETB _TCK`
237			`CLR _TCK`
238			`;; Bit2`
239			`MOV C,_TDO`
240			`RRC A`
241			`MOV _TDI,C`
242			`SETB _TCK`
243			`CLR _TCK`
244			`;; Bit3`
245			`MOV C,_TDO`
246			`RRC A`
247			`MOV _TDI,C`
248			`SETB _TCK`
249			`CLR _TCK`
250			`;; Bit4`
251			`MOV C,_TDO`
252			`RRC A`
253			`MOV _TDI,C`
254			`SETB _TCK`
255			`CLR _TCK`
256			`;; Bit5`
257			`MOV C,_TDO`
258			`RRC A`
259			`MOV _TDI,C`
260			`SETB _TCK`
261			`CLR _TCK`
262			`;; Bit6`
263			`MOV C,_TDO`
264			`RRC A`
265			`MOV _TDI,C`
266			`SETB _TCK`
267			`CLR _TCK`
268			`;; Bit7`
269			`MOV C,_TDO`
270			`RRC A`
271			`MOV _TDI,C`
272			`SETB _TCK`
273			`NOP`
274			`CLR _TCK`
275
276			`MOV DPL,A`
277			`ret`
278			`_endasm;`
279
280			`/* return value in DPL */`
281
282			`return c;`
283			`}`
284