| 1 |
17 |
wfjm |
/* -*- c++ -*- */
|
| 2 |
|
|
/* $Id: syncdelay.h 395 2011-07-17 22:02:55Z mueller $ */
|
| 3 |
|
|
/*-----------------------------------------------------------------------------
|
| 4 |
|
|
* Synchronization delay for FX2 access to specific registers
|
| 5 |
|
|
*-----------------------------------------------------------------------------
|
| 6 |
|
|
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,
|
| 7 |
|
|
* Copyright 2003 Free Software Foundation, Inc.
|
| 8 |
|
|
*-----------------------------------------------------------------------------
|
| 9 |
|
|
* This code is part of usbjtag. usbjtag is free software; you can redistribute
|
| 10 |
|
|
* it and/or modify it under the terms of the GNU General Public License as
|
| 11 |
|
|
* published by the Free Software Foundation; either version 2 of the License,
|
| 12 |
|
|
* or (at your option) any later version. usbjtag is distributed in the hope
|
| 13 |
|
|
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
|
| 14 |
|
|
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
| 15 |
|
|
* GNU General Public License for more details. You should have received a
|
| 16 |
|
|
* copy of the GNU General Public License along with this program in the file
|
| 17 |
|
|
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
|
| 18 |
|
|
* St, Fifth Floor, Boston, MA 02110-1301 USA
|
| 19 |
|
|
*-----------------------------------------------------------------------------
|
| 20 |
|
|
*/
|
| 21 |
|
|
|
| 22 |
|
|
#ifndef _SYNCDELAY_H_
|
| 23 |
|
|
#define _SYNCDELAY_H_
|
| 24 |
|
|
|
| 25 |
|
|
/*
|
| 26 |
|
|
* Magic delay required between access to certain xdata registers (TRM page 15-106).
|
| 27 |
|
|
* For our configuration, 48 MHz FX2 / 48 MHz IFCLK, we need three cycles. Each
|
| 28 |
|
|
* NOP is a single cycle....
|
| 29 |
|
|
*
|
| 30 |
|
|
* From TRM page 15-105:
|
| 31 |
|
|
*
|
| 32 |
|
|
* Under certain conditions, some read and write access to the FX2 registers must
|
| 33 |
|
|
* be separated by a "synchronization delay". The delay is necessary only under the
|
| 34 |
|
|
* following conditions:
|
| 35 |
|
|
*
|
| 36 |
|
|
* - between a write to any register in the 0xE600 - 0xE6FF range and a write to one
|
| 37 |
|
|
* of the registers listed below.
|
| 38 |
|
|
*
|
| 39 |
|
|
* - between a write to one of the registers listed below and a read from any register
|
| 40 |
|
|
* in the 0xE600 - 0xE6FF range.
|
| 41 |
|
|
*
|
| 42 |
|
|
* Registers which require a synchronization delay:
|
| 43 |
|
|
*
|
| 44 |
|
|
* FIFORESET FIFOPINPOLAR
|
| 45 |
|
|
* INPKTEND EPxBCH:L
|
| 46 |
|
|
* EPxFIFOPFH:L EPxAUTOINLENH:L
|
| 47 |
|
|
* EPxFIFOCFG EPxGPIFFLGSEL
|
| 48 |
|
|
* PINFLAGSAB PINFLAGSCD
|
| 49 |
|
|
* EPxFIFOIE EPxFIFOIRQ
|
| 50 |
|
|
* GPIFIE GPIFIRQ
|
| 51 |
|
|
* UDMACRCH:L GPIFADRH:L
|
| 52 |
|
|
* GPIFTRIG EPxGPIFTRIG
|
| 53 |
|
|
* OUTPKTEND REVCTL
|
| 54 |
|
|
* GPIFTCB3 GPIFTCB2
|
| 55 |
|
|
* GPIFTCB1 GPIFTCB0
|
| 56 |
|
|
*/
|
| 57 |
|
|
|
| 58 |
|
|
/*
|
| 59 |
|
|
* FIXME ensure that the peep hole optimizer isn't screwing us
|
| 60 |
|
|
*/
|
| 61 |
|
|
#define SYNCDELAY _asm nop; nop; nop; _endasm
|
| 62 |
|
|
#define NOP _asm nop; _endasm
|
| 63 |
|
|
|
| 64 |
|
|
|
| 65 |
|
|
#endif /* _SYNCDELAY_H_ */
|
