OpenCores
URL https://opencores.org/ocsvn/w11/w11/trunk

Subversion Repositories w11

[/] [w11/] [tags/] [w11a_V0.61/] [tools/] [tbench/] [test_w11a_dstw_word_flow.tcl] - Blame information for rev 40

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 25 wfjm
# $Id: test_w11a_dstw_word_flow.tcl 575 2014-07-27 20:55:41Z mueller $
2 19 wfjm
#
3 22 wfjm
# Copyright 2013-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4 19 wfjm
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
5
#
6
# Revision History:
7
# Date         Rev Version  Comment
8 25 wfjm
# 2014-07-27   575   1.0.2  drop tout value from asmwait, reply on asmwait_tout
9 22 wfjm
# 2014-03-01   552   1.0.1  check that unused regs stay 0
10 19 wfjm
# 2013-03-31   502   1.0    Initial version
11
#
12
# Test dstw flow with mov #nnn,... instructions for word access
13
#
14
 
15 22 wfjm
# ----------------------------------------------------------------------------
16 19 wfjm
rlc log "test_w11a_dstw_word_flow: test dstw flow for word with mov #nnn,..."
17
rlc log "  r0,(r0),(r0)+,@(r0)+,-(r0),@-(r0) (mode=0,1,2,3,4,5)"
18 22 wfjm
 
19
# code register pre/post conditions beyond defaults
20
#   r0           -> 0100
21
#   r1   #data1  -> ..same
22
#   r2   #data2  -> #data2+4
23
#   r3   #pdata3 -> #pdata3+4
24
#   r4   #data4e -> #data4e-4
25
#   r5   #pdat5e -> #pdat5e-4
26 19 wfjm
$cpu ldasm -lst lst -sym sym {
27
        . = 1000
28
start:  mov     #100,r0
29
        mov     #110,(r1)
30
        mov     #120,(r2)+
31
        mov     #121,(r2)+
32
        mov     #130,@(r3)+
33
        mov     #131,@(r3)+
34
        mov     #141,-(r4)
35
        mov     #140,-(r4)
36
        mov     #151,@-(r5)
37
        mov     #150,@-(r5)
38
        halt
39
stop:
40 22 wfjm
;
41 19 wfjm
data1:  .word   0
42
data2:  .word   0,0
43
data3:  .word   0,0
44
data4:  .word   0,0
45
data4e:
46
data5:  .word   0,0
47
data5e:
48
pdata3: .word   data3,data3+2
49
pdata5: .word   data5,data5+2
50
pdat5e:
51
}
52
 
53 20 wfjm
rw11::asmrun  $cpu sym [list r1 $sym(data1) \
54 22 wfjm
                             r2 $sym(data2) \
55
                             r3 $sym(pdata3) \
56
                             r4 $sym(data4e) \
57
                             r5 $sym(pdat5e) ]
58 25 wfjm
rw11::asmwait $cpu sym
59 20 wfjm
rw11::asmtreg $cpu [list r0 0100 \
60
                         r1 $sym(data1) \
61
                         r2 [expr {$sym(data2)  + 4}] \
62
                         r3 [expr {$sym(pdata3) + 4}] \
63
                         r4 [expr {$sym(data4e) - 4}] \
64
                         r5 [expr {$sym(pdat5e) - 4}] ]
65
rw11::asmtmem $cpu $sym(data1) {0110 0120 0121 0130 0131 0140 0141 0150 0151}
66 19 wfjm
 
67 22 wfjm
# ----------------------------------------------------------------------------
68
rlc log "  nn(r0),@nn(r0),var,@var,@#var (mode=6,7,67,77,37)"
69 19 wfjm
 
70 22 wfjm
# code register pre/post conditions beyond defaults
71
#   r0   #data0-020  -> ..same
72
#   r1   #pdata0-040 -> ..same
73 19 wfjm
$cpu ldasm -lst lst -sym sym {
74
        . = 1000
75
start:  mov     #200,20(r0)
76
        mov     #210,@40(r1)
77
        mov     #220,data2
78
        mov     #230,@pdata3
79
        mov     #240,@#data4
80
        halt
81
stop:
82 22 wfjm
;
83 19 wfjm
data0:  .word   0
84
data1:  .word   0
85
data2:  .word   0
86
data3:  .word   0
87
data4:  .word   0
88
data4e:
89
pdata1: .word   data1
90
pdata3: .word   data3
91
}
92
 
93 20 wfjm
rw11::asmrun  $cpu sym [list r0 [expr {$sym(data0)-020}] \
94
                             r1 [expr {$sym(pdata1)-040}]  ]
95 25 wfjm
rw11::asmwait $cpu sym
96 22 wfjm
rw11::asmtreg $cpu [list r0 [expr {$sym(data0)-020}] \
97
                         r1 [expr {$sym(pdata1)-040}] \
98
                         r2 0 \
99
                         r3 0 \
100
                         r4 0 \
101
                         r5 0 ]
102 20 wfjm
rw11::asmtmem $cpu $sym(data0) {0200 0210 0220 0230 0240}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.