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# $Id: Makefile 682 2015-05-15 18:35:29Z mueller $
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#
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# 'Meta Makefile' for whole retro project
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# allows to make all synthesis targets
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# allows to make all test bench targets
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#
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# Revision History:
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# Date Rev Version Comment
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# 2015-02-01 640 1.2 add vivado targets, separate from ise targets
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# 2015-01-25 638 1.1 drop as type fx2 targets
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# 2014-06-14 562 1.0.8 suspend nexys4 syn targets
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# 2013-09-28 535 1.0.7 add nexys4 port for sys_gen/tst_sram,w11a
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# 2013-05-01 513 1.0.6 add clean_sim_tmp and clean_syn_tmp targets
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# 2012-12-29 466 1.0.5 add tst_rlink_cuff
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# 2011-12-26 445 1.0.4 add tst_fx2loop
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# 2011-12-23 444 1.0.3 enforce -j 1 in sub-makes
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# 2011-11-27 433 1.0.2 add new nexys3 ports
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# 2011-11-18 426 1.0.1 add tst_serport and tst_snhumanio
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# 2011-07-09 391 1.0 Initial version
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#
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# Synthesis targets --------------------------------------------------
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# ISE based targets, by board type -----------------------
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# S3board ------------------------------------
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SYN_ise += rtl/sys_gen/tst_rlink/s3board
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SYN_ise += rtl/sys_gen/tst_serloop/s3board
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SYN_ise += rtl/sys_gen/tst_snhumanio/s3board
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SYN_ise += rtl/sys_gen/w11a/s3board
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# Nexys2 -------------------------------------
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SYN_ise += rtl/sys_gen/tst_fx2loop/nexys2/ic
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SYN_ise += rtl/sys_gen/tst_fx2loop/nexys2/ic3
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SYN_ise += rtl/sys_gen/tst_rlink/nexys2
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SYN_ise += rtl/sys_gen/tst_rlink_cuff/nexys2/ic
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SYN_ise += rtl/sys_gen/tst_rlink_cuff/nexys2/ic3
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SYN_ise += rtl/sys_gen/tst_serloop/nexys2
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SYN_ise += rtl/sys_gen/tst_snhumanio/nexys2
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SYN_ise += rtl/sys_gen/w11a/nexys2
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# Nexys3 -------------------------------------
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SYN_ise += rtl/sys_gen/tst_fx2loop/nexys3/ic
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SYN_ise += rtl/sys_gen/tst_fx2loop/nexys3/ic3
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SYN_ise += rtl/sys_gen/tst_rlink/nexys3
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SYN_ise += rtl/sys_gen/tst_rlink_cuff/nexys3/ic
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SYN_ise += rtl/sys_gen/tst_serloop/nexys3
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SYN_ise += rtl/sys_gen/tst_snhumanio/nexys3
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SYN_ise += rtl/sys_gen/w11a/nexys3
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# xc2 ----------------------------------------
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# Vivado based targets, by board type --------------------
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# Basys3 -------------------------------------
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SYN_viv += rtl/sys_gen/tst_snhumanio/basys3
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#SYN_viv += rtl/sys_gen/tst_serloop/basys3
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SYN_viv += rtl/sys_gen/tst_rlink/basys3
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SYN_viv += rtl/sys_gen/w11a/basys3
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# Nexys4 -------------------------------------
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SYN_viv += rtl/sys_gen/tst_rlink/nexys4
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SYN_viv += rtl/sys_gen/tst_serloop/nexys4
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SYN_viv += rtl/sys_gen/tst_snhumanio/nexys4
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SYN_viv += rtl/sys_gen/w11a/nexys4
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# Simulation targets -------------------------------------------------
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# ISE flow -----------------------------------------------
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# Component tests ----------------------------
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SIM_ise += rtl/bplib/nxcramlib/tb
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SIM_ise += rtl/vlib/comlib/tb
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SIM_ise += rtl/vlib/rlink/tb
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SIM_ise += rtl/vlib/serport/tb
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SIM_ise += rtl/w11a/tb
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# S3board ------------------------------------
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SIM_ise += rtl/sys_gen/tst_rlink/s3board/tb
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SIM_ise += rtl/sys_gen/tst_serloop/s3board/tb
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SIM_ise += rtl/sys_gen/w11a/s3board/tb
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# Nexys2 -------------------------------------
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SIM_ise += rtl/sys_gen/tst_rlink/nexys2/tb
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SIM_ise += rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb
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SIM_ise += rtl/sys_gen/tst_serloop/nexys2/tb
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SIM_ise += rtl/sys_gen/w11a/nexys2/tb
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# Nexys3 -------------------------------------
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SIM_ise += rtl/sys_gen/tst_rlink/nexys3/tb
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SIM_ise += rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb
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SIM_ise += rtl/sys_gen/tst_serloop/nexys3/tb
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SIM_ise += rtl/sys_gen/w11a/nexys3/tb
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# xc2 ----------------------------------------
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# Vivado flow --------------------------------------------
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# Basys3 -------------------------------------
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SIM_viv += rtl/sys_gen/tst_rlink/basys3/tb
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#SIM_viv += rtl/sys_gen/tst_serloop/basys3/tb
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SIM_viv += rtl/sys_gen/w11a/basys3/tb
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# Nexys4 -------------------------------------
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SIM_viv += rtl/sys_gen/tst_rlink/nexys4/tb
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SIM_viv += rtl/sys_gen/tst_serloop/nexys4/tb
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SIM_viv += rtl/sys_gen/w11a/nexys4/tb
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#
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.PHONY : default
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.PHONY : all all_ise all_viv
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.PHONY : all_sim_ise all_syn_ise all_syn_viv
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.PHONY : clean
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.PHONY : clean_sim_ise clean_sim_ise_tmp
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.PHONY : clean_sym_ise clean_sim_viv clean_sym_ise_tmp clean_sym_viv_tmp
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#
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# all directories most be declared as phony targets
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.PHONY : $(SYN_ise) $(SIM_ise)
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.PHONY : $(SYN_viv) $(SIM_viv)
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#
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default :
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@echo "No default action defined:"
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@echo " for VHDL simulation/synthesis use:"
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@echo " make -j `nproc` all"
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@echo " make -j `nproc` all_ise"
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@echo " make -j `nproc` all_viv"
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@echo " make -j `nproc` all_sim_ise"
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@echo " make -j `nproc` all_syn_ise"
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@echo " make -j `nproc` all_sim_viv"
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@echo " make -j 1 all_syn_viv"
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@echo " make clean"
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@echo " make clean_sim_ise"
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@echo " make clean_syn_ise"
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@echo " make clean_sim_viv"
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@echo " make clean_syn_viv"
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@echo " make clean_sim_ise_tmp"
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@echo " make clean_syn_ise_tmp"
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@echo " make clean_sim_viv_tmp"
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@echo " make clean_syn_viv_tmp"
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@echo " for tool/documentation generation use:"
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@echo " make -j `nproc` all_lib"
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@echo " make clean_lib"
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@echo " make all_tcl"
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@echo " make all_dox"
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#
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all : all_ise all_viv all_lib
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all_ise : all_sim_ise all_syn_ise
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all_viv : all_sim_viv all_syn_viv
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#
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clean : clean_sim_ise clean_syn_ise clean_sim_viv clean_syn_viv
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#
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clean_sim_ise :
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for dir in $(SIM_ise); do $(MAKE) -C $$dir clean; done
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clean_syn_ise :
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for dir in $(SYN_ise); do $(MAKE) -C $$dir clean; done
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#
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clean_sim_viv :
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for dir in $(SIM_viv); do $(MAKE) -C $$dir clean; done
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clean_syn_viv :
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for dir in $(SYN_viv); do $(MAKE) -C $$dir clean; done
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#
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clean_sim_ise_tmp :
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for dir in $(SIM_ise); do $(MAKE) -C $$dir ghdl_tmp_clean; done
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clean_syn_ise_tmp :
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for dir in $(SYN_ise); do $(MAKE) -C $$dir ise_tmp_clean; done
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#
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clean_sim_viv_tmp :
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for dir in $(SIM_viv); do $(MAKE) -C $$dir ghdl_tmp_clean; done
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clean_syn_viv_tmp :
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for dir in $(SYN_viv); do $(MAKE) -C $$dir viv_tmp_clean; done
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#
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all_sim_ise : $(SIM_ise)
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#
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all_syn_ise : $(SYN_ise)
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@if [ -n "`find -name "*_par.log" | xargs grep -L 'All constraints were met'`" ] ; then \
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echo "++++++++++ some designs have no timing closure: ++++++++++"; \
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find -name "*_par.log" | xargs grep -L 'All constraints were met'; \
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echo "++++++++++ ++++++++++++++++++++++++++++++++++++ ++++++++++"; \
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else \
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echo "++++++++++ all ISE designs have timing closure ++++++++++"; \
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fi
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#
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all_sim_viv : $(SIM_viv)
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#
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all_syn_viv : $(SYN_viv)
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@if [ -n "`find -name "*_rou_tim.rpt" | xargs grep -L 'All user specified timing constraints are met'`" ] ; then \
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echo "++++++++++ some designs have no timing closure: ++++++++++"; \
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find -name "*_rou_tim.rpt" | xargs grep -L 'All user specified timing constraints are met'; \
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echo "++++++++++ ++++++++++++++++++++++++++++++++++++ ++++++++++"; \
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else \
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echo "++++++++++ all Vivado designs have timing closure ++++++++++"; \
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fi
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#
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# Neither ghdl nor Xilinx tools allow multiple parallel compiles in one
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# directory. The following ensures that the sub-makes are called with -j 1
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# and will not try to run multiple compiles on one directory.
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#
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$(SIM_ise):
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$(MAKE) -j 1 -C $@
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$(SYN_ise):
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$(MAKE) -j 1 -C $@
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#
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$(SIM_viv):
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$(MAKE) -j 1 -C $@
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$(SYN_viv):
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$(MAKE) -j 1 -C $@
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#
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all_lib :
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$(MAKE) -C tools/src
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clean_lib :
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$(MAKE) -C tools/src distclean
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#
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all_tcl :
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(cd tools/tcl; setup_packages)
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#
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all_dox :
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(cd tools/dox; make_doxy)
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#
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all_all : all_sim all_syn all_lib all_tcl
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