OpenCores
URL https://opencores.org/ocsvn/w11/w11/trunk

Subversion Repositories w11

[/] [w11/] [tags/] [w11a_V0.7/] [rtl/] [bplib/] [bpgen/] [sn_humanio_demu.vhd] - Blame information for rev 33

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 29 wfjm
-- $Id: sn_humanio_demu.vhd 649 2015-02-21 21:10:16Z mueller $
2 13 wfjm
--
3
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4
--
5
-- This program is free software; you may redistribute and/or modify it under
6
-- the terms of the GNU General Public License as published by the Free
7
-- Software Foundation, either version 2, or at your option any later version.
8
--
9
-- This program is distributed in the hope that it will be useful, but
10
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
11
-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
12
-- for complete details.
13
--
14
------------------------------------------------------------------------------
15
-- Module Name:    sn_humanio_demu - syn
16
-- Description:    All BTN, SWI, LED handling for atlys
17
--
18
-- Dependencies:   bpgen/bp_swibtnled
19
--
20
-- Test bench:     -
21
--
22
-- Target Devices: generic
23 29 wfjm
-- Tool versions:  xst 13.1-14.7; ghdl 0.29-0.31
24 13 wfjm
--
25
-- Synthesized (xst):
26
-- Date         Rev  ise         Target      flop lutl lutm slic t peri
27
-- 2011-10-10   413 13.1    O40d xc3s1000-4    67   66    0   55 s  6.1 ns 
28
--
29
-- Revision History: 
30
-- Date         Rev Version  Comment
31
-- 2011-10-11   414   1.0.1  take care of RESET BTN being active low
32
-- 2011-10-10   413   1.0    Initial version
33
------------------------------------------------------------------------------
34
--    
35
 
36
library ieee;
37
use ieee.std_logic_1164.all;
38
use ieee.numeric_std.all;
39
 
40
use work.slvtypes.all;
41
use work.bpgenlib.all;
42
 
43
-- ----------------------------------------------------------------------------
44
 
45
entity sn_humanio_demu is               -- human i/o handling: swi,btn,led only
46
  generic (
47
    DEBOUNCE : boolean := true);        -- instantiate debouncer for SWI,BTN
48
  port (
49
    CLK : in slbit;                     -- clock
50
    RESET : in slbit := '0';            -- reset
51
    CE_MSEC : in slbit;                 -- 1 ms clock enable
52
    SWI : out slv8;                     -- switch settings, debounced
53
    BTN : out slv4;                     -- button settings, debounced
54
    LED : in slv8;                      -- led data
55
    DSP_DAT : in slv16;                 -- display data
56
    DSP_DP : in slv4;                   -- display decimal points
57
    I_SWI : in slv8;                    -- pad-i: switches
58
    I_BTN : in slv6;                    -- pad-i: buttons
59
    O_LED : out slv8                    -- pad-o: leds
60
  );
61
end sn_humanio_demu;
62
 
63
architecture syn of sn_humanio_demu is
64
 
65
  constant c_mode_led  : slv2 := "00";
66
  constant c_mode_dp   : slv2 := "01";
67
  constant c_mode_datl : slv2 := "10";
68
  constant c_mode_dath : slv2 := "11";
69
 
70
  type regs_type is record
71
    mode : slv2;                        -- current mode
72
    cnt : slv9;                         -- msec counter
73
    up_1 : slbit;                       -- btn up last cycle
74
    dn_1 : slbit;                       -- btn dn last cycle
75
    led : slv8;                         -- led state
76
  end record regs_type;
77
 
78
  constant regs_init : regs_type := (
79
    c_mode_led,                         -- mode
80
    (others=>'0'),                      -- cnt
81
    '0','0',                            -- up_1, dn_1
82
    (others=>'0')                       -- led
83
  );
84
 
85
  signal R_REGS : regs_type := regs_init;  -- state registers
86
  signal N_REGS : regs_type := regs_init;  -- next value state regs
87
 
88
  signal BTN_HW :  slv6 := (others=>'0');
89
  signal LED_HW :  slv8 := (others=>'0');
90
 
91
begin
92
 
93
 HIO : bp_swibtnled
94
    generic map (
95
      SWIDTH   => 8,
96
      BWIDTH   => 6,
97
      LWIDTH   => 8,
98
      DEBOUNCE => DEBOUNCE)
99
    port map (
100
      CLK     => CLK,
101
      RESET   => RESET,
102
      CE_MSEC => CE_MSEC,
103
      SWI     => SWI,
104
      BTN     => BTN_HW,
105
      LED     => LED_HW,
106
      I_SWI   => I_SWI,
107
      I_BTN   => I_BTN,
108
      O_LED   => O_LED
109
    );
110
 
111
  proc_regs: process (CLK)
112
  begin
113
 
114
    if rising_edge(CLK) then
115
      if RESET = '1' then
116
        R_REGS <= regs_init;
117
      else
118
        R_REGS <= N_REGS;
119
      end if;
120
    end if;
121
 
122
  end process proc_regs;
123
 
124
  proc_next: process (R_REGS, CE_MSEC, LED, DSP_DAT, DSP_DP, BTN_HW)
125
 
126
    variable r : regs_type := regs_init;
127
    variable n : regs_type := regs_init;
128
 
129
    variable ibtn : slv4 := (others=>'0');
130
    variable iup : slbit := '0';
131
    variable idn : slbit := '0';
132
    variable ipuls : slbit := '0';
133
 
134
  begin
135
    r := R_REGS;
136
    n := R_REGS;
137
 
138
    ibtn(0) := not BTN_HW(5);           -- RESET button is act. low !
139
    ibtn(1) := BTN_HW(1);
140
    ibtn(2) := BTN_HW(4);
141
    ibtn(3) := BTN_HW(3);
142
    iup     := BTN_HW(0);
143
    idn     := BTN_HW(2);
144
 
145
    ipuls := '0';
146
 
147
 
148
    n.up_1 := iup;
149
    n.dn_1 := idn;
150
 
151
    if iup='0' and idn='0' then
152
      n.cnt := (others=>'0');
153
    else
154
      if CE_MSEC = '1' then
155
        n.cnt := slv(unsigned(r.cnt) + 1);
156
        if r.cnt = "111111111" then
157
          ipuls := '1';
158
        end if;
159
      end if;
160
    end if;
161
 
162
    if iup='1' or idn='1' then
163
      n.led := (others=>'0');
164
      case r.mode is
165
        when c_mode_led  => n.led(0) := '1';
166
        when c_mode_dp   => n.led(1) := '1';
167
        when c_mode_datl => n.led(2) := '1';
168
        when c_mode_dath => n.led(3) := '1';
169
        when others => null;
170
      end case;
171
 
172
      if    iup='1' and (r.up_1='0' or ipuls='1') then
173
        n.mode := slv(unsigned(r.mode) + 1);
174
      elsif idn='1' and (r.dn_1='0' or ipuls='1') then
175
        n.mode := slv(unsigned(r.mode) - 1);
176
      end if;
177
 
178
    else
179
      case r.mode is
180
        when c_mode_led  => n.led := LED;
181
        when c_mode_dp   => n.led := "0000" & DSP_DP;
182
        when c_mode_datl => n.led := DSP_DAT( 7 downto 0);
183
        when c_mode_dath => n.led := DSP_DAT(15 downto 8);
184
        when others => null;
185
      end case;
186
    end if;
187
 
188
    N_REGS <= n;
189
 
190
    BTN    <= ibtn;
191
    LED_HW <= r.led;
192
 
193
  end process proc_next;
194
 
195
end syn;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.