1 |
29 |
wfjm |
-- $Id: fx2lib.vhd 638 2015-01-25 22:01:38Z mueller $
|
2 |
17 |
wfjm |
--
|
3 |
29 |
wfjm |
-- Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
4 |
17 |
wfjm |
--
|
5 |
|
|
-- This program is free software; you may redistribute and/or modify it under
|
6 |
|
|
-- the terms of the GNU General Public License as published by the Free
|
7 |
|
|
-- Software Foundation, either version 2, or at your option any later version.
|
8 |
|
|
--
|
9 |
|
|
-- This program is distributed in the hope that it will be useful, but
|
10 |
|
|
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
|
11 |
|
|
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
12 |
|
|
-- for complete details.
|
13 |
|
|
--
|
14 |
|
|
------------------------------------------------------------------------------
|
15 |
|
|
-- Package Name: fx2lib
|
16 |
|
|
-- Description: Cypress ez-usb fx2 support
|
17 |
|
|
--
|
18 |
|
|
-- Dependencies: -
|
19 |
29 |
wfjm |
-- Tool versions: xst 12.1-14.7; ghdl 0.26-0.31
|
20 |
17 |
wfjm |
--
|
21 |
|
|
-- Revision History:
|
22 |
|
|
-- Date Rev Version Comment
|
23 |
29 |
wfjm |
-- 2015-01-25 638 1.4 retire fx2_2fifoctl_as
|
24 |
17 |
wfjm |
-- 2012-01-14 453 1.3 use afull/aempty logic instead of exporting size
|
25 |
|
|
-- 2012-01-03 449 1.2.1 reorganize fx2ctl_moni; hardcode ep's
|
26 |
|
|
-- 2012-01-01 448 1.2 add fx2_2fifoctl_ic
|
27 |
|
|
-- 2011-12-25 445 1.1 change pktend iface in fx2_2fifoctl_as
|
28 |
|
|
-- 2011-07-17 394 1.0.1 add c_fifo_epx and fx2ctl_moni_type
|
29 |
|
|
-- 2011-07-07 389 1.0 Initial version
|
30 |
|
|
------------------------------------------------------------------------------
|
31 |
|
|
|
32 |
|
|
library ieee;
|
33 |
|
|
use ieee.std_logic_1164.all;
|
34 |
|
|
|
35 |
|
|
use work.slvtypes.all;
|
36 |
|
|
|
37 |
|
|
package fx2lib is
|
38 |
|
|
|
39 |
|
|
constant c_fifo_ep2 : slv2 := "00"; -- fifo address: end point 2
|
40 |
|
|
constant c_fifo_ep4 : slv2 := "01"; -- fifo address: end point 4
|
41 |
|
|
constant c_fifo_ep6 : slv2 := "10"; -- fifo address: end point 6
|
42 |
|
|
constant c_fifo_ep8 : slv2 := "11"; -- fifo address: end point 8
|
43 |
|
|
|
44 |
|
|
type fx2ctl_moni_type is record -- fx2ctl monitor port
|
45 |
|
|
fifo_ep4 : slbit; -- fifo 1 (ep4) active;
|
46 |
|
|
fifo_ep6 : slbit; -- fifo 2 (ep6) active;
|
47 |
|
|
fifo_ep8 : slbit; -- fifo 3 (ep8) active;
|
48 |
|
|
flag_ep4_empty : slbit; -- ep4 empty flag (latched);
|
49 |
|
|
flag_ep4_almost : slbit; -- ep4 almost empty flag (latched);
|
50 |
|
|
flag_ep6_full : slbit; -- ep6 full flag (latched);
|
51 |
|
|
flag_ep6_almost : slbit; -- ep6 almost full flag (latched);
|
52 |
|
|
flag_ep8_full : slbit; -- ep8 full flag (latched);
|
53 |
|
|
flag_ep8_almost : slbit; -- ep8 almost full flag (latched);
|
54 |
|
|
slrd : slbit; -- read strobe
|
55 |
|
|
slwr : slbit; -- write strobe
|
56 |
|
|
pktend : slbit; -- pktend strobe
|
57 |
|
|
end record fx2ctl_moni_type;
|
58 |
|
|
|
59 |
|
|
constant fx2ctl_moni_init : fx2ctl_moni_type := (
|
60 |
|
|
'0','0','0', -- fifo_ep[468]
|
61 |
|
|
'0','0', -- flag_ep4_(empty|almost)
|
62 |
|
|
'0','0', -- flag_ep6_(full|almost)
|
63 |
|
|
'0','0', -- flag_ep8_(full|almost)
|
64 |
|
|
'0','0','0' -- slrd, slwr, pktend
|
65 |
|
|
);
|
66 |
|
|
|
67 |
|
|
|
68 |
|
|
-- -------------------------------------
|
69 |
|
|
component fx2_2fifoctl_ic is -- EZ-USB FX2 driver (2 fifo; int clk)
|
70 |
|
|
generic (
|
71 |
|
|
RXFAWIDTH : positive := 5; -- receive fifo address width
|
72 |
|
|
TXFAWIDTH : positive := 5; -- transmit fifo address width
|
73 |
|
|
PETOWIDTH : positive := 7; -- packet end time-out counter width
|
74 |
|
|
CCWIDTH : positive := 5; -- chunk counter width
|
75 |
|
|
RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag
|
76 |
|
|
TXAFULL_THRES : natural := 1); -- threshold for tx afull flag
|
77 |
|
|
port (
|
78 |
|
|
CLK : in slbit; -- clock
|
79 |
|
|
RESET : in slbit := '0'; -- reset
|
80 |
|
|
RXDATA : out slv8; -- receive data out
|
81 |
|
|
RXVAL : out slbit; -- receive data valid
|
82 |
|
|
RXHOLD : in slbit; -- receive data hold
|
83 |
|
|
RXAEMPTY : out slbit; -- receive almost empty flag
|
84 |
|
|
TXDATA : in slv8; -- transmit data in
|
85 |
|
|
TXENA : in slbit; -- transmit data enable
|
86 |
|
|
TXBUSY : out slbit; -- transmit data busy
|
87 |
|
|
TXAFULL : out slbit; -- transmit almost full flag
|
88 |
|
|
MONI : out fx2ctl_moni_type; -- monitor port data
|
89 |
|
|
I_FX2_IFCLK : in slbit; -- fx2: interface clock
|
90 |
|
|
O_FX2_FIFO : out slv2; -- fx2: fifo address
|
91 |
|
|
I_FX2_FLAG : in slv4; -- fx2: fifo flags
|
92 |
|
|
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
|
93 |
|
|
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
|
94 |
|
|
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
|
95 |
|
|
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
|
96 |
|
|
IO_FX2_DATA : inout slv8 -- fx2: data lines
|
97 |
|
|
);
|
98 |
|
|
end component;
|
99 |
|
|
|
100 |
|
|
component fx2_3fifoctl_ic is -- EZ-USB FX2 driver (3 fifo; int clk)
|
101 |
|
|
generic (
|
102 |
|
|
RXFAWIDTH : positive := 5; -- receive fifo address width
|
103 |
|
|
TXFAWIDTH : positive := 5; -- transmit fifo address width
|
104 |
|
|
PETOWIDTH : positive := 7; -- packet end time-out counter width
|
105 |
|
|
CCWIDTH : positive := 5; -- chunk counter width
|
106 |
|
|
RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag
|
107 |
|
|
TXAFULL_THRES : natural := 1; -- threshold for tx afull flag
|
108 |
|
|
TX2AFULL_THRES : natural := 1); -- threshold for tx2 afull flag
|
109 |
|
|
port (
|
110 |
|
|
CLK : in slbit; -- clock
|
111 |
|
|
RESET : in slbit := '0'; -- reset
|
112 |
|
|
RXDATA : out slv8; -- receive data out
|
113 |
|
|
RXVAL : out slbit; -- receive data valid
|
114 |
|
|
RXHOLD : in slbit; -- receive data hold
|
115 |
|
|
RXAEMPTY : out slbit; -- receive almost empty flag
|
116 |
|
|
TXDATA : in slv8; -- transmit 1 data in
|
117 |
|
|
TXENA : in slbit; -- transmit 1 data enable
|
118 |
|
|
TXBUSY : out slbit; -- transmit 1 data busy
|
119 |
|
|
TXAFULL : out slbit; -- transmit 1 almost full flag
|
120 |
|
|
TX2DATA : in slv8; -- transmit 2 data in
|
121 |
|
|
TX2ENA : in slbit; -- transmit 2 data enable
|
122 |
|
|
TX2BUSY : out slbit; -- transmit 2 data busy
|
123 |
|
|
TX2AFULL : out slbit; -- transmit 2 almost full flag
|
124 |
|
|
MONI : out fx2ctl_moni_type; -- monitor port data
|
125 |
|
|
I_FX2_IFCLK : in slbit; -- fx2: interface clock
|
126 |
|
|
O_FX2_FIFO : out slv2; -- fx2: fifo address
|
127 |
|
|
I_FX2_FLAG : in slv4; -- fx2: fifo flags
|
128 |
|
|
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
|
129 |
|
|
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
|
130 |
|
|
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
|
131 |
|
|
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
|
132 |
|
|
IO_FX2_DATA : inout slv8 -- fx2: data lines
|
133 |
|
|
);
|
134 |
|
|
end component;
|
135 |
|
|
|
136 |
|
|
end package fx2lib;
|