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-- $Id: is61lv25616al.vhd 649 2015-02-21 21:10:16Z mueller $
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--
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-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: is61lv25616al - sim
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-- Description: ISSI 61LV25612AL SRAM model
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-- Currently a truely minimalistic functional model, without
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-- any timing checks. It assumes, that addr/data is stable at
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-- the trailing edge of we.
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--
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-- Dependencies: -
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-- Test bench: -
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-- Target Devices: generic
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-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
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-- Revision History:
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-- Date Rev Version Comment
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-- 2011-11-19 427 1.0.2 now numeric_std clean
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-- 2008-05-12 145 1.0.1 BUGFIX: Output now 'Z' if byte enables deasserted
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-- 2007-12-14 101 1.0 Initial version (written on warsaw airport)
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------------------------------------------------------------------------------
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-- Truth table accoring to data sheet:
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--
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-- Mode WE_N CE_N OE_N LB_N UB_N D(7:0) D(15:8)
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-- Not selected X H X X X high-Z high-Z
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-- Output disabled H L H X X high-Z high-Z
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-- X L X H H high-Z high-Z
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-- Read H L L L H D_out high-Z
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-- H L L H L high-Z D_out
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-- H L L L L D_out D_out
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-- Write L L X L H D_in high-Z
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-- L L X H L high-Z D_in
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-- L L X L L D_in D_in
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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entity is61lv25616al is -- ISSI 61LV25612AL SRAM model
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port (
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CE_N : in slbit; -- chip enable (act.low)
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OE_N : in slbit; -- output enable (act.low)
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WE_N : in slbit; -- write enable (act.low)
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UB_N : in slbit; -- upper byte enable (act.low)
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LB_N : in slbit; -- lower byte enable (act.low)
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ADDR : in slv18; -- address lines
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DATA : inout slv16 -- data lines
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);
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end is61lv25616al;
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architecture sim of is61lv25616al is
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signal CE : slbit := '0';
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signal OE : slbit := '0';
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signal WE : slbit := '0';
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signal BE_L : slbit := '0';
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signal BE_U : slbit := '0';
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component is61lv25616al_bank is -- ISSI 61LV25612AL bank
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port (
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CE : in slbit; -- chip enable (act.high)
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OE : in slbit; -- output enable (act.high)
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WE : in slbit; -- write enable (act.high)
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BE : in slbit; -- byte enable (act.high)
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ADDR : in slv18; -- address lines
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DATA : inout slv8 -- data lines
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);
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end component;
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begin
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CE <= not CE_N;
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OE <= not OE_N;
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WE <= not WE_N;
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BE_L <= not LB_N;
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BE_U <= not UB_N;
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BANK_L : is61lv25616al_bank port map (
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CE => CE,
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OE => OE,
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WE => WE,
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BE => BE_L,
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ADDR => ADDR,
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DATA => DATA(7 downto 0));
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BANK_U : is61lv25616al_bank port map (
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CE => CE,
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OE => OE,
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WE => WE,
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BE => BE_U,
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ADDR => ADDR,
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DATA => DATA(15 downto 8));
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end sim;
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-- ----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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entity is61lv25616al_bank is -- ISSI 61LV25612AL bank
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port (
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CE : in slbit; -- chip enable (act.high)
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OE : in slbit; -- output enable (act.high)
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WE : in slbit; -- write enable (act.high)
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BE : in slbit; -- byte enable (act.high)
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ADDR : in slv18; -- address lines
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DATA : inout slv8 -- data lines
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);
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end is61lv25616al_bank;
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architecture sim of is61lv25616al_bank is
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constant T_rc : time := 10 ns; -- read cycle time (min)
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constant T_aa : time := 10 ns; -- address access time (max)
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constant T_oha : time := 2 ns; -- output hold time (min)
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constant T_ace : time := 10 ns; -- ce access time (max)
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constant T_doe : time := 4 ns; -- oe access time (max)
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constant T_hzoe : time := 4 ns; -- oe to high-Z output (max)
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constant T_lzoe : time := 0 ns; -- oe to low-Z output (min)
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constant T_hzce : time := 4 ns; -- ce to high-Z output (min=0,max=4)
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constant T_lzce : time := 3 ns; -- ce to low-Z output (min)
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constant T_ba : time := 4 ns; -- lb,ub access time (max)
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constant T_hzb : time := 3 ns; -- lb,ub to high-Z output (min=0,max=3)
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constant T_lzb : time := 0 ns; -- lb,ub low-Z output (min)
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constant memsize : positive := 2**(ADDR'length);
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constant datzero : slv(DATA'range) := (others=>'0');
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type ram_type is array (0 to memsize-1) of slv(DATA'range);
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signal WE_EFF : slbit := '0';
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begin
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WE_EFF <= CE and WE and BE;
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proc_sram: process (CE, OE, WE, BE, WE_EFF, ADDR, DATA)
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variable ram : ram_type := (others=>datzero);
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begin
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if falling_edge(WE_EFF) then -- end of write cycle
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-- note: to_x01 used below to prevent
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-- that 'z' a written into mem.
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ram(to_integer(unsigned(ADDR))) := to_x01(DATA);
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end if;
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if CE='1' and OE='1' and BE='1' and WE='0' then -- output driver
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DATA <= ram(to_integer(unsigned(ADDR)));
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else
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DATA <= (others=>'Z');
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end if;
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end process proc_sram;
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end sim;
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