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[/] [w11/] [tags/] [w11a_V0.7/] [rtl/] [bplib/] [nexys2/] [nexys2_time_fx2_ic.ucf] - Blame information for rev 36
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wfjm |
## $Id: nexys2_time_fx2_ic.ucf 537 2013-10-06 09:06:23Z mueller $
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##
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## Revision History:
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## Date Rev Version Comment
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## 2013-10-05 537 1.1 add VALID for hold time check
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wfjm |
## 2012-01-01 448 1.0 Initial version
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##
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## timing rules for a 30 MHz internal clock design:
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## Period: 30 MHz
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## clk->out: longest setup time in FX2 is t_SRD (clk->SLRD) of 18.7 ns
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## clk->out < 33.3-18.7 = 14.6 ns
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## --> use 10 ns
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##
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## The nexys2 board has unfortunately the FX2 IFCLK *not* connected to a
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## clock capable pin -> not ok when FX2 uses internal clock. So allow par
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## to route from a 'normal' pin to a clock net. Not nice, compromizes the
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## timing, but unavoidable on nexys2 (Note: nexys3 and atlys are ok).
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## In practice IFCLK to pad times are quite similar on nexys2 and nexys3...
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NET "I_FX2_IFCLK" CLOCK_DEDICATED_ROUTE = FALSE;
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##
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NET "I_FX2_IFCLK" TNM_NET = "I_FX2_IFCLK";
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TIMESPEC "TS_I_FX2_IFCLK" = PERIOD "I_FX2_IFCLK" 33.34 ns HIGH 50 %;
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OFFSET = IN 2.5 ns VALID 33 ns BEFORE "I_FX2_IFCLK";
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OFFSET = OUT 10 ns VALID 33 ns AFTER "I_FX2_IFCLK";
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