| 1 |
29 |
wfjm |
-- $Id: tb_nexys3_core.vhd 649 2015-02-21 21:10:16Z mueller $
|
| 2 |
15 |
wfjm |
--
|
| 3 |
|
|
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
| 4 |
|
|
--
|
| 5 |
|
|
-- This program is free software; you may redistribute and/or modify it under
|
| 6 |
|
|
-- the terms of the GNU General Public License as published by the Free
|
| 7 |
|
|
-- Software Foundation, either version 2, or at your option any later version.
|
| 8 |
|
|
--
|
| 9 |
|
|
-- This program is distributed in the hope that it will be useful, but
|
| 10 |
|
|
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
|
| 11 |
|
|
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
| 12 |
|
|
-- for complete details.
|
| 13 |
|
|
--
|
| 14 |
|
|
------------------------------------------------------------------------------
|
| 15 |
|
|
-- Module Name: tb_nexys3_core - sim
|
| 16 |
|
|
-- Description: Test bench for nexys3 - core device handling
|
| 17 |
|
|
--
|
| 18 |
|
|
-- Dependencies: vlib/parts/micron/mt45w8mw16b
|
| 19 |
|
|
--
|
| 20 |
|
|
-- To test: generic, any nexys3 target
|
| 21 |
|
|
--
|
| 22 |
|
|
-- Target Devices: generic
|
| 23 |
29 |
wfjm |
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31
|
| 24 |
15 |
wfjm |
-- Revision History:
|
| 25 |
|
|
-- Date Rev Version Comment
|
| 26 |
|
|
-- 2011-11-25 432 1.0 Initial version (derived from tb_nexys2_core)
|
| 27 |
|
|
------------------------------------------------------------------------------
|
| 28 |
|
|
|
| 29 |
|
|
library ieee;
|
| 30 |
|
|
use ieee.std_logic_1164.all;
|
| 31 |
|
|
use ieee.numeric_std.all;
|
| 32 |
|
|
use ieee.std_logic_textio.all;
|
| 33 |
|
|
use std.textio.all;
|
| 34 |
|
|
|
| 35 |
|
|
use work.slvtypes.all;
|
| 36 |
19 |
wfjm |
use work.serportlib.all;
|
| 37 |
15 |
wfjm |
use work.simbus.all;
|
| 38 |
|
|
|
| 39 |
|
|
entity tb_nexys3_core is
|
| 40 |
|
|
port (
|
| 41 |
|
|
I_SWI : out slv8; -- n3 switches
|
| 42 |
|
|
I_BTN : out slv5; -- n3 buttons
|
| 43 |
|
|
O_MEM_CE_N : in slbit; -- cram: chip enable (act.low)
|
| 44 |
|
|
O_MEM_BE_N : in slv2; -- cram: byte enables (act.low)
|
| 45 |
|
|
O_MEM_WE_N : in slbit; -- cram: write enable (act.low)
|
| 46 |
|
|
O_MEM_OE_N : in slbit; -- cram: output enable (act.low)
|
| 47 |
|
|
O_MEM_ADV_N : in slbit; -- cram: address valid (act.low)
|
| 48 |
|
|
O_MEM_CLK : in slbit; -- cram: clock
|
| 49 |
|
|
O_MEM_CRE : in slbit; -- cram: command register enable
|
| 50 |
|
|
I_MEM_WAIT : out slbit; -- cram: mem wait
|
| 51 |
|
|
O_MEM_ADDR : in slv23; -- cram: address lines
|
| 52 |
|
|
IO_MEM_DATA : inout slv16 -- cram: data lines
|
| 53 |
|
|
);
|
| 54 |
|
|
end tb_nexys3_core;
|
| 55 |
|
|
|
| 56 |
|
|
architecture sim of tb_nexys3_core is
|
| 57 |
|
|
|
| 58 |
|
|
signal R_SWI : slv8 := (others=>'0');
|
| 59 |
|
|
signal R_BTN : slv5 := (others=>'0');
|
| 60 |
|
|
|
| 61 |
|
|
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
|
| 62 |
|
|
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
|
| 63 |
|
|
|
| 64 |
|
|
begin
|
| 65 |
|
|
|
| 66 |
|
|
MEM : entity work.mt45w8mw16b
|
| 67 |
|
|
port map (
|
| 68 |
|
|
CLK => O_MEM_CLK,
|
| 69 |
|
|
CE_N => O_MEM_CE_N,
|
| 70 |
|
|
OE_N => O_MEM_OE_N,
|
| 71 |
|
|
WE_N => O_MEM_WE_N,
|
| 72 |
|
|
UB_N => O_MEM_BE_N(1),
|
| 73 |
|
|
LB_N => O_MEM_BE_N(0),
|
| 74 |
|
|
ADV_N => O_MEM_ADV_N,
|
| 75 |
|
|
CRE => O_MEM_CRE,
|
| 76 |
|
|
MWAIT => I_MEM_WAIT,
|
| 77 |
|
|
ADDR => O_MEM_ADDR,
|
| 78 |
|
|
DATA => IO_MEM_DATA
|
| 79 |
|
|
);
|
| 80 |
|
|
|
| 81 |
|
|
proc_simbus: process (SB_VAL)
|
| 82 |
|
|
begin
|
| 83 |
|
|
if SB_VAL'event and to_x01(SB_VAL)='1' then
|
| 84 |
|
|
if SB_ADDR = sbaddr_swi then
|
| 85 |
|
|
R_SWI <= to_x01(SB_DATA(R_SWI'range));
|
| 86 |
|
|
end if;
|
| 87 |
|
|
if SB_ADDR = sbaddr_btn then
|
| 88 |
|
|
R_BTN <= to_x01(SB_DATA(R_BTN'range));
|
| 89 |
|
|
end if;
|
| 90 |
|
|
end if;
|
| 91 |
|
|
end process proc_simbus;
|
| 92 |
|
|
|
| 93 |
|
|
I_SWI <= R_SWI;
|
| 94 |
|
|
I_BTN <= R_BTN;
|
| 95 |
|
|
|
| 96 |
|
|
end sim;
|
