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[/] [w11/] [tags/] [w11a_V0.7/] [rtl/] [bplib/] [nexys4/] [nexys4lib.vhd] - Blame information for rev 33

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1 29 wfjm
-- $Id: nexys4lib.vhd 643 2015-02-07 17:41:53Z mueller $
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--
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-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Package Name:   nexys4lib
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-- Description:    Nexys 4 components
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-- 
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-- Dependencies:   -
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-- Tool versions:  ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31
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--
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-- Revision History: 
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-- Date         Rev Version  Comment
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-- 2015-02-06   643   1.2    factor out memory, add nexys4_cram_aif
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-- 2015-02-01   641   1.1    drop nexys4_fusp_aif; separate I_BTNRST_N
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-- 2013-09-21   534   1.0    Initial version 
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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package nexys4lib is
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component nexys4_aif is                 -- NEXYS 4, abstract iface, base
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  port (
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    I_CLK100 : in slbit;                -- 100 MHz clock
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    I_RXD : in slbit;                   -- receive data (board view)
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    O_TXD : out slbit;                  -- transmit data (board view)
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    O_RTS_N : out slbit;                -- rx rts (board view; act.low)
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    I_CTS_N : in slbit;                 -- tx cts (board view; act.low)
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    I_SWI : in slv16;                   -- n4 switches
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    I_BTN : in slv5;                    -- n4 buttons
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    I_BTNRST_N : in slbit;              -- n4 reset button
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    O_LED : out slv16;                  -- n4 leds
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    O_RGBLED0 : out slv3;               -- n4 rgb-led 0
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    O_RGBLED1 : out slv3;               -- n4 rgb-led 1
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    O_ANO_N : out slv8;                 -- 7 segment disp: anodes   (act.low)
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    O_SEG_N : out slv8                  -- 7 segment disp: segments (act.low)
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  );
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end component;
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component nexys4_cram_aif is            -- NEXYS 4, abstract iface, base+cram
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  port (
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    I_CLK100 : in slbit;                -- 100 MHz clock
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    I_RXD : in slbit;                   -- receive data (board view)
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    O_TXD : out slbit;                  -- transmit data (board view)
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    O_RTS_N : out slbit;                -- rx rts (board view; act.low)
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    I_CTS_N : in slbit;                 -- tx cts (board view; act.low)
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    I_SWI : in slv16;                   -- n4 switches
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    I_BTN : in slv5;                    -- n4 buttons
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    I_BTNRST_N : in slbit;              -- n4 reset button
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    O_LED : out slv16;                  -- n4 leds
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    O_RGBLED0 : out slv3;               -- n4 rgb-led 0
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    O_RGBLED1 : out slv3;               -- n4 rgb-led 1
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    O_ANO_N : out slv8;                 -- 7 segment disp: anodes   (act.low)
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    O_SEG_N : out slv8;                 -- 7 segment disp: segments (act.low)
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    O_MEM_CE_N : out slbit;             -- cram: chip enable   (act.low)
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    O_MEM_BE_N : out slv2;              -- cram: byte enables  (act.low)
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    O_MEM_WE_N : out slbit;             -- cram: write enable  (act.low)
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    O_MEM_OE_N : out slbit;             -- cram: output enable (act.low)
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    O_MEM_ADV_N  : out slbit;           -- cram: address valid (act.low)
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    O_MEM_CLK : out slbit;              -- cram: clock
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    O_MEM_CRE : out slbit;              -- cram: command register enable
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    I_MEM_WAIT : in slbit;              -- cram: mem wait
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    O_MEM_ADDR  : out slv23;            -- cram: address lines
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    IO_MEM_DATA : inout slv16           -- cram: data lines
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  );
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end component;
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end package nexys4lib;

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