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-- $Id: ibd_ibmon.vhd 672 2015-05-02 21:58:28Z mueller $
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--
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-- Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: ibd_ibmon - syn
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-- Description: ibus dev: ibus monitor
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--
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-- Dependencies: memlib/ram_1swsr_wfirst_gen
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--
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-- Test bench: -
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--
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-- Target Devices: generic
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-- Tool versions: xst 14.7; viv 2014.4; ghdl 0.31
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--
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2015-04-24 668 14.7 131013 xc6slx16-2 112 235 0 83 s 5.6
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2015-05-02 672 1.0.1 use natural for AWIDTH to work around a ghdl issue
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-- 2015-04-24 668 1.0 Initial version (derived from rbd_rbmon)
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------------------------------------------------------------------------------
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--
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-- Addr Bits Name r/w/f Function
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-- 000 cntl r/w/f Control register
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-- 05 conena r/w/- con enable
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-- 04 remena r/w/- rem enable
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-- 03 locena r/w/- loc enable
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-- 02 wena r/w/- wrap enable
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-- 01 stop r/w/f writing 1 stops moni
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-- 00 start r/w/f writing 1 starts moni and clears addr
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-- 001 stat r/w/- Status register
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-- 15:13 bsize r/-/- buffer size (AWIDTH-9)
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-- 00 wrap r/-/- line address wrapped (cleared on go)
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-- 010 12:01 hilim r/w/- upper address limit, inclusive (def: 177776)
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-- 011 12:01 lolim r/w/- lower address limit, inclusive (def: 160000)
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-- 100 addr r/w/- Address register
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-- *:02 laddr r/w/- line address
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-- 01:00 waddr r/w/- word address
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-- 101 data r/w/- Data register
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--
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-- data format:
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-- word 3 15 : burst (2nd re/we in a aval sequence)
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-- 14 : tout (busy in last re-we cycle)
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-- 13 : nak (no ack in last non-busy cycle)
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-- 12 : ack (ack seen)
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-- 11 : busy (busy seen)
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-- 10 : -- (reserved in case err is implemented)
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-- 09 : we (write cycle)
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-- 08 : rmw (read-modify-write)
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-- 07:00 : delay to prev (msb's)
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-- word 2 15:10 : delay to prev (lsb's)
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-- 09:00 : number of busy cycles
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-- word 1 : data
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-- word 0 15 : be1 (byte enable low)
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-- 14 : be0 (byte enable high)
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-- 13 : racc (remote access)
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-- 12:01 : addr (word address)
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-- 0 : cacc (console access)
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.memlib.all;
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use work.iblib.all;
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-- Note: AWIDTH has type natural to allow AWIDTH=0 can be used in if generates
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-- to control the instantiation. ghdl checks even for not instantiated
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-- entities the validity of generics, that's why natural needed here ....
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entity ibd_ibmon is -- ibus dev: ibus monitor
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generic (
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IB_ADDR : slv16 := slv(to_unsigned(8#160000#,16)); -- base address
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AWIDTH : natural := 9); -- buffer size
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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IB_MREQ : in ib_mreq_type; -- ibus: request
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IB_SRES : out ib_sres_type; -- ibus: response
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IB_SRES_SUM : in ib_sres_type -- ibus: response (sum for monitor)
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);
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end entity ibd_ibmon;
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architecture syn of ibd_ibmon is
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constant ibaddr_cntl : slv3 := "000"; -- cntl address offset
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constant ibaddr_stat : slv3 := "001"; -- stat address offset
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constant ibaddr_hilim : slv3 := "010"; -- hilim address offset
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constant ibaddr_lolim : slv3 := "011"; -- lolim address offset
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constant ibaddr_addr : slv3 := "100"; -- addr address offset
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constant ibaddr_data : slv3 := "101"; -- data address offset
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constant cntl_ibf_conena : integer := 5;
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constant cntl_ibf_remena : integer := 4;
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constant cntl_ibf_locena : integer := 3;
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constant cntl_ibf_wena : integer := 2;
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constant cntl_ibf_stop : integer := 1;
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constant cntl_ibf_start : integer := 0;
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subtype stat_ibf_bsize is integer range 15 downto 13;
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constant stat_ibf_wrap : integer := 0;
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subtype addr_ibf_laddr is integer range 2+AWIDTH-1 downto 2;
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subtype addr_ibf_waddr is integer range 1 downto 0;
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subtype iba_ibf_pref is integer range 15 downto 13;
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subtype iba_ibf_addr is integer range 12 downto 1;
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constant dat3_ibf_burst : integer := 15;
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constant dat3_ibf_tout : integer := 14;
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constant dat3_ibf_nak : integer := 13;
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constant dat3_ibf_ack : integer := 12;
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constant dat3_ibf_busy : integer := 11;
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constant dat3_ibf_we : integer := 9;
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constant dat3_ibf_rmw : integer := 8;
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subtype dat3_ibf_ndlymsb is integer range 7 downto 0;
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subtype dat2_ibf_ndlylsb is integer range 15 downto 10;
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subtype dat2_ibf_nbusy is integer range 9 downto 0;
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constant dat0_ibf_be1 : integer := 15;
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constant dat0_ibf_be0 : integer := 14;
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constant dat0_ibf_racc : integer := 13;
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subtype dat0_ibf_addr is integer range 12 downto 1;
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constant dat0_ibf_cacc : integer := 0;
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type regs_type is record -- state registers
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ibsel : slbit; -- ibus select
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conena : slbit; -- conena flag (record console access)
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remena : slbit; -- remena flag (record remote access)
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locena : slbit; -- locena flag (record local access)
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wena : slbit; -- wena flag (wrap enable)
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go : slbit; -- go flag
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hilim : slv13_1; -- upper address limit
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lolim : slv13_1; -- lower address limit
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wrap : slbit; -- laddr wrap flag
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laddr : slv(AWIDTH-1 downto 0); -- line address
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waddr : slv2; -- word address
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ibtake_1 : slbit; -- ib capture active in last cycle
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ibaddr : slv13_1; -- ibus trace: addr
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ibwe : slbit; -- ibus trace: we
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ibrmw : slbit; -- ibus trace: rmw
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ibbe0 : slbit; -- ibus trace: be0
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ibbe1 : slbit; -- ibus trace: be1
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ibcacc : slbit; -- ibus trace: cacc
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ibracc : slbit; -- ibus trace: racc
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iback : slbit; -- ibus trace: ack seen
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ibbusy : slbit; -- ibus trace: busy seen
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ibnak : slbit; -- ibus trace: nak detected
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ibtout : slbit; -- ibus trace: tout detected
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ibburst : slbit; -- ibus trace: burst detected
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ibdata : slv16; -- ibus trace: data
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ibnbusy : slv10; -- ibus number of busy cycles
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ibndly : slv14; -- ibus delay to prev. access
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end record regs_type;
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constant laddrzero : slv(AWIDTH-1 downto 0) := (others=>'0');
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constant laddrlast : slv(AWIDTH-1 downto 0) := (others=>'1');
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constant regs_init : regs_type := (
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'0', -- ibsel
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'1','1','1','1','1', -- conena,remena,locena,wena,go
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(others=>'1'), -- hilim (def: 177776)
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(others=>'0'), -- lolim (def: 160000)
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'0', -- wrap
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laddrzero, -- laddr
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"00", -- waddr
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'0', -- ibtake_1
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(others=>'0'), -- ibaddr
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'0','0','0','0','0','0', -- ibwe,ibrmw,ibbe0,ibbe1,ibcacc,ibracc
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'0','0', -- iback,ibbusy
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'0','0','0', -- ibnak,ibtout,ibburst
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(others=>'0'), -- ibdata
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(others=>'0'), -- ibnbusy
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(others=>'0') -- ibndly
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);
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constant ibnbusylast : slv10 := (others=>'1');
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constant ibndlylast : slv14 := (others=>'1');
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signal R_REGS : regs_type := regs_init;
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signal N_REGS : regs_type := regs_init;
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signal BRAM_EN : slbit := '0';
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signal BRAM_WE : slbit := '0';
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signal BRAM0_DI : slv32 := (others=>'0');
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signal BRAM1_DI : slv32 := (others=>'0');
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signal BRAM0_DO : slv32 := (others=>'0');
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signal BRAM1_DO : slv32 := (others=>'0');
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begin
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assert AWIDTH>=9 and AWIDTH<=14
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report "assert(AWIDTH>=9 and AWIDTH<=14): unsupported AWIDTH"
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severity failure;
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BRAM1 : ram_1swsr_wfirst_gen
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generic map (
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AWIDTH => AWIDTH,
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DWIDTH => 32)
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port map (
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CLK => CLK,
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EN => BRAM_EN,
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WE => BRAM_WE,
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ADDR => R_REGS.laddr,
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DI => BRAM1_DI,
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DO => BRAM1_DO
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);
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BRAM0 : ram_1swsr_wfirst_gen
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generic map (
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AWIDTH => AWIDTH,
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DWIDTH => 32)
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port map (
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CLK => CLK,
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EN => BRAM_EN,
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WE => BRAM_WE,
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ADDR => R_REGS.laddr,
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DI => BRAM0_DI,
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DO => BRAM0_DO
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);
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proc_regs: process (CLK)
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begin
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if rising_edge(CLK) then
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if RESET = '1' then
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R_REGS <= regs_init;
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else
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R_REGS <= N_REGS;
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end if;
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end if;
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end process proc_regs;
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proc_next : process (R_REGS, IB_MREQ, IB_SRES_SUM, BRAM0_DO, BRAM1_DO)
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variable r : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable iib_ack : slbit := '0';
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variable iib_busy : slbit := '0';
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variable iib_dout : slv16 := (others=>'0');
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variable iibena : slbit := '0';
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variable ibramen : slbit := '0'; -- BRAM enable
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variable ibramwe : slbit := '0'; -- BRAN we
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variable ibtake : slbit := '0';
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variable laddr_inc : slbit := '0';
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variable idat0 : slv16 := (others=>'0');
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variable idat1 : slv16 := (others=>'0');
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variable idat2 : slv16 := (others=>'0');
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variable idat3 : slv16 := (others=>'0');
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begin
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r := R_REGS;
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n := R_REGS;
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iib_ack := '0';
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iib_busy := '0';
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iib_dout := (others=>'0');
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iibena := IB_MREQ.re or IB_MREQ.we;
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ibramen := '0';
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ibramwe := '0';
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laddr_inc := '0';
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-- ibus address decoder
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n.ibsel := '0';
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if IB_MREQ.aval='1' and IB_MREQ.addr(12 downto 4)=IB_ADDR(12 downto 4) then
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n.ibsel := '1';
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ibramen := '1';
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end if;
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-- ibus transactions (react only on console (this includes racc))
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if r.ibsel = '1' and IB_MREQ.cacc='1' then
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iib_ack := iibena; -- ack all accesses
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case IB_MREQ.addr(3 downto 1) is
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when ibaddr_cntl => -- cntl ------------------
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if IB_MREQ.we = '1' then
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n.conena := IB_MREQ.din(cntl_ibf_conena);
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n.remena := IB_MREQ.din(cntl_ibf_remena);
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n.locena := IB_MREQ.din(cntl_ibf_locena);
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n.wena := IB_MREQ.din(cntl_ibf_wena);
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if IB_MREQ.din(cntl_ibf_start) = '1' then
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n.go := '1';
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n.wrap := '0';
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n.laddr := laddrzero;
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n.waddr := "00";
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end if;
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if IB_MREQ.din(cntl_ibf_stop) = '1' then
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n.go := '0';
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end if;
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end if;
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when ibaddr_stat => null; -- stat ------------------
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when ibaddr_hilim => -- hilim -----------------
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if IB_MREQ.we = '1' then
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n.hilim := IB_MREQ.din(iba_ibf_addr);
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end if;
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when ibaddr_lolim => -- lolim -----------------
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if IB_MREQ.we = '1' then
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n.lolim := IB_MREQ.din(iba_ibf_addr);
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end if;
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when ibaddr_addr => -- addr ------------------
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if IB_MREQ.we = '1' then
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n.go := '0';
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n.wrap := '0';
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n.laddr := IB_MREQ.din(addr_ibf_laddr);
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n.waddr := IB_MREQ.din(addr_ibf_waddr);
|
326 |
|
|
end if;
|
327 |
|
|
|
328 |
|
|
when ibaddr_data => -- data ------------------
|
329 |
|
|
if r.go='1' or IB_MREQ.we='1' then
|
330 |
|
|
iib_ack := '0'; -- error, do nak
|
331 |
|
|
end if;
|
332 |
|
|
if IB_MREQ.re = '1' then
|
333 |
|
|
n.waddr := slv(unsigned(r.waddr) + 1);
|
334 |
|
|
if r.waddr = "11" then
|
335 |
|
|
laddr_inc := '1';
|
336 |
|
|
end if;
|
337 |
|
|
end if;
|
338 |
|
|
|
339 |
|
|
when others => -- <> --------------------
|
340 |
|
|
iib_ack := '0'; -- error, do nak
|
341 |
|
|
|
342 |
|
|
end case;
|
343 |
|
|
end if;
|
344 |
|
|
|
345 |
|
|
-- ibus output driver
|
346 |
|
|
if r.ibsel = '1' then
|
347 |
|
|
case IB_MREQ.addr(3 downto 1) is
|
348 |
|
|
when ibaddr_cntl => -- cntl ------------------
|
349 |
|
|
iib_dout(cntl_ibf_conena) := r.conena;
|
350 |
|
|
iib_dout(cntl_ibf_remena) := r.remena;
|
351 |
|
|
iib_dout(cntl_ibf_locena) := r.locena;
|
352 |
|
|
iib_dout(cntl_ibf_wena) := r.wena;
|
353 |
|
|
iib_dout(cntl_ibf_start) := r.go;
|
354 |
|
|
when ibaddr_stat => -- stat ------------------
|
355 |
|
|
iib_dout(stat_ibf_bsize) := slv(to_unsigned(AWIDTH-9,3));
|
356 |
|
|
iib_dout(stat_ibf_wrap) := r.wrap;
|
357 |
|
|
when ibaddr_hilim => -- hilim -----------------
|
358 |
|
|
iib_dout(iba_ibf_pref) := (others=>'1');
|
359 |
|
|
iib_dout(iba_ibf_addr) := r.hilim;
|
360 |
|
|
when ibaddr_lolim => -- lolim -----------------
|
361 |
|
|
iib_dout(iba_ibf_pref) := (others=>'1');
|
362 |
|
|
iib_dout(iba_ibf_addr) := r.lolim;
|
363 |
|
|
when ibaddr_addr => -- addr ------------------
|
364 |
|
|
iib_dout(addr_ibf_laddr) := r.laddr;
|
365 |
|
|
iib_dout(addr_ibf_waddr) := r.waddr;
|
366 |
|
|
when ibaddr_data => -- data ------------------
|
367 |
|
|
case r.waddr is
|
368 |
|
|
when "11" => iib_dout := BRAM1_DO(31 downto 16);
|
369 |
|
|
when "10" => iib_dout := BRAM1_DO(15 downto 0);
|
370 |
|
|
when "01" => iib_dout := BRAM0_DO(31 downto 16);
|
371 |
|
|
when "00" => iib_dout := BRAM0_DO(15 downto 0);
|
372 |
|
|
when others => null;
|
373 |
|
|
end case;
|
374 |
|
|
when others => null;
|
375 |
|
|
end case;
|
376 |
|
|
end if;
|
377 |
|
|
|
378 |
|
|
-- ibus monitor
|
379 |
|
|
-- a ibus transaction are captured if the address is in alim window
|
380 |
|
|
-- and the access is not refering to ibd_ibmon itself
|
381 |
|
|
|
382 |
|
|
ibtake := '0';
|
383 |
|
|
if IB_MREQ.aval='1' and iibena='1' then -- aval and (re or we)
|
384 |
|
|
if unsigned(IB_MREQ.addr)>=unsigned(r.lolim) and -- and in addr window
|
385 |
|
|
unsigned(IB_MREQ.addr)<=unsigned(r.hilim) and
|
386 |
|
|
r.ibsel='0' then -- and not self
|
387 |
|
|
if (r.locena='1' and IB_MREQ.cacc='0' and IB_MREQ.racc='0') or
|
388 |
|
|
(r.remena='1' and IB_MREQ.racc='1') or
|
389 |
|
|
(r.conena='1' and IB_MREQ.cacc='1') then
|
390 |
|
|
ibtake := '1';
|
391 |
|
|
end if;
|
392 |
|
|
end if;
|
393 |
|
|
end if;
|
394 |
|
|
|
395 |
|
|
if ibtake = '1' then -- if capture active
|
396 |
|
|
n.ibaddr := IB_MREQ.addr; -- keep track of some state
|
397 |
|
|
n.ibwe := IB_MREQ.we;
|
398 |
|
|
n.ibrmw := IB_MREQ.rmw;
|
399 |
|
|
n.ibbe0 := IB_MREQ.be0;
|
400 |
|
|
n.ibbe1 := IB_MREQ.be1;
|
401 |
|
|
n.ibcacc := IB_MREQ.cacc;
|
402 |
|
|
n.ibracc := IB_MREQ.racc;
|
403 |
|
|
if IB_MREQ.we='1' then -- for write of din
|
404 |
|
|
n.ibdata := IB_MREQ.din;
|
405 |
|
|
else -- for read of dout
|
406 |
|
|
n.ibdata := IB_SRES_SUM.dout;
|
407 |
|
|
end if;
|
408 |
|
|
|
409 |
|
|
if r.ibtake_1 = '0' then -- if initial cycle of a transaction
|
410 |
|
|
n.iback := IB_SRES_SUM.ack;
|
411 |
|
|
n.ibbusy := IB_SRES_SUM.busy;
|
412 |
|
|
n.ibnbusy := (others=>'0');
|
413 |
|
|
else -- if non-initial cycles
|
414 |
|
|
if r.ibnbusy /= ibnbusylast then -- and count
|
415 |
|
|
n.ibnbusy := slv(unsigned(r.ibnbusy) + 1);
|
416 |
|
|
end if;
|
417 |
|
|
end if;
|
418 |
|
|
n.ibnak := not IB_SRES_SUM.ack;
|
419 |
|
|
n.ibtout := IB_SRES_SUM.busy;
|
420 |
|
|
|
421 |
|
|
else -- if capture not active
|
422 |
|
|
if r.go='1' and r.ibtake_1='1' then -- active and transaction just ended
|
423 |
|
|
ibramen := '1';
|
424 |
|
|
ibramwe := '1';
|
425 |
|
|
laddr_inc := '1';
|
426 |
|
|
n.ibburst := '1'; -- assume burst
|
427 |
|
|
end if;
|
428 |
|
|
if r.ibtake_1 = '1' then -- ibus transaction just ended
|
429 |
|
|
n.ibndly := (others=>'0'); -- clear delay counter
|
430 |
|
|
else -- just idle
|
431 |
|
|
if r.ibndly /= ibndlylast then -- count cycles
|
432 |
|
|
n.ibndly := slv(unsigned(r.ibndly) + 1);
|
433 |
|
|
end if;
|
434 |
|
|
end if;
|
435 |
|
|
end if;
|
436 |
|
|
|
437 |
|
|
if IB_MREQ.aval = '0' then -- if aval gone
|
438 |
|
|
n.ibburst := '0'; -- clear burst flag
|
439 |
|
|
end if;
|
440 |
|
|
|
441 |
|
|
if laddr_inc = '1' then
|
442 |
|
|
n.laddr := slv(unsigned(r.laddr) + 1);
|
443 |
|
|
if r.go='1' and r.laddr=laddrlast then
|
444 |
|
|
if r.wena = '1' then
|
445 |
|
|
n.wrap := '1';
|
446 |
|
|
else
|
447 |
|
|
n.go := '0';
|
448 |
|
|
end if;
|
449 |
|
|
end if;
|
450 |
|
|
end if;
|
451 |
|
|
|
452 |
|
|
idat3 := (others=>'0');
|
453 |
|
|
idat3(dat3_ibf_burst) := r.ibburst;
|
454 |
|
|
idat3(dat3_ibf_tout) := r.ibtout;
|
455 |
|
|
idat3(dat3_ibf_nak) := r.ibnak;
|
456 |
|
|
idat3(dat3_ibf_ack) := r.iback;
|
457 |
|
|
idat3(dat3_ibf_busy) := r.ibbusy;
|
458 |
|
|
idat3(dat3_ibf_we) := r.ibwe;
|
459 |
|
|
idat3(dat3_ibf_rmw) := r.ibrmw;
|
460 |
|
|
idat3(dat3_ibf_ndlymsb):= r.ibndly(13 downto 6);
|
461 |
|
|
idat2(dat2_ibf_ndlylsb):= r.ibndly( 5 downto 0);
|
462 |
|
|
idat2(dat2_ibf_nbusy) := r.ibnbusy;
|
463 |
|
|
idat1 := r.ibdata;
|
464 |
|
|
idat0(dat0_ibf_be1) := r.ibbe1;
|
465 |
|
|
idat0(dat0_ibf_be0) := r.ibbe0;
|
466 |
|
|
idat0(dat0_ibf_racc) := r.ibracc;
|
467 |
|
|
idat0(dat0_ibf_addr) := r.ibaddr;
|
468 |
|
|
idat0(dat0_ibf_cacc) := r.ibcacc;
|
469 |
|
|
|
470 |
|
|
n.ibtake_1 := ibtake;
|
471 |
|
|
|
472 |
|
|
N_REGS <= n;
|
473 |
|
|
|
474 |
|
|
BRAM_EN <= ibramen;
|
475 |
|
|
BRAM_WE <= ibramwe;
|
476 |
|
|
|
477 |
|
|
BRAM1_DI <= idat3 & idat2;
|
478 |
|
|
BRAM0_DI <= idat1 & idat0;
|
479 |
|
|
|
480 |
|
|
IB_SRES.dout <= iib_dout;
|
481 |
|
|
IB_SRES.ack <= iib_ack;
|
482 |
|
|
IB_SRES.busy <= iib_busy;
|
483 |
|
|
|
484 |
|
|
end process proc_next;
|
485 |
|
|
|
486 |
|
|
end syn;
|