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-- $Id: ibdr_pc11.vhd 427 2011-11-19 21:04:11Z mueller $
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--
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-- Copyright 2009-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: ibdr_pc11 - syn
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-- Description: ibus dev(rem): PC11
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--
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-- Dependencies: -
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-- Test bench: xxdp: zpcae0
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-- Target Devices: generic
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-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
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--
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2010-10-17 333 12.1 M53d xc3s1000-4 26 97 0 57 s 6.0
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-- 2009-06-28 230 10.1.03 K39 xc3s1000-4 25 92 0 54 s 4.9
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2011-11-18 427 1.2.2 now numeric_std clean
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-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
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-- 2010-10-17 333 1.2 use ibus V2 interface
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-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
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-- 2009-06-28 230 1.0 prdy now inits to '1'; setting err bit in csr now
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-- causes interrupt, if enabled; validated with zpcae0
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-- 2009-06-01 221 0.9 Initial version (untested)
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.iblib.all;
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-- ----------------------------------------------------------------------------
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entity ibdr_pc11 is -- ibus dev(rem): PC11
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-- fixed address: 177550
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- system reset
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BRESET : in slbit; -- ibus reset
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RB_LAM : out slbit; -- remote attention
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_SRES : out ib_sres_type; -- ibus response
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EI_REQ_PTR : out slbit; -- interrupt request, reader
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EI_REQ_PTP : out slbit; -- interrupt request, punch
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EI_ACK_PTR : in slbit; -- interrupt acknowledge, reader
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EI_ACK_PTP : in slbit -- interrupt acknowledge, punch
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);
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end ibdr_pc11;
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architecture syn of ibdr_pc11 is
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constant ibaddr_pc11 : slv16 := slv(to_unsigned(8#177550#,16));
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constant ibaddr_rcsr : slv2 := "00"; -- rcsr address offset
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constant ibaddr_rbuf : slv2 := "01"; -- rbuf address offset
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constant ibaddr_pcsr : slv2 := "10"; -- pcsr address offset
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constant ibaddr_pbuf : slv2 := "11"; -- pbuf address offset
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constant rcsr_ibf_rerr : integer := 15;
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constant rcsr_ibf_rbusy : integer := 11;
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constant rcsr_ibf_rdone : integer := 7;
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constant rcsr_ibf_rie : integer := 6;
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constant rcsr_ibf_renb : integer := 0;
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constant pcsr_ibf_perr : integer := 15;
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constant pcsr_ibf_prdy : integer := 7;
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constant pcsr_ibf_pie : integer := 6;
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constant pbuf_ibf_pval : integer := 8;
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constant pbuf_ibf_rbusy : integer := 9;
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type regs_type is record -- state registers
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ibsel : slbit; -- ibus select
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rerr : slbit; -- rcsr: reader error
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rbusy : slbit; -- rcsr: reader busy
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rdone : slbit; -- rcsr: reader done
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rie : slbit; -- rcsr: reader interrupt enable
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rbuf : slv8; -- rbuf:
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rintreq : slbit; -- ptr interrupt request
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perr : slbit; -- pcsr: punch error
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prdy : slbit; -- pcsr: punch ready
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pie : slbit; -- pcsr: punch interrupt enable
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pbuf : slv8; -- pbuf:
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pintreq : slbit; -- ptp interrupt request
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end record regs_type;
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constant regs_init : regs_type := (
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'0', -- ibsel
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'1', -- rerr (init=1!)
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'0','0','0', -- rbusy,rdone,rie
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(others=>'0'), -- rbuf
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'0', -- rintreq
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'1', -- perr (init=1!)
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'1', -- prdy (init=1!)
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'0', -- pie
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(others=>'0'), -- pbuf
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'0' -- pintreq
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);
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signal R_REGS : regs_type := regs_init;
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signal N_REGS : regs_type := regs_init;
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begin
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proc_regs: process (CLK)
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begin
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if rising_edge(CLK) then
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if BRESET = '1' then -- BRESET is 1 for system and ibus reset
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R_REGS <= regs_init; --
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if RESET = '0' then -- if RESET=0 we do just an ibus reset
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R_REGS.rerr <= N_REGS.rerr; -- don't reset RERR flag
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R_REGS.perr <= N_REGS.perr; -- don't reset PERR flag
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end if;
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else
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2 |
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R_REGS <= N_REGS;
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end if;
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end if;
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end process proc_regs;
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proc_next : process (R_REGS, IB_MREQ, EI_ACK_PTR, EI_ACK_PTP)
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variable r : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable idout : slv16 := (others=>'0');
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variable ibreq : slbit := '0';
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variable ibrd : slbit := '0';
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variable ibw0 : slbit := '0';
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variable ibw1 : slbit := '0';
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variable ilam : slbit := '0';
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begin
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r := R_REGS;
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n := R_REGS;
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idout := (others=>'0');
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ibreq := IB_MREQ.re or IB_MREQ.we;
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ibrd := IB_MREQ.re;
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ibw0 := IB_MREQ.we and IB_MREQ.be0;
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ibw1 := IB_MREQ.we and IB_MREQ.be1;
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ilam := '0';
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wfjm |
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-- ibus address decoder
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n.ibsel := '0';
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if IB_MREQ.aval='1' and
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IB_MREQ.addr(12 downto 3)=ibaddr_pc11(12 downto 3) then
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n.ibsel := '1';
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end if;
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-- ibus transactions
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if r.ibsel = '1' then
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case IB_MREQ.addr(2 downto 1) is
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when ibaddr_rcsr => -- RCSR -- reader control status -----
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idout(rcsr_ibf_rerr) := r.rerr;
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idout(rcsr_ibf_rbusy) := r.rbusy;
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idout(rcsr_ibf_rdone) := r.rdone;
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idout(rcsr_ibf_rie) := r.rie;
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if IB_MREQ.racc = '0' then -- cpu ---------------------
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if ibw0 = '1' then
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n.rie := IB_MREQ.din(rcsr_ibf_rie);
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if IB_MREQ.din(rcsr_ibf_rie) = '1' then-- set IE to 1
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if r.rie = '0' and -- IE 0->1 transition
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IB_MREQ.din(rcsr_ibf_renb)='0' and -- when RENB not set
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(r.rerr='1' or r.rdone='1') then -- but err or done set
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n.rintreq := '1'; -- request interrupt
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end if;
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else -- set IE to 0
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n.rintreq := '0'; -- cancel interrupts
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end if;
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if IB_MREQ.din(rcsr_ibf_renb) = '1' then -- set RENB
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if r.rerr = '0' then -- if not in error state
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n.rbusy := '1'; -- set busy
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n.rdone := '0'; -- clear done
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| 188 |
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n.rbuf := (others=>'0'); -- clear buffer
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| 189 |
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n.rintreq := '0'; -- cancel interrupt
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ilam := '1'; -- rri lam
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else -- if in error state
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if r.rie = '1' then -- if interrupts on
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n.rintreq := '1'; -- request interrupt
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end if;
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end if;
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end if;
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end if;
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else -- rri ---------------------
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if ibw1 = '1' then
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n.rerr := IB_MREQ.din(rcsr_ibf_rerr); -- set ERR bit
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if IB_MREQ.din(rcsr_ibf_rerr)='1' -- if 0->1 transition
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and r.rerr='0' then
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n.rbusy := '0'; -- clear busy
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n.rdone := '0'; -- clear done
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| 206 |
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if r.rie = '1' then -- if interrupts on
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n.rintreq := '1'; -- request interrupt
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end if;
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| 209 |
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end if;
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| 210 |
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end if;
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| 211 |
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end if;
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| 212 |
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| 213 |
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when ibaddr_rbuf => -- RBUF -- reader data buffer --------
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| 215 |
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idout(r.rbuf'range) := r.rbuf;
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| 217 |
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if IB_MREQ.racc = '0' then -- cpu ---------------------
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| 218 |
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if true then -- !! PC11 is unusual !!
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| 219 |
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n.rdone := '0'; -- any read or write will clear done
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| 220 |
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n.rbuf := (others=>'0'); -- and the reader buffer
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| 221 |
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n.rintreq := '0'; -- also interrupt is canceled
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| 222 |
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end if;
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| 223 |
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| 224 |
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else -- rri ---------------------
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| 225 |
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if ibw0 = '1' then
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| 226 |
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n.rbuf := IB_MREQ.din(n.rbuf'range);
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| 227 |
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n.rbusy := '0';
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| 228 |
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n.rdone := '1';
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| 229 |
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if r.rie = '1' then
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| 230 |
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n.rintreq := '1';
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| 231 |
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end if;
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| 232 |
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end if;
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| 233 |
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end if;
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| 234 |
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| 235 |
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when ibaddr_pcsr => -- PCSR -- punch control status ------
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| 236 |
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| 237 |
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idout(pcsr_ibf_perr) := r.perr;
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| 238 |
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idout(pcsr_ibf_prdy) := r.prdy;
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| 239 |
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idout(pcsr_ibf_pie) := r.pie;
|
| 240 |
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| 241 |
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if IB_MREQ.racc = '0' then -- cpu ---------------------
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| 242 |
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if ibw0 = '1' then
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| 243 |
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n.pie := IB_MREQ.din(pcsr_ibf_pie);
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| 244 |
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if IB_MREQ.din(pcsr_ibf_pie) = '1' then-- set IE to 1
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| 245 |
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if r.pie='0' and -- IE 0->1 transition
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| 246 |
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(r.perr='1' or r.prdy='1') then -- but err or done set
|
| 247 |
|
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n.pintreq := '1'; -- request interrupt
|
| 248 |
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end if;
|
| 249 |
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else -- set IE to 0
|
| 250 |
|
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n.pintreq := '0'; -- cancel interrupts
|
| 251 |
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end if;
|
| 252 |
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end if;
|
| 253 |
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| 254 |
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else -- rri ---------------------
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| 255 |
|
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if ibw1 = '1' then
|
| 256 |
|
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n.perr := IB_MREQ.din(pcsr_ibf_perr); -- set ERR bit
|
| 257 |
|
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if IB_MREQ.din(pcsr_ibf_perr)='1' -- if 0->1 transition
|
| 258 |
|
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and r.perr='0' then
|
| 259 |
|
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n.prdy := '1'; -- set ready
|
| 260 |
|
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if r.pie = '1' then -- if interrupts on
|
| 261 |
|
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n.pintreq := '1'; -- request interrupt
|
| 262 |
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end if;
|
| 263 |
|
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end if;
|
| 264 |
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end if;
|
| 265 |
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end if;
|
| 266 |
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|
| 267 |
|
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when ibaddr_pbuf => -- PBUF -- punch data buffer ---------
|
| 268 |
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|
| 269 |
|
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if IB_MREQ.racc = '0' then -- cpu ---------------------
|
| 270 |
|
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if ibw0 = '1' then
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| 271 |
|
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if r.perr = '0' then -- if not in error state
|
| 272 |
|
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n.pbuf := IB_MREQ.din(n.pbuf'range);
|
| 273 |
|
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n.prdy := '0'; -- clear ready
|
| 274 |
|
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n.pintreq := '0'; -- cancel interrupts
|
| 275 |
|
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ilam := '1'; -- rri lam
|
| 276 |
|
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else -- if in error state
|
| 277 |
|
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if r.pie = '1' then -- if interrupts on
|
| 278 |
|
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n.pintreq := '1'; -- request interrupt
|
| 279 |
|
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end if;
|
| 280 |
|
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end if;
|
| 281 |
|
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end if;
|
| 282 |
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|
| 283 |
|
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else -- rri ---------------------
|
| 284 |
|
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idout(r.pbuf'range) := r.pbuf;
|
| 285 |
|
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idout(pbuf_ibf_pval) := not r.prdy;
|
| 286 |
|
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idout(pbuf_ibf_rbusy) := r.rbusy;
|
| 287 |
|
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if ibrd = '1' then
|
| 288 |
|
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n.prdy := '1';
|
| 289 |
|
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if r.pie = '1' then
|
| 290 |
|
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n.pintreq := '1';
|
| 291 |
|
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end if;
|
| 292 |
|
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end if;
|
| 293 |
|
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end if;
|
| 294 |
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|
| 295 |
|
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when others => null;
|
| 296 |
|
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end case;
|
| 297 |
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|
| 298 |
|
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end if;
|
| 299 |
|
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|
| 300 |
|
|
-- other state changes
|
| 301 |
|
|
if EI_ACK_PTR = '1' then
|
| 302 |
|
|
n.rintreq := '0';
|
| 303 |
|
|
end if;
|
| 304 |
|
|
if EI_ACK_PTP = '1' then
|
| 305 |
|
|
n.pintreq := '0';
|
| 306 |
|
|
end if;
|
| 307 |
|
|
|
| 308 |
|
|
N_REGS <= n;
|
| 309 |
|
|
|
| 310 |
|
|
IB_SRES.dout <= idout;
|
| 311 |
8 |
wfjm |
IB_SRES.ack <= r.ibsel and ibreq;
|
| 312 |
2 |
wfjm |
IB_SRES.busy <= '0';
|
| 313 |
|
|
|
| 314 |
8 |
wfjm |
RB_LAM <= ilam;
|
| 315 |
2 |
wfjm |
EI_REQ_PTR <= r.rintreq;
|
| 316 |
|
|
EI_REQ_PTP <= r.pintreq;
|
| 317 |
|
|
|
| 318 |
|
|
end process proc_next;
|
| 319 |
|
|
|
| 320 |
|
|
|
| 321 |
|
|
end syn;
|
