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[/] [w11/] [tags/] [w11a_V0.7/] [rtl/] [make_viv/] [generic_vivado.mk] - Blame information for rev 36

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# $Id: generic_vivado.mk 646 2015-02-15 12:04:55Z mueller $
#
# Copyright 2015- by Walter F.J. Mueller 
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Revision History:
# Date         Rev Version  Comment
# 2015-02-15   646   1.0    Initial version
# 2015-01-25   637   0.1    First draft
#---
#
# check that part is defined
#
ifndef VIV_BOARD_SETUP
$(error VIV_BOARD_SETUP is not defined)
endif
#
# ensure that default tools and flows are defined
#
ifndef VIV_INIT
VIV_INIT = $(RETROBASE)/rtl/make_viv/viv_init.tcl
endif
ifndef VIV_BUILD_FLOW
VIV_BUILD_FLOW = $(RETROBASE)/rtl/make_viv/viv_default_build.tcl
endif
ifndef VIV_CONFIG_FLOW
VIV_CONFIG_FLOW = $(RETROBASE)/rtl/make_viv/viv_default_config.tcl
endif
ifndef VIV_MODEL_FLOW
VIV_MODEL_FLOW = $(RETROBASE)/rtl/make_viv/viv_default_model.tcl
endif
#
# $@ first target
# $< first dependency
# $* stem in rule match
#
# when chaining, don't delete 'expensive' intermediate files:
.SECONDARY :
#
# Synthesize + Implement -> generate bit file
#   input:   %.vbom     vbom project description
#   output:  %.bit
#
%.bit : %.vbom
        rm -rf project_mflow
        xtwv vivado -mode batch \
                -source ${VIV_INIT} \
                -source ${VIV_BOARD_SETUP} \
                -source ${VIV_BUILD_FLOW} \
                -tclargs $* bit
#
# Configure FPGA with vivado hardware server
#   input:   %.bit
#   output:  .PHONY
#
%.vconfig : %.bit
        xtwv vivado -mode batch \
                -source ${VIV_INIT} \
                -source ${VIV_BOARD_SETUP} \
                -source ${VIV_CONFIG_FLOW} \
                -tclargs $*
#
# Partial Synthesize + Implement -> generate dcp for model generation
#
%_syn.dcp : %.vbom
        rm -rf project_mflow
        xtwv vivado -mode batch \
                -source ${VIV_INIT} \
                -source ${VIV_BOARD_SETUP} \
                -source ${VIV_BUILD_FLOW} \
                -tclargs $* syn
%_opt.dcp %_rou.dcp : %.vbom
        rm -rf project_mflow
        xtwv vivado -mode batch \
                -source ${VIV_INIT} \
                -source ${VIV_BOARD_SETUP} \
                -source ${VIV_BUILD_FLOW} \
                -tclargs $* imp
#
# Post-synthesis functional simulation model (Vhdl/Unisim)
#   input:   %_syn.dcp
#   output:  %_ssim.vhd
#
%_ssim.vhd : %_syn.dcp
        xtwv vivado -mode batch \
                -source ${VIV_INIT} \
                -source ${VIV_MODEL_FLOW} \
                -tclargs $* ssim
#
# Post-optimization functional simulation model (Vhdl/Unisim)
#   input:   %_opt.dcp
#   output:  %_osim.vhd
#
%_osim.vhd : %_opt.dcp
        xtwv vivado -mode batch \
                -source ${VIV_INIT} \
                -source ${VIV_MODEL_FLOW} \
                -tclargs $* osim
#
# Post-routing timing simulation model (Verilog/Simprim)
#   input:   %_rou.dcp
#   output:  %_tsim.v
#            %_tsim.sdf
#
%_tsim.v %_tsim.sdf : %_rou.dcp
        xtwv vivado -mode batch \
                -source ${VIV_INIT} \
                -source ${VIV_MODEL_FLOW} \
                -tclargs $* tsim
#
# vivado project quick starter
#
.PHONY : vivado
vivado :
        xtwv vivado -mode gui project_mflow/project_mflow.xpr
 
#
# generate dep_vsyn files from vbom
#
%.dep_vsyn: %.vbom
        vbomconv --dep_vsyn $< > $@
 
#
# Cleanup
#
include $(RETROBASE)/rtl/make_viv/dontincdep.mk
#
.PHONY : viv_clean viv_tmp_clean
#
viv_clean: viv_tmp_clean
        rm -f *.bit
        rm -f *.dcp
        rm -f *.jou
        rm -f *.log
        rm -f *.rpt
        rm -f *_[so]sim.vhd
        rm -f *_tsim.v
        rm -f *_tsim.sdf
#
viv_tmp_clean:
        rm -rf ./project_mflow
#

Line No.	Rev	Author	Line
1	29	wfjm	`# $Id: generic_vivado.mk 646 2015-02-15 12:04:55Z mueller $`
2			`#`
3			`# Copyright 2015- by Walter F.J. Mueller`
4			`# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory`
5			`#`
6			`# Revision History:`
7			`# Date Rev Version Comment`
8			`# 2015-02-15 646 1.0 Initial version`
9			`# 2015-01-25 637 0.1 First draft`
10			`#---`
11			`#`
12			`# check that part is defined`
13			`#`
14			`ifndef VIV_BOARD_SETUP`
15			`$(error VIV_BOARD_SETUP is not defined)`
16			`endif`
17			`#`
18			`# ensure that default tools and flows are defined`
19			`#`
20			`ifndef VIV_INIT`
21			`VIV_INIT = $(RETROBASE)/rtl/make_viv/viv_init.tcl`
22			`endif`
23			`ifndef VIV_BUILD_FLOW`
24			`VIV_BUILD_FLOW = $(RETROBASE)/rtl/make_viv/viv_default_build.tcl`
25			`endif`
26			`ifndef VIV_CONFIG_FLOW`
27			`VIV_CONFIG_FLOW = $(RETROBASE)/rtl/make_viv/viv_default_config.tcl`
28			`endif`
29			`ifndef VIV_MODEL_FLOW`
30			`VIV_MODEL_FLOW = $(RETROBASE)/rtl/make_viv/viv_default_model.tcl`
31			`endif`
32			`#`
33			`# $@ first target`
34			`# $< first dependency`
35			`# $* stem in rule match`
36			`#`
37			`# when chaining, don't delete 'expensive' intermediate files:`
38			`.SECONDARY :`
39			`#`
40			`# Synthesize + Implement -> generate bit file`
41			`# input: %.vbom vbom project description`
42			`# output: %.bit`
43			`#`
44			`%.bit : %.vbom`
45			`rm -rf project_mflow`
46			`xtwv vivado -mode batch \`
47			`-source ${VIV_INIT} \`
48			`-source ${VIV_BOARD_SETUP} \`
49			`-source ${VIV_BUILD_FLOW} \`
50			`-tclargs $* bit`
51			`#`
52			`# Configure FPGA with vivado hardware server`
53			`# input: %.bit`
54			`# output: .PHONY`
55			`#`
56			`%.vconfig : %.bit`
57			`xtwv vivado -mode batch \`
58			`-source ${VIV_INIT} \`
59			`-source ${VIV_BOARD_SETUP} \`
60			`-source ${VIV_CONFIG_FLOW} \`
61			`-tclargs $*`
62			`#`
63			`# Partial Synthesize + Implement -> generate dcp for model generation`
64			`#`
65			`%_syn.dcp : %.vbom`
66			`rm -rf project_mflow`
67			`xtwv vivado -mode batch \`
68			`-source ${VIV_INIT} \`
69			`-source ${VIV_BOARD_SETUP} \`
70			`-source ${VIV_BUILD_FLOW} \`
71			`-tclargs $* syn`
72			`%_opt.dcp %_rou.dcp : %.vbom`
73			`rm -rf project_mflow`
74			`xtwv vivado -mode batch \`
75			`-source ${VIV_INIT} \`
76			`-source ${VIV_BOARD_SETUP} \`
77			`-source ${VIV_BUILD_FLOW} \`
78			`-tclargs $* imp`
79			`#`
80			`# Post-synthesis functional simulation model (Vhdl/Unisim)`
81			`# input: %_syn.dcp`
82			`# output: %_ssim.vhd`
83			`#`
84			`%_ssim.vhd : %_syn.dcp`
85			`xtwv vivado -mode batch \`
86			`-source ${VIV_INIT} \`
87			`-source ${VIV_MODEL_FLOW} \`
88			`-tclargs $* ssim`
89			`#`
90			`# Post-optimization functional simulation model (Vhdl/Unisim)`
91			`# input: %_opt.dcp`
92			`# output: %_osim.vhd`
93			`#`
94			`%_osim.vhd : %_opt.dcp`
95			`xtwv vivado -mode batch \`
96			`-source ${VIV_INIT} \`
97			`-source ${VIV_MODEL_FLOW} \`
98			`-tclargs $* osim`
99			`#`
100			`# Post-routing timing simulation model (Verilog/Simprim)`
101			`# input: %_rou.dcp`
102			`# output: %_tsim.v`
103			`# %_tsim.sdf`
104			`#`
105			`%_tsim.v %_tsim.sdf : %_rou.dcp`
106			`xtwv vivado -mode batch \`
107			`-source ${VIV_INIT} \`
108			`-source ${VIV_MODEL_FLOW} \`
109			`-tclargs $* tsim`
110			`#`
111			`# vivado project quick starter`
112			`#`
113			`.PHONY : vivado`
114			`vivado :`
115			`xtwv vivado -mode gui project_mflow/project_mflow.xpr`
116
117			`#`
118			`# generate dep_vsyn files from vbom`
119			`#`
120			`%.dep_vsyn: %.vbom`
121			`vbomconv --dep_vsyn $< > $@`
122
123			`#`
124			`# Cleanup`
125			`#`
126			`include $(RETROBASE)/rtl/make_viv/dontincdep.mk`
127			`#`
128			`.PHONY : viv_clean viv_tmp_clean`
129			`#`
130			`viv_clean: viv_tmp_clean`
131			`rm -f *.bit`
132			`rm -f *.dcp`
133			`rm -f *.jou`
134			`rm -f *.log`
135			`rm -f *.rpt`
136			`rm -f *_[so]sim.vhd`
137			`rm -f *_tsim.v`
138			`rm -f *_tsim.sdf`
139			`#`
140			`viv_tmp_clean:`
141			`rm -rf ./project_mflow`
142			`#`

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[/] [w11/] [tags/] [w11a_V0.7/] [rtl/] [make_viv/] [generic_vivado.mk] - Blame information for rev 36