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-- $Id: ram_2swsr_xfirst_gen_unisim.vhd 686 2015-06-04 21:08:08Z mueller $
--
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name:    ram_2swsr_xfirst_gen_unisim - syn
-- Description:    Dual-Port RAM with with two synchronous read/write ports
--                 Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies:   -
-- Test bench:     -
-- Target Devices: Spartan-3, Virtex-2,-4
-- Tool versions:  ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31
-- Revision History: 
-- Date         Rev Version  Comment
-- 2011-08-14   406   1.0.2  cleaner code for L_DI(A|B) initialization
-- 2008-04-13   135   1.0.1  fix range error for AW_14_S1
-- 2008-03-08   123   1.0    Initial version (merged from _rfirst/_wfirst) 
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
library unisim;
use unisim.vcomponents.ALL;
 
use work.slvtypes.all;
 
entity ram_2swsr_xfirst_gen_unisim is   -- RAM, 2 sync r/w ports
  generic (
    AWIDTH : positive := 11;            -- address port width
    DWIDTH : positive :=  9;            -- data port width
    WRITE_MODE : string := "READ_FIRST"); -- write mode: (READ|WRITE)_FIRST
  port(
    CLKA  : in slbit;                   -- clock port A
    CLKB  : in slbit;                   -- clock port B
    ENA   : in slbit;                   -- enable port A
    ENB   : in slbit;                   -- enable port B
    WEA   : in slbit;                   -- write enable port A
    WEB   : in slbit;                   -- write enable port B
    ADDRA : in slv(AWIDTH-1 downto 0);  -- address port A
    ADDRB : in slv(AWIDTH-1 downto 0);  -- address port B
    DIA   : in slv(DWIDTH-1 downto 0);  -- data in port A
    DIB   : in slv(DWIDTH-1 downto 0);  -- data in port B
    DOA   : out slv(DWIDTH-1 downto 0); -- data out port A
    DOB   : out slv(DWIDTH-1 downto 0)  -- data out port B
  );
end ram_2swsr_xfirst_gen_unisim;
 
 
architecture syn of ram_2swsr_xfirst_gen_unisim is
 
  constant ok_mod32 : boolean := (DWIDTH mod 32)=0 and
                                 ((DWIDTH+35)/36)=((DWIDTH+31)/32);
  constant ok_mod16 : boolean := (DWIDTH mod 16)=0 and
                                 ((DWIDTH+17)/18)=((DWIDTH+16)/16);
  constant ok_mod08 : boolean := (DWIDTH mod 32)=0 and
                                 ((DWIDTH+8)/9)=((DWIDTH+7)/8);
 
begin
 
  assert AWIDTH>=9 and AWIDTH<=14
    report "assert(AWIDTH>=9 and AWIDTH<=14): unsupported BRAM from factor"
    severity failure;
 
  AW_09_S36: if AWIDTH=9 and not ok_mod32 generate
    constant dw_mem : positive := ((DWIDTH+35)/36)*36;
    signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
  begin
 
    DI_PAD: if dw_mem>DWIDTH generate
      L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
      L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
    end generate DI_PAD;
    L_DIA(DIA'range) <= DIA;
    L_DIB(DIB'range) <= DIB;
 
   GL: for i in dw_mem/36-1 downto 0 generate
      MEM : RAMB16_S36_S36
        generic map (
          INIT_A       => O"000000000000",
          INIT_B       => O"000000000000",
          SRVAL_A      => O"000000000000",
          SRVAL_B      => O"000000000000",
          WRITE_MODE_A => WRITE_MODE,
          WRITE_MODE_B => WRITE_MODE)
        port map (
          DOA   => L_DOA(36*i+31 downto 36*i),
          DOB   => L_DOB(36*i+31 downto 36*i),
          DOPA  => L_DOA(36*i+35 downto 36*i+32),
          DOPB  => L_DOB(36*i+35 downto 36*i+32),
          ADDRA => ADDRA,
          ADDRB => ADDRB,
          CLKA  => CLKA,
          CLKB  => CLKB,
          DIA   => L_DIA(36*i+31 downto 36*i),
          DIB   => L_DIB(36*i+31 downto 36*i),
          DIPA  => L_DIA(36*i+35 downto 36*i+32),
          DIPB  => L_DIB(36*i+35 downto 36*i+32),
          ENA   => ENA,
          ENB   => ENB,
          SSRA  => '0',
          SSRB  => '0',
          WEA   => WEA,
          WEB   => WEB
        );
    end generate GL;
 
    DOA <= L_DOA(DOA'range);
    DOB <= L_DOB(DOB'range);
 
  end generate AW_09_S36;
 
  AW_09_S32: if AWIDTH=9 and ok_mod32 generate
    GL: for i in DWIDTH/32-1 downto 0 generate
      MEM : RAMB16_S36_S36
        generic map (
          INIT_A       => X"00000000",
          INIT_B       => X"00000000",
          SRVAL_A      => X"00000000",
          SRVAL_B      => X"00000000",
          WRITE_MODE_A => WRITE_MODE,
          WRITE_MODE_B => WRITE_MODE)
        port map (
          DOA   => DOA(32*i+31 downto 32*i),
          DOB   => DOB(32*i+31 downto 32*i),
          DOPA  => open,
          DOPB  => open,
          ADDRA => ADDRA,
          ADDRB => ADDRB,
          CLKA  => CLKA,
          CLKB  => CLKB,
          DIA   => DIA(32*i+31 downto 32*i),
          DIB   => DIB(32*i+31 downto 32*i),
          DIPA  => "0000",
          DIPB  => "0000",
          ENA   => ENA,
          ENB   => ENB,
          SSRA  => '0',
          SSRB  => '0',
          WEA   => WEA,
          WEB   => WEB
        );
    end generate GL;
  end generate AW_09_S32;
 
  AW_10_S18: if AWIDTH=10 and not ok_mod16 generate
    constant dw_mem : positive := ((DWIDTH+17)/18)*18;
    signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
  begin
 
    DI_PAD: if dw_mem>DWIDTH generate
      L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
      L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
    end generate DI_PAD;
    L_DIA(DIA'range) <= DIA;
    L_DIB(DIB'range) <= DIB;
 
    GL: for i in dw_mem/18-1 downto 0 generate
      MEM : RAMB16_S18_S18
        generic map (
          INIT_A       => O"000000",
          INIT_B       => O"000000",
          SRVAL_A      => O"000000",
          SRVAL_B      => O"000000",
          WRITE_MODE_A => WRITE_MODE,
          WRITE_MODE_B => WRITE_MODE)
        port map (
          DOA   => L_DOA(18*i+15 downto 18*i),
          DOB   => L_DOB(18*i+15 downto 18*i),
          DOPA  => L_DOA(18*i+17 downto 18*i+16),
          DOPB  => L_DOB(18*i+17 downto 18*i+16),
          ADDRA => ADDRA,
          ADDRB => ADDRB,
          CLKA  => CLKA,
          CLKB  => CLKB,
          DIA   => L_DIA(18*i+15 downto 18*i),
          DIB   => L_DIB(18*i+15 downto 18*i),
          DIPA  => L_DIA(18*i+17 downto 18*i+16),
          DIPB  => L_DIB(18*i+17 downto 18*i+16),
          ENA   => ENA,
          ENB   => ENB,
          SSRA  => '0',
          SSRB  => '0',
          WEA   => WEA,
          WEB   => WEB
        );
    end generate GL;
 
    DOA <= L_DOA(DOA'range);
    DOB <= L_DOB(DOB'range);
 
  end generate AW_10_S18;
 
  AW_10_S16: if AWIDTH=10 and ok_mod16 generate
    GL: for i in DWIDTH/16-1 downto 0 generate
      MEM : RAMB16_S18_S18
        generic map (
          INIT_A       => X"0000",
          INIT_B       => X"0000",
          SRVAL_A      => X"0000",
          SRVAL_B      => X"0000",
          WRITE_MODE_A => WRITE_MODE,
          WRITE_MODE_B => WRITE_MODE)
        port map (
          DOA   => DOA(16*i+15 downto 16*i),
          DOB   => DOB(16*i+15 downto 16*i),
          DOPA  => open,
          DOPB  => open,
          ADDRA => ADDRA,
          ADDRB => ADDRB,
          CLKA  => CLKA,
          CLKB  => CLKB,
          DIA   => DIA(16*i+15 downto 16*i),
          DIB   => DIB(16*i+15 downto 16*i),
          DIPA  => "00",
          DIPB  => "00",
          ENA   => ENA,
          ENB   => ENB,
          SSRA  => '0',
          SSRB  => '0',
          WEA   => WEA,
          WEB   => WEB
        );
    end generate GL;
  end generate AW_10_S16;
 
  AW_11_S9: if AWIDTH=11  and not ok_mod08 generate
    constant dw_mem : positive := ((DWIDTH+8)/9)*9;
    signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
  begin
 
    DI_PAD: if dw_mem>DWIDTH generate
      L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
      L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
    end generate DI_PAD;
    L_DIA(DIA'range) <= DIA;
    L_DIB(DIB'range) <= DIB;
 
    GL: for i in dw_mem/9-1 downto 0 generate
      MEM : RAMB16_S9_S9
        generic map (
          INIT_A       => O"000",
          INIT_B       => O"000",
          SRVAL_A      => O"000",
          SRVAL_B      => O"000",
          WRITE_MODE_A => WRITE_MODE,
          WRITE_MODE_B => WRITE_MODE)
        port map (
          DOA   => L_DOA(9*i+7 downto 9*i),
          DOB   => L_DOB(9*i+7 downto 9*i),
          DOPA  => L_DOA(9*i+8 downto 9*i+8),
          DOPB  => L_DOB(9*i+8 downto 9*i+8),
          ADDRA => ADDRA,
          ADDRB => ADDRB,
          CLKA  => CLKA,
          CLKB  => CLKB,
          DIA   => L_DIA(9*i+7 downto 9*i),
          DIB   => L_DIB(9*i+7 downto 9*i),
          DIPA  => L_DIA(9*i+8 downto 9*i+8),
          DIPB  => L_DIB(9*i+8 downto 9*i+8),
          ENA   => ENA,
          ENB   => ENB,
          SSRA  => '0',
          SSRB  => '0',
          WEA   => WEA,
          WEB   => WEB
        );
    end generate GL;
 
    DOA <= L_DOA(DOA'range);
    DOB <= L_DOB(DOB'range);
 
  end generate AW_11_S9;
 
  AW_11_S8: if AWIDTH=11 and ok_mod08 generate
    GL: for i in DWIDTH/8-1 downto 0 generate
      MEM : RAMB16_S9_S9
        generic map (
          INIT_A       => X"00",
          INIT_B       => X"00",
          SRVAL_A      => X"00",
          SRVAL_B      => X"00",
          WRITE_MODE_A => WRITE_MODE,
          WRITE_MODE_B => WRITE_MODE)
        port map (
          DOA   => DOA(8*i+7 downto 8*i),
          DOB   => DOB(8*i+7 downto 8*i),
          DOPA  => open,
          DOPB  => open,
          ADDRA => ADDRA,
          ADDRB => ADDRB,
          CLKA  => CLKA,
          CLKB  => CLKB,
          DIA   => DIA(8*i+7 downto 8*i),
          DIB   => DIB(8*i+7 downto 8*i),
          DIPA  => "0",
          DIPB  => "0",
          ENA   => ENA,
          ENB   => ENB,
          SSRA  => '0',
          SSRB  => '0',
          WEA   => WEA,
          WEB   => WEB
        );
    end generate GL;
  end generate AW_11_S8;
 
  AW_12_S4: if AWIDTH = 12 generate
    constant dw_mem : positive := ((DWIDTH+3)/4)*4;
    signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
  begin
 
    DI_PAD: if dw_mem>DWIDTH generate
      L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
      L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
    end generate DI_PAD;
    L_DIA(DIA'range) <= DIA;
    L_DIB(DIB'range) <= DIB;
 
    GL: for i in dw_mem/4-1 downto 0 generate
      MEM : RAMB16_S4_S4
        generic map (
          INIT_A       => X"0",
          INIT_B       => X"0",
          SRVAL_A      => X"0",
          SRVAL_B      => X"0",
          WRITE_MODE_A => WRITE_MODE,
          WRITE_MODE_B => WRITE_MODE)
        port map (
          DOA   => L_DOA(4*i+3 downto 4*i),
          DOB   => L_DOB(4*i+3 downto 4*i),
          ADDRA => ADDRA,
          ADDRB => ADDRB,
          CLKA  => CLKA,
          CLKB  => CLKB,
          DIA   => L_DIA(4*i+3 downto 4*i),
          DIB   => L_DIB(4*i+3 downto 4*i),
          ENA   => ENA,
          ENB   => ENB,
          SSRA  => '0',
          SSRB  => '0',
          WEA   => WEA,
          WEB   => WEB
        );
    end generate GL;
 
    DOA <= L_DOA(DOA'range);
    DOB <= L_DOB(DOB'range);
 
  end generate AW_12_S4;
 
  AW_13_S2: if AWIDTH = 13 generate
    constant dw_mem : positive := ((DWIDTH+1)/2)*2;
    signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
    signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
  begin
 
    DI_PAD: if dw_mem>DWIDTH generate
      L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
      L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
    end generate DI_PAD;
    L_DIA(DIA'range) <= DIA;
    L_DIB(DIB'range) <= DIB;
 
    GL: for i in dw_mem/2-1 downto 0 generate
      MEM : RAMB16_S2_S2
        generic map (
          INIT_A       => "00",
          INIT_B       => "00",
          SRVAL_A      => "00",
          SRVAL_B      => "00",
          WRITE_MODE_A => WRITE_MODE,
          WRITE_MODE_B => WRITE_MODE)
        port map (
          DOA   => L_DOA(2*i+1 downto 2*i),
          DOB   => L_DOB(2*i+1 downto 2*i),
          ADDRA => ADDRA,
          ADDRB => ADDRB,
          CLKA  => CLKA,
          CLKB  => CLKB,
          DIA   => L_DIA(2*i+1 downto 2*i),
          DIB   => L_DIB(2*i+1 downto 2*i),
          ENA   => ENA,
          ENB   => ENB,
          SSRA  => '0',
          SSRB  => '0',
          WEA   => WEA,
          WEB   => WEB
        );
    end generate GL;
 
    DOA <= L_DOA(DOA'range);
    DOB <= L_DOB(DOB'range);
 
  end generate AW_13_S2;
 
  AW_14_S1: if AWIDTH = 14 generate
    GL: for i in DWIDTH-1 downto 0 generate
      MEM : RAMB16_S1_S1
        generic map (
          INIT_A       => "0",
          INIT_B       => "0",
          SRVAL_A      => "0",
          SRVAL_B      => "0",
          WRITE_MODE_A => WRITE_MODE,
          WRITE_MODE_B => WRITE_MODE)
        port map (
          DOA   => DOA(i downto i),
          DOB   => DOB(i downto i),
          ADDRA => ADDRA,
          ADDRB => ADDRB,
          CLKA  => CLKA,
          CLKB  => CLKB,
          DIA   => DIA(i downto i),
          DIB   => DIB(i downto i),
          ENA   => ENA,
          ENB   => ENB,
          SSRA  => '0',
          SSRB  => '0',
          WEA   => WEA,
          WEB   => WEB
        );
    end generate GL;
  end generate AW_14_S1;
 
 
end syn;
 
-- Note: in XST 8.2 the defaults for INIT_(A|B) and SRVAL_(A|B) are
--       nonsense:  INIT_A : bit_vector := X"000";
--       This is a 12 bit value, while a 9 bit one is needed. Thus the
--       explicit definition above.

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[/] [w11/] [tags/] [w11a_V0.7/] [rtl/] [vlib/] [memlib/] [ram_2swsr_xfirst_gen_unisim.vhd] - Blame information for rev 40

Line No.	Rev	Author	Line
1	31	wfjm	`-- $Id: ram_2swsr_xfirst_gen_unisim.vhd 686 2015-06-04 21:08:08Z mueller $`
2			`--`
3			`-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>`
4			`--`
5			`-- This program is free software; you may redistribute and/or modify it under`
6			`-- the terms of the GNU General Public License as published by the Free`
7			`-- Software Foundation, either version 2, or at your option any later version.`
8			`--`
9			`-- This program is distributed in the hope that it will be useful, but`
10			`-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY`
11			`-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
12			`-- for complete details.`
13			`--`
14			`------------------------------------------------------------------------------`
15			`-- Module Name: ram_2swsr_xfirst_gen_unisim - syn`
16			`-- Description: Dual-Port RAM with with two synchronous read/write ports`
17			`-- Direct instantiation of Xilinx UNISIM primitives`
18			`--`
19			`-- Dependencies: -`
20			`-- Test bench: -`
21			`-- Target Devices: Spartan-3, Virtex-2,-4`
22			`-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31`
23			`-- Revision History:`
24			`-- Date Rev Version Comment`
25			`-- 2011-08-14 406 1.0.2 cleaner code for L_DI(A\|B) initialization`
26			`-- 2008-04-13 135 1.0.1 fix range error for AW_14_S1`
27			`-- 2008-03-08 123 1.0 Initial version (merged from _rfirst/_wfirst)`
28			`------------------------------------------------------------------------------`
29
30			`library ieee;`
31			`use ieee.std_logic_1164.all;`
32
33			`library unisim;`
34			`use unisim.vcomponents.ALL;`
35
36			`use work.slvtypes.all;`
37
38			`entity ram_2swsr_xfirst_gen_unisim is -- RAM, 2 sync r/w ports`
39			`generic (`
40			`AWIDTH : positive := 11; -- address port width`
41			`DWIDTH : positive := 9; -- data port width`
42			`WRITE_MODE : string := "READ_FIRST"); -- write mode: (READ\|WRITE)_FIRST`
43			`port(`
44			`CLKA : in slbit; -- clock port A`
45			`CLKB : in slbit; -- clock port B`
46			`ENA : in slbit; -- enable port A`
47			`ENB : in slbit; -- enable port B`
48			`WEA : in slbit; -- write enable port A`
49			`WEB : in slbit; -- write enable port B`
50			`ADDRA : in slv(AWIDTH-1 downto 0); -- address port A`
51			`ADDRB : in slv(AWIDTH-1 downto 0); -- address port B`
52			`DIA : in slv(DWIDTH-1 downto 0); -- data in port A`
53			`DIB : in slv(DWIDTH-1 downto 0); -- data in port B`
54			`DOA : out slv(DWIDTH-1 downto 0); -- data out port A`
55			`DOB : out slv(DWIDTH-1 downto 0) -- data out port B`
56			`);`
57			`end ram_2swsr_xfirst_gen_unisim;`
58
59
60			`architecture syn of ram_2swsr_xfirst_gen_unisim is`
61
62			`constant ok_mod32 : boolean := (DWIDTH mod 32)=0 and`
63			`((DWIDTH+35)/36)=((DWIDTH+31)/32);`
64			`constant ok_mod16 : boolean := (DWIDTH mod 16)=0 and`
65			`((DWIDTH+17)/18)=((DWIDTH+16)/16);`
66			`constant ok_mod08 : boolean := (DWIDTH mod 32)=0 and`
67			`((DWIDTH+8)/9)=((DWIDTH+7)/8);`
68
69			`begin`
70
71			`assert AWIDTH>=9 and AWIDTH<=14`
72			`report "assert(AWIDTH>=9 and AWIDTH<=14): unsupported BRAM from factor"`
73			`severity failure;`
74
75			`AW_09_S36: if AWIDTH=9 and not ok_mod32 generate`
76			`constant dw_mem : positive := ((DWIDTH+35)/36)*36;`
77			`signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');`
78			`signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');`
79			`signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');`
80			`signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');`
81			`begin`
82
83			`DI_PAD: if dw_mem>DWIDTH generate`
84			`L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');`
85			`L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');`
86			`end generate DI_PAD;`
87			`L_DIA(DIA'range) <= DIA;`
88			`L_DIB(DIB'range) <= DIB;`
89
90			`GL: for i in dw_mem/36-1 downto 0 generate`
91			`MEM : RAMB16_S36_S36`
92			`generic map (`
93			`INIT_A => O"000000000000",`
94			`INIT_B => O"000000000000",`
95			`SRVAL_A => O"000000000000",`
96			`SRVAL_B => O"000000000000",`
97			`WRITE_MODE_A => WRITE_MODE,`
98			`WRITE_MODE_B => WRITE_MODE)`
99			`port map (`
100			`DOA => L_DOA(36i+31 downto 36i),`
101			`DOB => L_DOB(36i+31 downto 36i),`
102			`DOPA => L_DOA(36i+35 downto 36i+32),`
103			`DOPB => L_DOB(36i+35 downto 36i+32),`
104			`ADDRA => ADDRA,`
105			`ADDRB => ADDRB,`
106			`CLKA => CLKA,`
107			`CLKB => CLKB,`
108			`DIA => L_DIA(36i+31 downto 36i),`
109			`DIB => L_DIB(36i+31 downto 36i),`
110			`DIPA => L_DIA(36i+35 downto 36i+32),`
111			`DIPB => L_DIB(36i+35 downto 36i+32),`
112			`ENA => ENA,`
113			`ENB => ENB,`
114			`SSRA => '0',`
115			`SSRB => '0',`
116			`WEA => WEA,`
117			`WEB => WEB`
118			`);`
119			`end generate GL;`
120
121			`DOA <= L_DOA(DOA'range);`
122			`DOB <= L_DOB(DOB'range);`
123
124			`end generate AW_09_S36;`
125
126			`AW_09_S32: if AWIDTH=9 and ok_mod32 generate`
127			`GL: for i in DWIDTH/32-1 downto 0 generate`
128			`MEM : RAMB16_S36_S36`
129			`generic map (`
130			`INIT_A => X"00000000",`
131			`INIT_B => X"00000000",`
132			`SRVAL_A => X"00000000",`
133			`SRVAL_B => X"00000000",`
134			`WRITE_MODE_A => WRITE_MODE,`
135			`WRITE_MODE_B => WRITE_MODE)`
136			`port map (`
137			`DOA => DOA(32i+31 downto 32i),`
138			`DOB => DOB(32i+31 downto 32i),`
139			`DOPA => open,`
140			`DOPB => open,`
141			`ADDRA => ADDRA,`
142			`ADDRB => ADDRB,`
143			`CLKA => CLKA,`
144			`CLKB => CLKB,`
145			`DIA => DIA(32i+31 downto 32i),`
146			`DIB => DIB(32i+31 downto 32i),`
147			`DIPA => "0000",`
148			`DIPB => "0000",`
149			`ENA => ENA,`
150			`ENB => ENB,`
151			`SSRA => '0',`
152			`SSRB => '0',`
153			`WEA => WEA,`
154			`WEB => WEB`
155			`);`
156			`end generate GL;`
157			`end generate AW_09_S32;`
158
159			`AW_10_S18: if AWIDTH=10 and not ok_mod16 generate`
160			`constant dw_mem : positive := ((DWIDTH+17)/18)*18;`
161			`signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');`
162			`signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');`
163			`signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');`
164			`signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');`
165			`begin`
166
167			`DI_PAD: if dw_mem>DWIDTH generate`
168			`L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');`
169			`L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');`
170			`end generate DI_PAD;`
171			`L_DIA(DIA'range) <= DIA;`
172			`L_DIB(DIB'range) <= DIB;`
173
174			`GL: for i in dw_mem/18-1 downto 0 generate`
175			`MEM : RAMB16_S18_S18`
176			`generic map (`
177			`INIT_A => O"000000",`
178			`INIT_B => O"000000",`
179			`SRVAL_A => O"000000",`
180			`SRVAL_B => O"000000",`
181			`WRITE_MODE_A => WRITE_MODE,`
182			`WRITE_MODE_B => WRITE_MODE)`
183			`port map (`
184			`DOA => L_DOA(18i+15 downto 18i),`
185			`DOB => L_DOB(18i+15 downto 18i),`
186			`DOPA => L_DOA(18i+17 downto 18i+16),`
187			`DOPB => L_DOB(18i+17 downto 18i+16),`
188			`ADDRA => ADDRA,`
189			`ADDRB => ADDRB,`
190			`CLKA => CLKA,`
191			`CLKB => CLKB,`
192			`DIA => L_DIA(18i+15 downto 18i),`
193			`DIB => L_DIB(18i+15 downto 18i),`
194			`DIPA => L_DIA(18i+17 downto 18i+16),`
195			`DIPB => L_DIB(18i+17 downto 18i+16),`
196			`ENA => ENA,`
197			`ENB => ENB,`
198			`SSRA => '0',`
199			`SSRB => '0',`
200			`WEA => WEA,`
201			`WEB => WEB`
202			`);`
203			`end generate GL;`
204
205			`DOA <= L_DOA(DOA'range);`
206			`DOB <= L_DOB(DOB'range);`
207
208			`end generate AW_10_S18;`
209
210			`AW_10_S16: if AWIDTH=10 and ok_mod16 generate`
211			`GL: for i in DWIDTH/16-1 downto 0 generate`
212			`MEM : RAMB16_S18_S18`
213			`generic map (`
214			`INIT_A => X"0000",`
215			`INIT_B => X"0000",`
216			`SRVAL_A => X"0000",`
217			`SRVAL_B => X"0000",`
218			`WRITE_MODE_A => WRITE_MODE,`
219			`WRITE_MODE_B => WRITE_MODE)`
220			`port map (`
221			`DOA => DOA(16i+15 downto 16i),`
222			`DOB => DOB(16i+15 downto 16i),`
223			`DOPA => open,`
224			`DOPB => open,`
225			`ADDRA => ADDRA,`
226			`ADDRB => ADDRB,`
227			`CLKA => CLKA,`
228			`CLKB => CLKB,`
229			`DIA => DIA(16i+15 downto 16i),`
230			`DIB => DIB(16i+15 downto 16i),`
231			`DIPA => "00",`
232			`DIPB => "00",`
233			`ENA => ENA,`
234			`ENB => ENB,`
235			`SSRA => '0',`
236			`SSRB => '0',`
237			`WEA => WEA,`
238			`WEB => WEB`
239			`);`
240			`end generate GL;`
241			`end generate AW_10_S16;`
242
243			`AW_11_S9: if AWIDTH=11 and not ok_mod08 generate`
244			`constant dw_mem : positive := ((DWIDTH+8)/9)*9;`
245			`signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');`
246			`signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');`
247			`signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');`
248			`signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');`
249			`begin`
250
251			`DI_PAD: if dw_mem>DWIDTH generate`
252			`L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');`
253			`L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');`
254			`end generate DI_PAD;`
255			`L_DIA(DIA'range) <= DIA;`
256			`L_DIB(DIB'range) <= DIB;`
257
258			`GL: for i in dw_mem/9-1 downto 0 generate`
259			`MEM : RAMB16_S9_S9`
260			`generic map (`
261			`INIT_A => O"000",`
262			`INIT_B => O"000",`
263			`SRVAL_A => O"000",`
264			`SRVAL_B => O"000",`
265			`WRITE_MODE_A => WRITE_MODE,`
266			`WRITE_MODE_B => WRITE_MODE)`
267			`port map (`
268			`DOA => L_DOA(9i+7 downto 9i),`
269			`DOB => L_DOB(9i+7 downto 9i),`
270			`DOPA => L_DOA(9i+8 downto 9i+8),`
271			`DOPB => L_DOB(9i+8 downto 9i+8),`
272			`ADDRA => ADDRA,`
273			`ADDRB => ADDRB,`
274			`CLKA => CLKA,`
275			`CLKB => CLKB,`
276			`DIA => L_DIA(9i+7 downto 9i),`
277			`DIB => L_DIB(9i+7 downto 9i),`
278			`DIPA => L_DIA(9i+8 downto 9i+8),`
279			`DIPB => L_DIB(9i+8 downto 9i+8),`
280			`ENA => ENA,`
281			`ENB => ENB,`
282			`SSRA => '0',`
283			`SSRB => '0',`
284			`WEA => WEA,`
285			`WEB => WEB`
286			`);`
287			`end generate GL;`
288
289			`DOA <= L_DOA(DOA'range);`
290			`DOB <= L_DOB(DOB'range);`
291
292			`end generate AW_11_S9;`
293
294			`AW_11_S8: if AWIDTH=11 and ok_mod08 generate`
295			`GL: for i in DWIDTH/8-1 downto 0 generate`
296			`MEM : RAMB16_S9_S9`
297			`generic map (`
298			`INIT_A => X"00",`
299			`INIT_B => X"00",`
300			`SRVAL_A => X"00",`
301			`SRVAL_B => X"00",`
302			`WRITE_MODE_A => WRITE_MODE,`
303			`WRITE_MODE_B => WRITE_MODE)`
304			`port map (`
305			`DOA => DOA(8i+7 downto 8i),`
306			`DOB => DOB(8i+7 downto 8i),`
307			`DOPA => open,`
308			`DOPB => open,`
309			`ADDRA => ADDRA,`
310			`ADDRB => ADDRB,`
311			`CLKA => CLKA,`
312			`CLKB => CLKB,`
313			`DIA => DIA(8i+7 downto 8i),`
314			`DIB => DIB(8i+7 downto 8i),`
315			`DIPA => "0",`
316			`DIPB => "0",`
317			`ENA => ENA,`
318			`ENB => ENB,`
319			`SSRA => '0',`
320			`SSRB => '0',`
321			`WEA => WEA,`
322			`WEB => WEB`
323			`);`
324			`end generate GL;`
325			`end generate AW_11_S8;`
326
327			`AW_12_S4: if AWIDTH = 12 generate`
328			`constant dw_mem : positive := ((DWIDTH+3)/4)*4;`
329			`signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');`
330			`signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');`
331			`signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');`
332			`signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');`
333			`begin`
334
335			`DI_PAD: if dw_mem>DWIDTH generate`
336			`L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');`
337			`L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');`
338			`end generate DI_PAD;`
339			`L_DIA(DIA'range) <= DIA;`
340			`L_DIB(DIB'range) <= DIB;`
341
342			`GL: for i in dw_mem/4-1 downto 0 generate`
343			`MEM : RAMB16_S4_S4`
344			`generic map (`
345			`INIT_A => X"0",`
346			`INIT_B => X"0",`
347			`SRVAL_A => X"0",`
348			`SRVAL_B => X"0",`
349			`WRITE_MODE_A => WRITE_MODE,`
350			`WRITE_MODE_B => WRITE_MODE)`
351			`port map (`
352			`DOA => L_DOA(4i+3 downto 4i),`
353			`DOB => L_DOB(4i+3 downto 4i),`
354			`ADDRA => ADDRA,`
355			`ADDRB => ADDRB,`
356			`CLKA => CLKA,`
357			`CLKB => CLKB,`
358			`DIA => L_DIA(4i+3 downto 4i),`
359			`DIB => L_DIB(4i+3 downto 4i),`
360			`ENA => ENA,`
361			`ENB => ENB,`
362			`SSRA => '0',`
363			`SSRB => '0',`
364			`WEA => WEA,`
365			`WEB => WEB`
366			`);`
367			`end generate GL;`
368
369			`DOA <= L_DOA(DOA'range);`
370			`DOB <= L_DOB(DOB'range);`
371
372			`end generate AW_12_S4;`
373
374			`AW_13_S2: if AWIDTH = 13 generate`
375			`constant dw_mem : positive := ((DWIDTH+1)/2)*2;`
376			`signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');`
377			`signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');`
378			`signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');`
379			`signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');`
380			`begin`
381
382			`DI_PAD: if dw_mem>DWIDTH generate`
383			`L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');`
384			`L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');`
385			`end generate DI_PAD;`
386			`L_DIA(DIA'range) <= DIA;`
387			`L_DIB(DIB'range) <= DIB;`
388
389			`GL: for i in dw_mem/2-1 downto 0 generate`
390			`MEM : RAMB16_S2_S2`
391			`generic map (`
392			`INIT_A => "00",`
393			`INIT_B => "00",`
394			`SRVAL_A => "00",`
395			`SRVAL_B => "00",`
396			`WRITE_MODE_A => WRITE_MODE,`
397			`WRITE_MODE_B => WRITE_MODE)`
398			`port map (`
399			`DOA => L_DOA(2i+1 downto 2i),`
400			`DOB => L_DOB(2i+1 downto 2i),`
401			`ADDRA => ADDRA,`
402			`ADDRB => ADDRB,`
403			`CLKA => CLKA,`
404			`CLKB => CLKB,`
405			`DIA => L_DIA(2i+1 downto 2i),`
406			`DIB => L_DIB(2i+1 downto 2i),`
407			`ENA => ENA,`
408			`ENB => ENB,`
409			`SSRA => '0',`
410			`SSRB => '0',`
411			`WEA => WEA,`
412			`WEB => WEB`
413			`);`
414			`end generate GL;`
415
416			`DOA <= L_DOA(DOA'range);`
417			`DOB <= L_DOB(DOB'range);`
418
419			`end generate AW_13_S2;`
420
421			`AW_14_S1: if AWIDTH = 14 generate`
422			`GL: for i in DWIDTH-1 downto 0 generate`
423			`MEM : RAMB16_S1_S1`
424			`generic map (`
425			`INIT_A => "0",`
426			`INIT_B => "0",`
427			`SRVAL_A => "0",`
428			`SRVAL_B => "0",`
429			`WRITE_MODE_A => WRITE_MODE,`
430			`WRITE_MODE_B => WRITE_MODE)`
431			`port map (`
432			`DOA => DOA(i downto i),`
433			`DOB => DOB(i downto i),`
434			`ADDRA => ADDRA,`
435			`ADDRB => ADDRB,`
436			`CLKA => CLKA,`
437			`CLKB => CLKB,`
438			`DIA => DIA(i downto i),`
439			`DIB => DIB(i downto i),`
440			`ENA => ENA,`
441			`ENB => ENB,`
442			`SSRA => '0',`
443			`SSRB => '0',`
444			`WEA => WEA,`
445			`WEB => WEB`
446			`);`
447			`end generate GL;`
448			`end generate AW_14_S1;`
449
450
451			`end syn;`
452
453			`-- Note: in XST 8.2 the defaults for INIT_(A\|B) and SRVAL_(A\|B) are`
454			`-- nonsense: INIT_A : bit_vector := X"000";`
455			`-- This is a 12 bit value, while a 9 bit one is needed. Thus the`
456			`-- explicit definition above.`