1 |
30 |
wfjm |
-- $Id: pdp11.vhd 677 2015-05-09 21:52:32Z mueller $
|
2 |
2 |
wfjm |
--
|
3 |
30 |
wfjm |
-- Copyright 2006-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
4 |
2 |
wfjm |
--
|
5 |
|
|
-- This program is free software; you may redistribute and/or modify it under
|
6 |
|
|
-- the terms of the GNU General Public License as published by the Free
|
7 |
|
|
-- Software Foundation, either version 2, or at your option any later version.
|
8 |
|
|
--
|
9 |
|
|
-- This program is distributed in the hope that it will be useful, but
|
10 |
|
|
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
|
11 |
|
|
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
12 |
|
|
-- for complete details.
|
13 |
|
|
--
|
14 |
|
|
------------------------------------------------------------------------------
|
15 |
|
|
-- Package Name: pdp11
|
16 |
|
|
-- Description: Definitions for pdp11 components
|
17 |
|
|
--
|
18 |
|
|
-- Dependencies: -
|
19 |
29 |
wfjm |
-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
|
20 |
25 |
wfjm |
--
|
21 |
2 |
wfjm |
-- Revision History:
|
22 |
|
|
-- Date Rev Version Comment
|
23 |
30 |
wfjm |
-- 2015-05-09 677 1.6 start/stop/suspend overhaul; reset overhaul
|
24 |
|
|
-- 2015-05-01 672 1.5.5 add pdp11_sys70, sys_hio70
|
25 |
|
|
-- 2015-04-30 670 1.5.4 rename pdp11_sys70 -> pdp11_reg70
|
26 |
29 |
wfjm |
-- 2015-02-20 649 1.5.3 add pdp11_statleds
|
27 |
|
|
-- 2015-02-08 644 1.5.2 add pdp11_bram_memctl
|
28 |
27 |
wfjm |
-- 2014-08-28 588 1.5.1 use new rlink v4 iface and 4 bit STAT
|
29 |
|
|
-- 2014-08-15 583 1.5 rb_mreq addr now 16 bit
|
30 |
|
|
-- 2014-08-10: 581 1.4.10 add c_cc_f_* field defs for condition code array
|
31 |
25 |
wfjm |
-- 2014-07-12 569 1.4.9 dpath_stat_type: merge div_zero+div_ovfl to div_quit
|
32 |
|
|
-- dpath_cntl_type: add munit_s_div_sr
|
33 |
13 |
wfjm |
-- 2011-11-18 427 1.4.8 now numeric_std clean
|
34 |
9 |
wfjm |
-- 2010-12-30 351 1.4.7 rename pdp11_core_rri->pdp11_core_rbus; use rblib
|
35 |
8 |
wfjm |
-- 2010-10-23 335 1.4.6 rename RRI_LAM->RB_LAM;
|
36 |
|
|
-- 2010-10-16 332 1.4.5 renames of pdp11_du_drv port names
|
37 |
|
|
-- 2010-09-18 330 1.4.4 rename (adlm)box->(oalm)unit
|
38 |
2 |
wfjm |
-- 2010-06-20 308 1.4.3 add c_ibrb_ibf_ def's
|
39 |
|
|
-- 2010-06-20 307 1.4.2 rename cpacc to cacc in vm_cntl_type, mmu_cntl_type
|
40 |
|
|
-- 2010-06-18 306 1.4.1 add racc, be to cp_addr_type; rm pdp11_ibdr_rri
|
41 |
|
|
-- 2010-06-13 305 1.4 add rnum to cp_cntl_type, cprnum to cpustat_type;
|
42 |
|
|
-- reassign cp command codes and rename: c_cp_func_...
|
43 |
|
|
-- -> c_cpfunc_...; remove cpaddr_(lal|lah|inc) from
|
44 |
|
|
-- dpath_cntl_type; add cpdout_we to dpath_cntl_type;
|
45 |
|
|
-- reassign rbus adresses and rename: c_rb_addr_...
|
46 |
|
|
-- -> c_rbaddr_...; rename rbus fields: c_rb_statf_...
|
47 |
|
|
-- -> c_stat_rbf_...
|
48 |
|
|
-- 2010-06-12 304 1.3.3 add cpuwait to cp_stat_type and cpustat_type
|
49 |
|
|
-- 2010-06-11 303 1.3.2 use IB_MREQ.racc instead of RRI_REQ
|
50 |
|
|
-- 2010-05-02 287 1.3.1 rename RP_STAT->RB_STAT
|
51 |
|
|
-- 2010-05-01 285 1.3 port to rri V2 interface; drop pdp11_rri_2rp;
|
52 |
|
|
-- rename c_rp_addr_* -> c_rb_addr_*
|
53 |
|
|
-- 2010-03-21 270 1.2.6 add pdp11_du_drv
|
54 |
|
|
-- 2009-05-30 220 1.2.5 final removal of snoopers (were already commented)
|
55 |
|
|
-- 2009-05-10 214 1.2.4 add ENA (trace enable) for _tmu; add _pdp11_tmu_sb
|
56 |
|
|
-- 2009-05-09 213 1.2.3 BUGFIX: default for inst_compl now '0'
|
57 |
|
|
-- 2008-12-14 177 1.2.2 add gpr_* fields to DM_STAT_DP
|
58 |
|
|
-- 2008-11-30 174 1.2.1 BUGFIX: add updt_dstadsrc;
|
59 |
|
|
-- 2008-08-22 161 1.2 move slvnn_m subtypes to slvtypes;
|
60 |
|
|
-- move (and rename) intbus defs to iblib package;
|
61 |
|
|
-- move intbus devices to ibdlib package;
|
62 |
|
|
-- rename ubf_ --> ibf_;
|
63 |
|
|
-- 2008-05-09 144 1.1.17 use EI_ACK with _kw11l, _dl11
|
64 |
|
|
-- 2008-05-03 143 1.1.16 rename _cpursta->_cpurust
|
65 |
|
|
-- 2008-04-27 140 1.1.15 add c_cpursta_xxx defs; cpufail->cpursta in cp_stat
|
66 |
|
|
-- 2008-04-25 138 1.1.14 add BRESET port to _mmu, _vmbox, use in _irq
|
67 |
|
|
-- 2008-04-19 137 1.1.13 add _tmu,_sys70 entity, dm_stat_** types and ports
|
68 |
|
|
-- 2008-04-18 136 1.1.12 ibdr_sdreg: use RESET; ibdr_minisys: add RESET
|
69 |
|
|
-- 2008-03-02 121 1.1.11 remove snoopers; add waitsusp in cpustat_type
|
70 |
|
|
-- 2008-02-24 119 1.1.10 add lah,rps,wps commands, cp_addr_type.
|
71 |
|
|
-- _vmbox,_mmu interface changed
|
72 |
|
|
-- 2008-02-17 117 1.1.9 add em_(mreq|sres)_type, pdp11_cache, pdp11_bram
|
73 |
|
|
-- 2008-01-27 115 1.1.8 add pdp11_ubmap, pdp11_mem70
|
74 |
|
|
-- 2008-01-26 114 1.1.7 add c_rp_addr_ibr(b) defs (for ibr addresses)
|
75 |
|
|
-- 2008-01-20 113 1.1.6 _core_rri: use RRI_LAM; _minisys: RRI_LAM vector
|
76 |
|
|
-- 2008-01-20 112 1.1.5 added ibdr_minisys; _ibdr_rri
|
77 |
|
|
-- 2008-01-06 111 1.1.4 rename ibdr_kw11l->ibd_kw11l; add ibdr_(dl11|rk11)
|
78 |
|
|
-- mod pdp11_intmap;
|
79 |
|
|
-- 2008-01-05 110 1.1.3 delete _mmu_regfile; rename _mmu_regs->_mmu_sadr
|
80 |
|
|
-- rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
|
81 |
|
|
-- add ibdr_kw11l.
|
82 |
|
|
-- 2008-01-01 109 1.1.2 _vmbox w/ IB_SRES_(CPU|EXT); remove vm_regs_type
|
83 |
|
|
-- 2007-12-30 108 1.1.1 add ibdr_sdreg, ubf_byte[01]
|
84 |
|
|
-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now; remove DMA port
|
85 |
|
|
-- 2007-08-16 74 1.0.6 add AP_LAM interface to pdp11_core_rri
|
86 |
|
|
-- 2007-08-12 73 1.0.5 add c_rp_addr_xxx and c_rp_statf_xxx def's
|
87 |
|
|
-- 2007-08-10 72 1.0.4 added c_cp_func_xxx constant def's for commands
|
88 |
|
|
-- 2007-07-15 66 1.0.3 rename pdp11_top -> pdp11_core
|
89 |
|
|
-- 2007-07-02 63 1.0.2 reordered ports on pdp11_top (by function, not i/o)
|
90 |
|
|
-- 2007-06-14 56 1.0.1 Use slvtypes.all
|
91 |
|
|
-- 2007-05-12 26 1.0 Initial version
|
92 |
|
|
------------------------------------------------------------------------------
|
93 |
|
|
|
94 |
|
|
library ieee;
|
95 |
|
|
use ieee.std_logic_1164.all;
|
96 |
13 |
wfjm |
use ieee.numeric_std.all;
|
97 |
2 |
wfjm |
|
98 |
|
|
use work.slvtypes.all;
|
99 |
|
|
use work.iblib.all;
|
100 |
9 |
wfjm |
use work.rblib.all;
|
101 |
2 |
wfjm |
|
102 |
|
|
package pdp11 is
|
103 |
|
|
|
104 |
|
|
type psw_type is record -- processor status
|
105 |
|
|
cmode : slv2; -- current mode
|
106 |
|
|
pmode : slv2; -- previous mode
|
107 |
|
|
rset : slbit; -- register set
|
108 |
|
|
pri : slv3; -- processor priority
|
109 |
|
|
tflag : slbit; -- trace flag
|
110 |
|
|
cc : slv4; -- condition codes (NZVC).
|
111 |
|
|
end record psw_type;
|
112 |
|
|
|
113 |
27 |
wfjm |
constant c_cc_f_n: integer := 3; -- condition code: n
|
114 |
|
|
constant c_cc_f_z: integer := 2; -- condition code: z
|
115 |
|
|
constant c_cc_f_v: integer := 1; -- condition code: v
|
116 |
|
|
constant c_cc_f_c: integer := 0; -- condition code: c
|
117 |
|
|
|
118 |
2 |
wfjm |
constant psw_init : psw_type := (
|
119 |
|
|
"00","00", -- cmode, pmode (=kernel)
|
120 |
|
|
'0',"111",'0', -- rset, pri (=7), tflag
|
121 |
|
|
"0000" -- cc NZVC=0
|
122 |
|
|
);
|
123 |
|
|
|
124 |
|
|
constant c_psw_kmode : slv2 := "00"; -- processor mode: kernel
|
125 |
|
|
constant c_psw_smode : slv2 := "01"; -- processor mode: supervisor
|
126 |
|
|
constant c_psw_umode : slv2 := "11"; -- processor mode: user
|
127 |
|
|
|
128 |
|
|
subtype psw_ibf_cmode is integer range 15 downto 14;
|
129 |
|
|
subtype psw_ibf_pmode is integer range 13 downto 12;
|
130 |
|
|
constant psw_ibf_rset: integer := 11;
|
131 |
|
|
subtype psw_ibf_pri is integer range 7 downto 5;
|
132 |
|
|
constant psw_ibf_tflag: integer := 4;
|
133 |
|
|
subtype psw_ibf_cc is integer range 3 downto 0;
|
134 |
|
|
|
135 |
|
|
type sarsdr_type is record -- combined SAR/SDR MMU status
|
136 |
|
|
saf : slv16; -- segment address field
|
137 |
|
|
slf : slv7; -- segment length field
|
138 |
|
|
ed : slbit; -- expansion direction
|
139 |
|
|
acf : slv3; -- access control field
|
140 |
|
|
end record sarsdr_type;
|
141 |
|
|
|
142 |
|
|
constant sarsdr_init : sarsdr_type := (
|
143 |
|
|
(others=>'0'), -- saf
|
144 |
|
|
"0000000",'0',"000" -- slf, ed, acf
|
145 |
|
|
);
|
146 |
|
|
|
147 |
|
|
type dpath_cntl_type is record -- data path control
|
148 |
|
|
gpr_asrc : slv3; -- src register address
|
149 |
|
|
gpr_adst : slv3; -- dst register address
|
150 |
|
|
gpr_mode : slv2; -- psw mode for gpr access
|
151 |
|
|
gpr_rset : slbit; -- register set
|
152 |
|
|
gpr_we : slbit; -- gpr write enable
|
153 |
|
|
gpr_bytop : slbit; -- gpr high byte enable
|
154 |
|
|
gpr_pcinc : slbit; -- pc increment enable
|
155 |
|
|
psr_ccwe : slbit; -- enable update cc
|
156 |
|
|
psr_we: slbit; -- write enable psw (from DIN)
|
157 |
|
|
psr_func : slv3; -- write function psw (from DIN)
|
158 |
|
|
dsrc_sel : slbit; -- src data register source select
|
159 |
|
|
dsrc_we : slbit; -- src data register write enable
|
160 |
|
|
ddst_sel : slbit; -- dst data register source select
|
161 |
|
|
ddst_we : slbit; -- dst data register write enable
|
162 |
|
|
dtmp_sel : slv2; -- tmp data register source select
|
163 |
|
|
dtmp_we : slbit; -- tmp data register write enable
|
164 |
8 |
wfjm |
ounit_asel : slv2; -- ounit a port selector
|
165 |
|
|
ounit_azero : slbit; -- ounit a port force zero
|
166 |
|
|
ounit_const : slv9; -- ounit b port const
|
167 |
|
|
ounit_bsel : slv2; -- ounit b port selector
|
168 |
|
|
ounit_opsub : slbit; -- ounit operation
|
169 |
|
|
aunit_srcmod : slv2; -- aunit src port modifier
|
170 |
|
|
aunit_dstmod : slv2; -- aunit dst port modifier
|
171 |
|
|
aunit_cimod : slv2; -- aunit ci port modifier
|
172 |
|
|
aunit_cc1op : slbit; -- aunit use cc modes (1 op instruction)
|
173 |
|
|
aunit_ccmode : slv3; -- aunit cc port mode
|
174 |
|
|
aunit_bytop : slbit; -- aunit byte operation
|
175 |
|
|
lunit_func : slv4; -- lunit function
|
176 |
|
|
lunit_bytop : slbit; -- lunit byte operation
|
177 |
|
|
munit_func : slv2; -- munit function
|
178 |
|
|
munit_s_div : slbit; -- munit s_opg_div state
|
179 |
|
|
munit_s_div_cn : slbit; -- munit s_opg_div_cn state
|
180 |
|
|
munit_s_div_cr : slbit; -- munit s_opg_div_cr state
|
181 |
25 |
wfjm |
munit_s_div_sr : slbit; -- munit s_opg_div_sr state
|
182 |
8 |
wfjm |
munit_s_ash : slbit; -- munit s_opg_ash state
|
183 |
|
|
munit_s_ash_cn : slbit; -- munit s_opg_ash_cn state
|
184 |
|
|
munit_s_ashc : slbit; -- munit s_opg_ashc state
|
185 |
|
|
munit_s_ashc_cn : slbit; -- munit s_opg_ashc_cn state
|
186 |
2 |
wfjm |
ireg_we : slbit; -- ireg register write enable
|
187 |
|
|
cres_sel : slv3; -- result bus (cres) select
|
188 |
|
|
dres_sel : slv3; -- result bus (dres) select
|
189 |
|
|
vmaddr_sel : slv2; -- virtual address select
|
190 |
|
|
cpdout_we : slbit; -- capture dres for cpdout
|
191 |
|
|
end record dpath_cntl_type;
|
192 |
|
|
|
193 |
|
|
constant dpath_cntl_init : dpath_cntl_type := (
|
194 |
|
|
"000","000","00",'0','0','0','0', -- gpr
|
195 |
|
|
'0','0',"000", -- psr
|
196 |
|
|
'0','0','0','0',"00",'0', -- dsrc,..,dtmp
|
197 |
8 |
wfjm |
"00",'0',"000000000","00",'0', -- ounit
|
198 |
|
|
"00","00","00",'0',"000",'0', -- aunit
|
199 |
|
|
"0000",'0', -- lunit
|
200 |
25 |
wfjm |
"00",'0','0','0','0','0','0','0','0',-- munit
|
201 |
2 |
wfjm |
'0',"000","000","00",'0' -- rest
|
202 |
|
|
);
|
203 |
|
|
|
204 |
|
|
constant c_dpath_dsrc_src : slbit := '0'; -- DSRC = R(SRC)
|
205 |
|
|
constant c_dpath_dsrc_res : slbit := '1'; -- DSRC = DRES
|
206 |
|
|
constant c_dpath_ddst_dst : slbit := '0'; -- DDST = R(DST)
|
207 |
|
|
constant c_dpath_ddst_res : slbit := '1'; -- DDST = DRES
|
208 |
|
|
|
209 |
|
|
constant c_dpath_dtmp_dsrc : slv2 := "00"; -- DTMP = DSRC
|
210 |
|
|
constant c_dpath_dtmp_psw : slv2 := "01"; -- DTMP = PSW
|
211 |
|
|
constant c_dpath_dtmp_dres : slv2 := "10"; -- DTMP = DRES
|
212 |
|
|
constant c_dpath_dtmp_drese : slv2 := "11"; -- DTMP = DRESE
|
213 |
|
|
|
214 |
8 |
wfjm |
constant c_dpath_res_ounit : slv3 := "000"; -- D/CRES = OUNIT
|
215 |
|
|
constant c_dpath_res_aunit : slv3 := "001"; -- D/CRES = AUNIT
|
216 |
|
|
constant c_dpath_res_lunit : slv3 := "010"; -- D/CRES = LUNIT
|
217 |
|
|
constant c_dpath_res_munit : slv3 := "011"; -- D/CRES = MUNIT
|
218 |
2 |
wfjm |
constant c_dpath_res_vmdout : slv3 := "100"; -- D/CRES = VMDOUT
|
219 |
|
|
constant c_dpath_res_fpdout : slv3 := "101"; -- D/CRES = FPDOUT
|
220 |
|
|
constant c_dpath_res_ireg : slv3 := "110"; -- D/CRES = IREG
|
221 |
|
|
constant c_dpath_res_cpdin : slv3 := "111"; -- D/CRES = CPDIN
|
222 |
|
|
|
223 |
|
|
constant c_dpath_vmaddr_dsrc : slv2 := "00"; -- VMADDR = DSRC
|
224 |
|
|
constant c_dpath_vmaddr_ddst : slv2 := "01"; -- VMADDR = DDST
|
225 |
|
|
constant c_dpath_vmaddr_pc : slv2 := "10"; -- VMADDR = PC
|
226 |
|
|
constant c_dpath_vmaddr_dtmp : slv2 := "11"; -- VMADDR = DTMP
|
227 |
|
|
|
228 |
|
|
type dpath_stat_type is record -- data path status
|
229 |
|
|
ccout_z : slbit; -- current effective Z cc flag
|
230 |
|
|
shc_tc : slbit; -- last shc cycle (shc==0)
|
231 |
25 |
wfjm |
div_cr : slbit; -- division: remainder correction needed
|
232 |
2 |
wfjm |
div_cq : slbit; -- division: quotient correction needed
|
233 |
25 |
wfjm |
div_quit : slbit; -- division: abort (0/ or /0 or V=1)
|
234 |
2 |
wfjm |
end record dpath_stat_type;
|
235 |
|
|
|
236 |
|
|
constant dpath_stat_init : dpath_stat_type := (others=>'0');
|
237 |
|
|
|
238 |
|
|
type decode_stat_type is record -- decode status
|
239 |
|
|
is_dstmode0 : slbit; -- dest. is register mode
|
240 |
|
|
is_srcpc : slbit; -- source is pc
|
241 |
|
|
is_srcpcmode1 : slbit; -- source is pc and mode=1
|
242 |
|
|
is_dstpc : slbit; -- dest. is pc
|
243 |
|
|
is_dstw_reg : slbit; -- dest. register to be written
|
244 |
|
|
is_dstw_pc : slbit; -- pc register to be written
|
245 |
|
|
is_rmwop : slbit; -- read-modify-write operation
|
246 |
|
|
is_bytop : slbit; -- byte operation
|
247 |
|
|
is_res : slbit; -- reserved operation code
|
248 |
|
|
op_rtt : slbit; -- RTT instruction
|
249 |
|
|
op_mov : slbit; -- MOV instruction
|
250 |
|
|
trap_vec : slv3; -- trap vector addr bits 4:2
|
251 |
|
|
force_srcsp : slbit; -- force src register to be sp
|
252 |
|
|
updt_dstadsrc : slbit; -- update dsrc in dsta flow
|
253 |
8 |
wfjm |
aunit_srcmod : slv2; -- aunit src port modifier
|
254 |
|
|
aunit_dstmod : slv2; -- aunit dst port modifier
|
255 |
|
|
aunit_cimod : slv2; -- aunit ci port modifier
|
256 |
|
|
aunit_cc1op : slbit; -- aunit use cc modes (1 op instruction)
|
257 |
|
|
aunit_ccmode : slv3; -- aunit cc port mode
|
258 |
|
|
lunit_func : slv4; -- lunit function
|
259 |
|
|
munit_func : slv2; -- munit function
|
260 |
2 |
wfjm |
res_sel : slv3; -- result bus (cres/dres) select
|
261 |
|
|
fork_op : slv4; -- op fork after idecode state
|
262 |
|
|
fork_srcr : slv2; -- src-read fork after idecode state
|
263 |
|
|
fork_dstr : slv2; -- dst-read fork after src read state
|
264 |
|
|
fork_dsta : slv2; -- dst-addr fork after idecode state
|
265 |
|
|
fork_opg : slv4; -- opg fork
|
266 |
|
|
fork_opa : slv3; -- opa fork
|
267 |
|
|
do_fork_op : slbit; -- execute fork_op
|
268 |
|
|
do_fork_srcr : slbit; -- execute fork_srcr
|
269 |
|
|
do_fork_dstr : slbit; -- execute fork_dstr
|
270 |
|
|
do_fork_dsta : slbit; -- execute fork_dsta
|
271 |
|
|
do_fork_opg : slbit; -- execute fork_opg
|
272 |
|
|
do_pref_dec : slbit; -- can do prefetch at decode phase
|
273 |
|
|
end record decode_stat_type;
|
274 |
|
|
|
275 |
|
|
constant decode_stat_init : decode_stat_type := (
|
276 |
|
|
'0','0','0','0','0','0','0','0','0', -- is_
|
277 |
|
|
'0','0',"000",'0','0', -- op_, trap_, force_, updt_
|
278 |
8 |
wfjm |
"00","00","00",'0',"000", -- aunit_
|
279 |
|
|
"0000","00","000", -- lunit_, munit_, res_
|
280 |
2 |
wfjm |
"0000","00","00","00","0000","000", -- fork_
|
281 |
|
|
'0','0','0','0','0', -- do_fork_
|
282 |
|
|
'0' -- do_pref_
|
283 |
|
|
);
|
284 |
|
|
|
285 |
|
|
constant c_fork_op_halt : slv4 := "0000";
|
286 |
|
|
constant c_fork_op_wait : slv4 := "0001";
|
287 |
|
|
constant c_fork_op_rtti : slv4 := "0010";
|
288 |
|
|
constant c_fork_op_trap : slv4 := "0011";
|
289 |
|
|
constant c_fork_op_reset: slv4 := "0100";
|
290 |
|
|
constant c_fork_op_rts : slv4 := "0101";
|
291 |
|
|
constant c_fork_op_spl : slv4 := "0110";
|
292 |
|
|
constant c_fork_op_mcc : slv4 := "0111";
|
293 |
|
|
constant c_fork_op_br : slv4 := "1000";
|
294 |
|
|
constant c_fork_op_mark : slv4 := "1001";
|
295 |
|
|
constant c_fork_op_sob : slv4 := "1010";
|
296 |
|
|
constant c_fork_op_mtp : slv4 := "1011";
|
297 |
|
|
|
298 |
|
|
constant c_fork_srcr_def : slv2:= "00";
|
299 |
|
|
constant c_fork_srcr_inc : slv2:= "01";
|
300 |
|
|
constant c_fork_srcr_dec : slv2:= "10";
|
301 |
|
|
constant c_fork_srcr_ind : slv2:= "11";
|
302 |
|
|
|
303 |
|
|
constant c_fork_dstr_def : slv2:= "00";
|
304 |
|
|
constant c_fork_dstr_inc : slv2:= "01";
|
305 |
|
|
constant c_fork_dstr_dec : slv2:= "10";
|
306 |
|
|
constant c_fork_dstr_ind : slv2:= "11";
|
307 |
|
|
|
308 |
|
|
constant c_fork_dsta_def : slv2:= "00";
|
309 |
|
|
constant c_fork_dsta_inc : slv2:= "01";
|
310 |
|
|
constant c_fork_dsta_dec : slv2:= "10";
|
311 |
|
|
constant c_fork_dsta_ind : slv2:= "11";
|
312 |
|
|
|
313 |
|
|
constant c_fork_opg_gen : slv4 := "0000";
|
314 |
|
|
constant c_fork_opg_wdef : slv4 := "0001";
|
315 |
|
|
constant c_fork_opg_winc : slv4 := "0010";
|
316 |
|
|
constant c_fork_opg_wdec : slv4 := "0011";
|
317 |
|
|
constant c_fork_opg_wind : slv4 := "0100";
|
318 |
|
|
constant c_fork_opg_mul : slv4 := "0101";
|
319 |
|
|
constant c_fork_opg_div : slv4 := "0110";
|
320 |
|
|
constant c_fork_opg_ash : slv4 := "0111";
|
321 |
|
|
constant c_fork_opg_ashc : slv4 := "1000";
|
322 |
|
|
|
323 |
|
|
constant c_fork_opa_jsr : slv3 := "000";
|
324 |
|
|
constant c_fork_opa_jmp : slv3 := "001";
|
325 |
|
|
constant c_fork_opa_mtp : slv3 := "010";
|
326 |
|
|
constant c_fork_opa_mfp_reg : slv3 := "011";
|
327 |
|
|
constant c_fork_opa_mfp_mem : slv3 := "100";
|
328 |
|
|
|
329 |
|
|
-- Note: MSB=0 are 'normal' states, MSB=1 are fatal errors
|
330 |
|
|
constant c_cpurust_init : slv4 := "0000"; -- cpu in init state
|
331 |
|
|
constant c_cpurust_halt : slv4 := "0001"; -- cpu executed HALT
|
332 |
|
|
constant c_cpurust_reset : slv4 := "0010"; -- cpu was reset
|
333 |
|
|
constant c_cpurust_stop : slv4 := "0011"; -- cpu was stopped
|
334 |
|
|
constant c_cpurust_step : slv4 := "0100"; -- cpu was stepped
|
335 |
|
|
constant c_cpurust_susp : slv4 := "0101"; -- cpu was suspended
|
336 |
|
|
constant c_cpurust_runs : slv4 := "0111"; -- cpu running
|
337 |
|
|
constant c_cpurust_vecfet : slv4 := "1000"; -- vector fetch error halt
|
338 |
|
|
constant c_cpurust_recrsv : slv4 := "1001"; -- recursive red-stack halt
|
339 |
|
|
constant c_cpurust_sfail : slv4 := "1100"; -- sequencer failure
|
340 |
|
|
constant c_cpurust_vfail : slv4 := "1101"; -- vmbox failure
|
341 |
|
|
|
342 |
|
|
type cpustat_type is record -- CPU status
|
343 |
|
|
cmdbusy : slbit; -- command busy
|
344 |
|
|
cmdack : slbit; -- command acknowledge
|
345 |
|
|
cmderr : slbit; -- command error
|
346 |
|
|
cmdmerr : slbit; -- command memory access error
|
347 |
|
|
cpugo : slbit; -- CPU go state
|
348 |
|
|
cpustep : slbit; -- CPU step flag
|
349 |
30 |
wfjm |
cpususp : slbit; -- CPU susp flag
|
350 |
2 |
wfjm |
cpuwait : slbit; -- CPU wait flag
|
351 |
|
|
cpurust : slv4; -- CPU run status
|
352 |
30 |
wfjm |
suspint : slbit; -- internal suspend flag
|
353 |
|
|
suspext : slbit; -- external suspend flag
|
354 |
2 |
wfjm |
cpfunc : slv5; -- current control port function
|
355 |
|
|
cprnum : slv3; -- current control port register number
|
356 |
|
|
waitsusp : slbit; -- WAIT instruction suspended
|
357 |
30 |
wfjm |
itimer : slbit; -- ITIMER pulse
|
358 |
|
|
creset : slbit; -- CRESET pulse
|
359 |
|
|
breset : slbit; -- BRESET pulse
|
360 |
|
|
intack : slbit; -- INT_ACK pulse
|
361 |
2 |
wfjm |
intvect : slv9_2; -- current interrupt vector
|
362 |
|
|
trap_mmu : slbit; -- mmu trace trap pending
|
363 |
|
|
trap_ysv : slbit; -- ysv trap pending
|
364 |
|
|
prefdone : slbit; -- prefetch done
|
365 |
|
|
do_gprwe : slbit; -- pending gpr_we
|
366 |
|
|
do_intrsv : slbit; -- active rsv interrupt sequence
|
367 |
|
|
end record cpustat_type;
|
368 |
|
|
|
369 |
|
|
constant cpustat_init : cpustat_type := (
|
370 |
30 |
wfjm |
'0','0','0','0', -- cmdbusy,cmdack,cmderr,cmdmerr
|
371 |
|
|
'0','0','0','0', -- cpugo,cpustep,cpususp,cpuwait
|
372 |
2 |
wfjm |
c_cpurust_init, -- cpurust
|
373 |
30 |
wfjm |
'0','0', -- suspint,suspext
|
374 |
2 |
wfjm |
"00000","000", -- cpfunc, cprnum
|
375 |
|
|
'0', -- waitsusp
|
376 |
30 |
wfjm |
'0','0','0','0', -- itimer,creset,breset,intack
|
377 |
2 |
wfjm |
(others=>'0'), -- intvect
|
378 |
|
|
'0','0','0', -- trap_(mmu|ysv), prefdone
|
379 |
|
|
'0','0' -- do_gprwe, do_intrsv
|
380 |
|
|
);
|
381 |
|
|
|
382 |
|
|
type cpuerr_type is record -- CPU error register
|
383 |
|
|
illhlt : slbit; -- illegal halt (in non-kernel mode)
|
384 |
|
|
adderr : slbit; -- address error (odd, jmp/jsr reg)
|
385 |
|
|
nxm : slbit; -- non-existent memory
|
386 |
|
|
iobto : slbit; -- I/O bus timeout (non-exist UB)
|
387 |
|
|
ysv : slbit; -- yellow stack violation
|
388 |
|
|
rsv : slbit; -- red stack violation
|
389 |
|
|
end record cpuerr_type;
|
390 |
|
|
|
391 |
|
|
constant cpuerr_init : cpuerr_type := (others=>'0');
|
392 |
|
|
|
393 |
|
|
type vm_cntl_type is record -- virt memory control port
|
394 |
|
|
req : slbit; -- request
|
395 |
|
|
wacc : slbit; -- write access
|
396 |
|
|
macc : slbit; -- modify access (r-m-w sequence)
|
397 |
|
|
cacc : slbit; -- console access
|
398 |
|
|
bytop : slbit; -- byte operation
|
399 |
|
|
dspace : slbit; -- dspace operation
|
400 |
|
|
kstack : slbit; -- access through kernel stack
|
401 |
|
|
intrsv : slbit; -- active rsv interrupt sequence
|
402 |
|
|
mode : slv2; -- mode
|
403 |
|
|
trap_done : slbit; -- mmu trap taken (to set ssr0 bit)
|
404 |
|
|
end record vm_cntl_type;
|
405 |
|
|
|
406 |
|
|
constant vm_cntl_init : vm_cntl_type := (
|
407 |
|
|
'0','0','0','0', -- req, wacc, macc,cacc
|
408 |
|
|
'0','0','0', -- bytop, dspace, kstack
|
409 |
|
|
'0',"00",'0' -- intrsv, mode, trap_done
|
410 |
|
|
);
|
411 |
|
|
|
412 |
|
|
type vm_stat_type is record -- virt memory status port
|
413 |
|
|
ack : slbit; -- acknowledge
|
414 |
|
|
err : slbit; -- error (see err_xxx for reason)
|
415 |
|
|
fail : slbit; -- failure (machine check)
|
416 |
|
|
err_odd : slbit; -- abort: odd address error
|
417 |
|
|
err_mmu : slbit; -- abort: mmu reject
|
418 |
|
|
err_nxm : slbit; -- abort: non-existing memory
|
419 |
|
|
err_iobto : slbit; -- abort: non-existing I/O resource
|
420 |
|
|
err_rsv : slbit; -- abort: red stack violation
|
421 |
|
|
trap_ysv : slbit; -- trap: yellow stack violation
|
422 |
|
|
trap_mmu : slbit; -- trap: mmu trace trap
|
423 |
|
|
end record vm_stat_type;
|
424 |
|
|
|
425 |
|
|
constant vm_stat_init : vm_stat_type := (others=>'0');
|
426 |
|
|
|
427 |
|
|
type em_mreq_type is record -- external memory - master request
|
428 |
|
|
req : slbit; -- request
|
429 |
|
|
we : slbit; -- write enable
|
430 |
|
|
be : slv2; -- byte enables
|
431 |
|
|
cancel : slbit; -- cancel request
|
432 |
|
|
addr : slv22_1; -- address
|
433 |
|
|
din : slv16; -- data in (input to memory)
|
434 |
|
|
end record em_mreq_type;
|
435 |
|
|
|
436 |
|
|
constant em_mreq_init : em_mreq_type := (
|
437 |
|
|
'0','0',"00",'0', -- req, we, be, cancel
|
438 |
|
|
(others=>'0'),(others=>'0') -- addr, din
|
439 |
|
|
);
|
440 |
|
|
|
441 |
|
|
type em_sres_type is record -- external memory - slave response
|
442 |
|
|
ack_r : slbit; -- acknowledge read
|
443 |
|
|
ack_w : slbit; -- acknowledge write
|
444 |
|
|
dout : slv16; -- data out (output from memory)
|
445 |
|
|
end record em_sres_type;
|
446 |
|
|
|
447 |
|
|
constant em_sres_init : em_sres_type := (
|
448 |
|
|
'0','0', -- ack_r, ack_w
|
449 |
|
|
(others=>'0') -- dout
|
450 |
|
|
);
|
451 |
|
|
|
452 |
|
|
type mmu_cntl_type is record -- mmu control port
|
453 |
|
|
req : slbit; -- translate request
|
454 |
|
|
wacc : slbit; -- write access
|
455 |
|
|
macc : slbit; -- modify access (r-m-w sequence)
|
456 |
|
|
cacc : slbit; -- console access (bypass mmu)
|
457 |
|
|
dspace : slbit; -- dspace access
|
458 |
|
|
mode : slv2; -- processor mode
|
459 |
|
|
trap_done : slbit; -- mmu trap taken (set ssr0 bit)
|
460 |
|
|
end record mmu_cntl_type;
|
461 |
|
|
|
462 |
|
|
constant mmu_cntl_init : mmu_cntl_type := (
|
463 |
|
|
'0','0','0','0', -- req, wacc, macc, cacc
|
464 |
|
|
'0',"00",'0' -- dspace, mode, trap_done
|
465 |
|
|
);
|
466 |
|
|
|
467 |
|
|
type mmu_stat_type is record -- mmu status port
|
468 |
|
|
vaok : slbit; -- virtual address valid
|
469 |
|
|
trap : slbit; -- mmu trap request
|
470 |
|
|
ena_mmu : slbit; -- mmu enable (ssr0 bit 0)
|
471 |
|
|
ena_22bit : slbit; -- mmu in 22 bit mode (ssr3 bit 4)
|
472 |
|
|
ena_ubmap : slbit; -- ubmap enable (ssr3 bit 5)
|
473 |
|
|
end record mmu_stat_type;
|
474 |
|
|
|
475 |
|
|
constant mmu_stat_init : mmu_stat_type := (others=>'0');
|
476 |
|
|
|
477 |
|
|
type mmu_moni_type is record -- mmu monitor port
|
478 |
|
|
istart : slbit; -- instruction start
|
479 |
|
|
idone : slbit; -- instruction done
|
480 |
|
|
pc : slv16; -- PC of new instruction
|
481 |
|
|
regmod : slbit; -- register modified
|
482 |
|
|
regnum : slv3; -- register number
|
483 |
|
|
delta : slv4; -- register offset
|
484 |
|
|
isdec : slbit; -- offset to be subtracted
|
485 |
|
|
trace_prev : slbit; -- use ssr12 trace state of prev. state
|
486 |
|
|
end record mmu_moni_type;
|
487 |
|
|
|
488 |
|
|
constant mmu_moni_init : mmu_moni_type := (
|
489 |
|
|
'0','0',(others=>'0'), -- istart, idone, pc
|
490 |
|
|
'0',"000","0000", -- regmod, regnum, delta
|
491 |
|
|
'0','0' -- isdec, trace_prev
|
492 |
|
|
);
|
493 |
|
|
|
494 |
|
|
type mmu_ssr0_type is record -- MMU ssr0
|
495 |
|
|
abo_nonres : slbit; -- abort non resident
|
496 |
|
|
abo_length : slbit; -- abort segment length
|
497 |
|
|
abo_rdonly : slbit; -- abort read-only
|
498 |
|
|
trap_mmu : slbit; -- trap management
|
499 |
|
|
ena_trap : slbit; -- enable traps
|
500 |
|
|
inst_compl : slbit; -- instruction complete
|
501 |
|
|
seg_mode : slv2; -- segement mode
|
502 |
|
|
dspace : slbit; -- address space (D=1, I=0)
|
503 |
|
|
seg_num : slv3; -- segment number
|
504 |
|
|
ena_mmu : slbit; -- enable memory management
|
505 |
|
|
trace_prev : slbit; -- ssr12 trace status in prev. state
|
506 |
|
|
end record mmu_ssr0_type;
|
507 |
|
|
|
508 |
|
|
constant mmu_ssr0_init : mmu_ssr0_type := (
|
509 |
|
|
inst_compl=>'0', seg_mode=>"00", seg_num=>"000",
|
510 |
|
|
others=>'0'
|
511 |
|
|
);
|
512 |
|
|
|
513 |
|
|
type mmu_ssr1_type is record -- MMU ssr1
|
514 |
|
|
rb_delta : slv5; -- RB: amount change
|
515 |
|
|
rb_num : slv3; -- RB: register number
|
516 |
|
|
ra_delta : slv5; -- RA: amount change
|
517 |
|
|
ra_num : slv3; -- RA: register number
|
518 |
|
|
end record mmu_ssr1_type;
|
519 |
|
|
|
520 |
|
|
constant mmu_ssr1_init : mmu_ssr1_type := (
|
521 |
|
|
"00000","000", -- rb_...
|
522 |
|
|
"00000","000" -- ra_...
|
523 |
|
|
);
|
524 |
|
|
|
525 |
|
|
type mmu_ssr3_type is record -- MMU ssr3
|
526 |
|
|
ena_ubmap : slbit; -- enable unibus mapping
|
527 |
|
|
ena_22bit : slbit; -- enable 22 bit mapping
|
528 |
|
|
dspace_km : slbit; -- enable dspace kernel
|
529 |
|
|
dspace_sm : slbit; -- enable dspace supervisor
|
530 |
|
|
dspace_um : slbit; -- enable dspace user
|
531 |
|
|
end record mmu_ssr3_type;
|
532 |
|
|
|
533 |
|
|
constant mmu_ssr3_init : mmu_ssr3_type := (others=>'0');
|
534 |
|
|
|
535 |
|
|
-- control port definitions --------------------------------------------------
|
536 |
|
|
|
537 |
|
|
type cp_cntl_type is record -- control port control
|
538 |
|
|
req : slbit; -- request
|
539 |
|
|
func : slv5; -- function
|
540 |
|
|
rnum : slv3; -- register number
|
541 |
|
|
end record cp_cntl_type;
|
542 |
|
|
|
543 |
30 |
wfjm |
constant c_cpfunc_noop : slv5 := "00000"; -- noop : no operation
|
544 |
|
|
constant c_cpfunc_start : slv5 := "00001"; -- sta : cpu start
|
545 |
|
|
constant c_cpfunc_stop : slv5 := "00010"; -- sto : cpu stop
|
546 |
|
|
constant c_cpfunc_step : slv5 := "00011"; -- cont : cpu step
|
547 |
|
|
constant c_cpfunc_creset : slv5 := "00100"; -- step : cpu cpu reset
|
548 |
|
|
constant c_cpfunc_breset : slv5 := "00101"; -- rst : cpu bus reset
|
549 |
|
|
constant c_cpfunc_suspend : slv5 := "00110"; -- rst : cpu suspend
|
550 |
|
|
constant c_cpfunc_resume : slv5 := "00111"; -- rst : cpu resume
|
551 |
2 |
wfjm |
|
552 |
30 |
wfjm |
constant c_cpfunc_rreg : slv5 := "10000"; -- rreg : read register
|
553 |
|
|
constant c_cpfunc_wreg : slv5 := "10001"; -- wreg : write register
|
554 |
|
|
constant c_cpfunc_rpsw : slv5 := "10010"; -- rpsw : read psw
|
555 |
|
|
constant c_cpfunc_wpsw : slv5 := "10011"; -- wpsw : write psw
|
556 |
|
|
constant c_cpfunc_rmem : slv5 := "10100"; -- rmem : read memory
|
557 |
|
|
constant c_cpfunc_wmem : slv5 := "10101"; -- wmem : write memory
|
558 |
|
|
|
559 |
2 |
wfjm |
constant cp_cntl_init : cp_cntl_type := ('0',c_cpfunc_noop,"000");
|
560 |
|
|
|
561 |
|
|
type cp_stat_type is record -- control port status
|
562 |
|
|
cmdbusy : slbit; -- command busy
|
563 |
|
|
cmdack : slbit; -- command acknowledge
|
564 |
|
|
cmderr : slbit; -- command error
|
565 |
|
|
cmdmerr : slbit; -- command memory access error
|
566 |
|
|
cpugo : slbit; -- CPU go state
|
567 |
|
|
cpustep : slbit; -- CPU step flag
|
568 |
|
|
cpuwait : slbit; -- CPU wait flag
|
569 |
30 |
wfjm |
cpususp : slbit; -- CPU susp flag
|
570 |
2 |
wfjm |
cpurust : slv4; -- CPU run status
|
571 |
30 |
wfjm |
suspint : slbit; -- internal suspend
|
572 |
|
|
suspext : slbit; -- external suspend
|
573 |
2 |
wfjm |
end record cp_stat_type;
|
574 |
|
|
|
575 |
|
|
constant cp_stat_init : cp_stat_type := (
|
576 |
|
|
'0','0','0','0', -- cmd...
|
577 |
|
|
'0','0','0','0', -- cpu...
|
578 |
30 |
wfjm |
(others=>'0'), -- cpurust
|
579 |
|
|
'0','0' -- susp...
|
580 |
2 |
wfjm |
);
|
581 |
|
|
|
582 |
|
|
type cp_addr_type is record -- control port address
|
583 |
|
|
addr : slv22_1; -- address
|
584 |
28 |
wfjm |
racc : slbit; -- ibus remote access
|
585 |
2 |
wfjm |
be : slv2; -- byte enables
|
586 |
|
|
ena_22bit : slbit; -- enable 22 bit mode
|
587 |
|
|
ena_ubmap : slbit; -- enable unibus mapper
|
588 |
|
|
end record cp_addr_type;
|
589 |
|
|
|
590 |
|
|
constant cp_addr_init : cp_addr_type := (
|
591 |
|
|
(others=>'0'), -- addr
|
592 |
|
|
'0',"00", -- racc, be
|
593 |
|
|
'0','0' -- ena_...
|
594 |
|
|
);
|
595 |
|
|
|
596 |
|
|
-- debug and monitoring port definitions -------------------------------------
|
597 |
|
|
|
598 |
|
|
type dm_cntl_type is record -- debug and monitor control
|
599 |
|
|
dum1 : slbit; -- dummy 1
|
600 |
|
|
dum2 : slbit; -- dummy 2
|
601 |
|
|
end record dm_cntl_type;
|
602 |
|
|
|
603 |
|
|
constant dm_cntl_init : dm_cntl_type := (others=>'0');
|
604 |
|
|
|
605 |
|
|
type dm_stat_dp_type is record -- debug and monitor status - dpath
|
606 |
|
|
pc : slv16; -- pc
|
607 |
|
|
psw : psw_type; -- psw
|
608 |
|
|
ireg : slv16; -- ireg
|
609 |
|
|
ireg_we : slbit; -- ireg we
|
610 |
|
|
dsrc : slv16; -- dsrc register
|
611 |
|
|
ddst : slv16; -- ddst register
|
612 |
|
|
dtmp : slv16; -- dtmp register
|
613 |
|
|
dres : slv16; -- dres bus
|
614 |
|
|
gpr_adst : slv3; -- gpr dst regsiter
|
615 |
|
|
gpr_mode : slv2; -- gpr mode
|
616 |
|
|
gpr_bytop : slbit; -- gpr bytop
|
617 |
|
|
gpr_we : slbit; -- gpr we
|
618 |
|
|
end record dm_stat_dp_type;
|
619 |
|
|
|
620 |
|
|
constant dm_stat_dp_init : dm_stat_dp_type := (
|
621 |
|
|
(others=>'0'), -- pc
|
622 |
|
|
psw_init, -- psw
|
623 |
|
|
(others=>'0'),'0', -- ireg, ireg_we
|
624 |
|
|
(others=>'0'),(others=>'0'), -- dsrc, ddst
|
625 |
|
|
(others=>'0'),(others=>'0'), -- dtmp, dres
|
626 |
|
|
(others=>'0'),(others=>'0'), -- gpr_adst, gpr_mode
|
627 |
|
|
'0','0' -- gpr_bytop, gpr_we
|
628 |
|
|
);
|
629 |
|
|
|
630 |
|
|
type dm_stat_vm_type is record -- debug and monitor status - vmbox
|
631 |
|
|
ibmreq : ib_mreq_type; -- ibus master request
|
632 |
|
|
ibsres : ib_sres_type; -- ibus slave response
|
633 |
|
|
end record dm_stat_vm_type;
|
634 |
|
|
|
635 |
|
|
constant dm_stat_vm_init : dm_stat_vm_type := (ib_mreq_init,ib_sres_init);
|
636 |
|
|
|
637 |
|
|
type dm_stat_co_type is record -- debug and monitor status - core
|
638 |
|
|
cpugo : slbit; -- cpugo state flag
|
639 |
30 |
wfjm |
cpususp : slbit; -- cpususp state flag
|
640 |
|
|
suspint : slbit; -- suspint state flag
|
641 |
|
|
suspext : slbit; -- suspext state flag
|
642 |
2 |
wfjm |
end record dm_stat_co_type;
|
643 |
|
|
|
644 |
30 |
wfjm |
constant dm_stat_co_init : dm_stat_co_type := (
|
645 |
|
|
'0','0', -- cpu...
|
646 |
|
|
'0','0' -- susp...
|
647 |
|
|
);
|
648 |
2 |
wfjm |
|
649 |
|
|
type dm_stat_sy_type is record -- debug and monitor status - system
|
650 |
|
|
emmreq : em_mreq_type; -- external memory: request
|
651 |
|
|
emsres : em_sres_type; -- external memory: response
|
652 |
|
|
chit : slbit; -- cache hit
|
653 |
|
|
end record dm_stat_sy_type;
|
654 |
|
|
|
655 |
30 |
wfjm |
constant dm_stat_sy_init : dm_stat_sy_type := (
|
656 |
|
|
em_mreq_init, -- emmreq
|
657 |
|
|
em_sres_init, -- emsres
|
658 |
|
|
'0' -- chit
|
659 |
|
|
);
|
660 |
2 |
wfjm |
|
661 |
|
|
-- rbus interface definitions ------------------------------------------------
|
662 |
|
|
|
663 |
|
|
constant c_rbaddr_conf : slv5 := "00000"; -- R/W configuration reg
|
664 |
|
|
constant c_rbaddr_cntl : slv5 := "00001"; -- -/F control reg
|
665 |
|
|
constant c_rbaddr_stat : slv5 := "00010"; -- R/- status reg
|
666 |
|
|
constant c_rbaddr_psw : slv5 := "00011"; -- R/W psw access
|
667 |
|
|
constant c_rbaddr_al : slv5 := "00100"; -- R/W address low reg
|
668 |
|
|
constant c_rbaddr_ah : slv5 := "00101"; -- R/W address high reg
|
669 |
|
|
constant c_rbaddr_mem : slv5 := "00110"; -- R/W memory access
|
670 |
|
|
constant c_rbaddr_memi : slv5 := "00111"; -- R/W memory access; inc addr
|
671 |
|
|
|
672 |
|
|
constant c_rbaddr_r0 : slv5 := "01000"; -- R/W gpr 0
|
673 |
|
|
constant c_rbaddr_r1 : slv5 := "01001"; -- R/W gpr 1
|
674 |
|
|
constant c_rbaddr_r2 : slv5 := "01010"; -- R/W gpr 2
|
675 |
|
|
constant c_rbaddr_r3 : slv5 := "01011"; -- R/W gpr 3
|
676 |
|
|
constant c_rbaddr_r4 : slv5 := "01100"; -- R/W gpr 4
|
677 |
|
|
constant c_rbaddr_r5 : slv5 := "01101"; -- R/W gpr 5
|
678 |
|
|
constant c_rbaddr_sp : slv5 := "01110"; -- R/W gpr 6 (sp)
|
679 |
|
|
constant c_rbaddr_pc : slv5 := "01111"; -- R/W gpr 7 (pc)
|
680 |
|
|
|
681 |
28 |
wfjm |
constant c_rbaddr_membe: slv5 := "10000"; -- R/W memory write byte enables
|
682 |
2 |
wfjm |
|
683 |
28 |
wfjm |
subtype c_al_rbf_addr is integer range 15 downto 1; -- al: address
|
684 |
|
|
constant c_ah_rbf_ena_ubmap: integer := 7; -- ah: ubmap
|
685 |
|
|
constant c_ah_rbf_ena_22bit: integer := 6; -- ah: 22bit
|
686 |
|
|
subtype c_ah_rbf_addr is integer range 5 downto 0; -- ah: address
|
687 |
2 |
wfjm |
|
688 |
30 |
wfjm |
constant c_stat_rbf_suspext: integer := 9; -- stat field: suspext
|
689 |
|
|
constant c_stat_rbf_suspint: integer := 8; -- stat field: suspint
|
690 |
|
|
subtype c_stat_rbf_cpurust is integer range 7 downto 4; -- cpurust
|
691 |
|
|
constant c_stat_rbf_cpususp: integer := 3; -- stat field: cpususp
|
692 |
|
|
constant c_stat_rbf_cpugo: integer := 2; -- stat field: cpugo
|
693 |
|
|
constant c_stat_rbf_cmdmerr: integer := 1; -- stat field: cmdmerr
|
694 |
2 |
wfjm |
constant c_stat_rbf_cmderr: integer := 0; -- stat field: cmderr
|
695 |
|
|
|
696 |
28 |
wfjm |
subtype c_membe_rbf_be is integer range 1 downto 0; -- membe: be's
|
697 |
|
|
constant c_membe_rbf_stick: integer := 2; -- membe: sticky flag
|
698 |
|
|
|
699 |
2 |
wfjm |
-- -------------------------------------
|
700 |
|
|
|
701 |
|
|
component pdp11_gpr is -- general purpose registers
|
702 |
|
|
port (
|
703 |
|
|
CLK : in slbit; -- clock
|
704 |
|
|
DIN : in slv16; -- input data
|
705 |
|
|
ASRC : in slv3; -- source register number
|
706 |
|
|
ADST : in slv3; -- destination register number
|
707 |
|
|
MODE : in slv2; -- processor mode (k=>00,s=>01,u=>11)
|
708 |
|
|
RSET : in slbit; -- register set
|
709 |
|
|
WE : in slbit; -- write enable
|
710 |
|
|
BYTOP : in slbit; -- byte operation (write low byte only)
|
711 |
|
|
PCINC : in slbit; -- increment PC
|
712 |
|
|
DSRC : out slv16; -- source register data
|
713 |
|
|
DDST : out slv16; -- destination register data
|
714 |
|
|
PC : out slv16 -- current PC value
|
715 |
|
|
);
|
716 |
|
|
end component;
|
717 |
|
|
|
718 |
|
|
constant c_gpr_r5 : slv3 := "101"; -- register number of r5
|
719 |
|
|
constant c_gpr_sp : slv3 := "110"; -- register number of SP
|
720 |
|
|
constant c_gpr_pc : slv3 := "111"; -- register number of PC
|
721 |
|
|
|
722 |
|
|
component pdp11_psr is -- processor status word register
|
723 |
|
|
port (
|
724 |
|
|
CLK : in slbit; -- clock
|
725 |
30 |
wfjm |
CRESET : in slbit; -- cpu reset
|
726 |
2 |
wfjm |
DIN : in slv16; -- input data
|
727 |
|
|
CCIN : in slv4; -- cc input
|
728 |
|
|
CCWE : in slbit; -- enable update cc
|
729 |
|
|
WE : in slbit; -- write enable (from DIN)
|
730 |
|
|
FUNC : in slv3; -- write function (from DIN)
|
731 |
|
|
PSW : out psw_type; -- current psw
|
732 |
|
|
IB_MREQ : in ib_mreq_type; -- ibus request
|
733 |
|
|
IB_SRES : out ib_sres_type -- ibus response
|
734 |
|
|
);
|
735 |
|
|
end component;
|
736 |
|
|
|
737 |
|
|
constant c_psr_func_wspl : slv3 := "000"; -- SPL mode: set pri
|
738 |
|
|
constant c_psr_func_wcc : slv3 := "001"; -- CC mode: set/clear cc
|
739 |
|
|
constant c_psr_func_wint : slv3 := "010"; -- interupt mode: pmode=cmode
|
740 |
|
|
constant c_psr_func_wrti : slv3 := "011"; -- rti mode: protect modes
|
741 |
|
|
constant c_psr_func_wall : slv3 := "100"; -- write all fields
|
742 |
|
|
|
743 |
8 |
wfjm |
component pdp11_ounit is -- offset adder for addresses (ounit)
|
744 |
2 |
wfjm |
port (
|
745 |
|
|
DSRC : in slv16; -- 'src' data for port A
|
746 |
|
|
DDST : in slv16; -- 'dst' data for port A
|
747 |
|
|
DTMP : in slv16; -- 'tmp' data for port A
|
748 |
|
|
PC : in slv16; -- PC data for port A
|
749 |
|
|
ASEL : in slv2; -- selector for port A
|
750 |
|
|
AZERO : in slbit; -- force zero for port A
|
751 |
|
|
IREG8 : in slv8; -- 'ireg' data for port B
|
752 |
|
|
VMDOUT : in slv16; -- virt. memory data for port B
|
753 |
|
|
CONST : in slv9; -- sequencer const data for port B
|
754 |
|
|
BSEL : in slv2; -- selector for port B
|
755 |
|
|
OPSUB : in slbit; -- operation: 0 add, 1 sub
|
756 |
|
|
DOUT : out slv16; -- data output
|
757 |
|
|
NZOUT : out slv2 -- NZ condition codes out
|
758 |
|
|
);
|
759 |
|
|
end component;
|
760 |
|
|
|
761 |
8 |
wfjm |
constant c_ounit_asel_ddst : slv2 := "00"; -- A = DDST
|
762 |
|
|
constant c_ounit_asel_dsrc : slv2 := "01"; -- A = DSRC
|
763 |
|
|
constant c_ounit_asel_pc : slv2 := "10"; -- A = PC
|
764 |
|
|
constant c_ounit_asel_dtmp : slv2 := "11"; -- A = DTMP
|
765 |
2 |
wfjm |
|
766 |
8 |
wfjm |
constant c_ounit_bsel_const : slv2 := "00"; -- B = CONST
|
767 |
|
|
constant c_ounit_bsel_vmdout : slv2 := "01"; -- B = VMDOUT
|
768 |
|
|
constant c_ounit_bsel_ireg6 : slv2 := "10"; -- B = 2*IREG(6bit)
|
769 |
|
|
constant c_ounit_bsel_ireg8 : slv2 := "11"; -- B = 2*IREG(8bit,sign-extend)
|
770 |
2 |
wfjm |
|
771 |
8 |
wfjm |
component pdp11_aunit is -- arithmetic unit for data (aunit)
|
772 |
2 |
wfjm |
port (
|
773 |
|
|
DSRC : in slv16; -- 'src' data in
|
774 |
|
|
DDST : in slv16; -- 'dst' data in
|
775 |
|
|
CI : in slbit; -- carry flag in
|
776 |
|
|
SRCMOD : in slv2; -- src modifier mode
|
777 |
|
|
DSTMOD : in slv2; -- dst modifier mode
|
778 |
|
|
CIMOD : in slv2; -- ci modifier mode
|
779 |
|
|
CC1OP : in slbit; -- use cc modes (1 op instruction)
|
780 |
|
|
CCMODE : in slv3; -- cc mode
|
781 |
|
|
BYTOP : in slbit; -- byte operation
|
782 |
|
|
DOUT : out slv16; -- data output
|
783 |
|
|
CCOUT : out slv4 -- condition codes out
|
784 |
|
|
);
|
785 |
|
|
end component;
|
786 |
|
|
|
787 |
8 |
wfjm |
constant c_aunit_mod_pass : slv2 := "00"; -- pass data
|
788 |
|
|
constant c_aunit_mod_inv : slv2 := "01"; -- invert data
|
789 |
|
|
constant c_aunit_mod_zero : slv2 := "10"; -- set to 0
|
790 |
|
|
constant c_aunit_mod_one : slv2 := "11"; -- set to 1
|
791 |
2 |
wfjm |
|
792 |
8 |
wfjm |
-- the c_aunit_ccmode codes follow exactly the opcode format (bit 8:6)
|
793 |
|
|
constant c_aunit_ccmode_clr : slv3 := "000"; -- do clr instruction
|
794 |
|
|
constant c_aunit_ccmode_com : slv3 := "001"; -- do com instruction
|
795 |
|
|
constant c_aunit_ccmode_inc : slv3 := "010"; -- do inc instruction
|
796 |
|
|
constant c_aunit_ccmode_dec : slv3 := "011"; -- do dec instruction
|
797 |
|
|
constant c_aunit_ccmode_neg : slv3 := "100"; -- do neg instruction
|
798 |
|
|
constant c_aunit_ccmode_adc : slv3 := "101"; -- do adc instruction
|
799 |
|
|
constant c_aunit_ccmode_sbc : slv3 := "110"; -- do sbc instruction
|
800 |
|
|
constant c_aunit_ccmode_tst : slv3 := "111"; -- do tst instruction
|
801 |
2 |
wfjm |
|
802 |
8 |
wfjm |
component pdp11_lunit is -- logic unit for data (lunit)
|
803 |
2 |
wfjm |
port (
|
804 |
|
|
DSRC : in slv16; -- 'src' data in
|
805 |
|
|
DDST : in slv16; -- 'dst' data in
|
806 |
|
|
CCIN : in slv4; -- condition codes in
|
807 |
|
|
FUNC : in slv4; -- function
|
808 |
|
|
BYTOP : in slbit; -- byte operation
|
809 |
|
|
DOUT : out slv16; -- data output
|
810 |
|
|
CCOUT : out slv4 -- condition codes out
|
811 |
|
|
);
|
812 |
|
|
end component;
|
813 |
|
|
|
814 |
8 |
wfjm |
constant c_lunit_func_asr : slv4 := "0000"; -- ASR/ASRB ??? recheck coding !!
|
815 |
|
|
constant c_lunit_func_asl : slv4 := "0001"; -- ASL/ASLB
|
816 |
|
|
constant c_lunit_func_ror : slv4 := "0010"; -- ROR/RORB
|
817 |
|
|
constant c_lunit_func_rol : slv4 := "0011"; -- ROL/ROLB
|
818 |
|
|
constant c_lunit_func_bis : slv4 := "0100"; -- BIS/BISB
|
819 |
|
|
constant c_lunit_func_bic : slv4 := "0101"; -- BIC/BICB
|
820 |
|
|
constant c_lunit_func_bit : slv4 := "0110"; -- BIT/BITB
|
821 |
|
|
constant c_lunit_func_mov : slv4 := "0111"; -- MOV/MOVB
|
822 |
|
|
constant c_lunit_func_sxt : slv4 := "1000"; -- SXT
|
823 |
|
|
constant c_lunit_func_swap : slv4 := "1001"; -- SWAB
|
824 |
|
|
constant c_lunit_func_xor : slv4 := "1010"; -- XOR
|
825 |
2 |
wfjm |
|
826 |
8 |
wfjm |
component pdp11_munit is -- mul/div unit for data (munit)
|
827 |
2 |
wfjm |
port (
|
828 |
|
|
CLK : in slbit; -- clock
|
829 |
|
|
DSRC : in slv16; -- 'src' data in
|
830 |
|
|
DDST : in slv16; -- 'dst' data in
|
831 |
|
|
DTMP : in slv16; -- 'tmp' data in
|
832 |
|
|
GPR_DSRC : in slv16; -- 'src' data from GPR
|
833 |
|
|
FUNC : in slv2; -- function
|
834 |
25 |
wfjm |
S_DIV : in slbit; -- s_opg_div state (load dd_low)
|
835 |
|
|
S_DIV_CN : in slbit; -- s_opg_div_cn state (1st..16th cycle)
|
836 |
|
|
S_DIV_CR : in slbit; -- s_opg_div_cr state (remainder corr.)
|
837 |
|
|
S_DIV_SR : in slbit; -- s_opg_div_sr state (store remainder)
|
838 |
2 |
wfjm |
S_ASH : in slbit; -- s_opg_ash state
|
839 |
|
|
S_ASH_CN : in slbit; -- s_opg_ash_cn state
|
840 |
|
|
S_ASHC : in slbit; -- s_opg_ashc state
|
841 |
|
|
S_ASHC_CN : in slbit; -- s_opg_ashc_cn state
|
842 |
|
|
SHC_TC : out slbit; -- last shc cycle (shc==0)
|
843 |
25 |
wfjm |
DIV_CR : out slbit; -- division: remainder correction needed
|
844 |
2 |
wfjm |
DIV_CQ : out slbit; -- division: quotient correction needed
|
845 |
25 |
wfjm |
DIV_QUIT : out slbit; -- division: abort (0/ or /0 or V=1)
|
846 |
2 |
wfjm |
DOUT : out slv16; -- data output
|
847 |
|
|
DOUTE : out slv16; -- data output extra
|
848 |
|
|
CCOUT : out slv4 -- condition codes out
|
849 |
|
|
);
|
850 |
|
|
end component;
|
851 |
|
|
|
852 |
8 |
wfjm |
constant c_munit_func_mul : slv2 := "00"; -- MUL
|
853 |
|
|
constant c_munit_func_div : slv2 := "01"; -- DIV
|
854 |
|
|
constant c_munit_func_ash : slv2 := "10"; -- ASH
|
855 |
|
|
constant c_munit_func_ashc : slv2 := "11"; -- ASHC
|
856 |
2 |
wfjm |
|
857 |
|
|
component pdp11_mmu_sadr is -- mmu SAR/SDR register set
|
858 |
|
|
port (
|
859 |
|
|
CLK : in slbit; -- clock
|
860 |
|
|
MODE : in slv2; -- mode
|
861 |
|
|
ASN : in slv4; -- augmented segment number (1+3 bit)
|
862 |
|
|
AIB_WE : in slbit; -- update AIB
|
863 |
|
|
AIB_SETA : in slbit; -- set access AIB
|
864 |
|
|
AIB_SETW : in slbit; -- set write AIB
|
865 |
|
|
SARSDR : out sarsdr_type; -- combined SAR/SDR
|
866 |
|
|
IB_MREQ : in ib_mreq_type; -- ibus request
|
867 |
|
|
IB_SRES : out ib_sres_type -- ibus response
|
868 |
|
|
);
|
869 |
|
|
end component;
|
870 |
|
|
|
871 |
|
|
component pdp11_mmu_ssr12 is -- mmu register ssr1 and ssr2
|
872 |
|
|
port (
|
873 |
|
|
CLK : in slbit; -- clock
|
874 |
30 |
wfjm |
CRESET : in slbit; -- cpu reset
|
875 |
2 |
wfjm |
TRACE : in slbit; -- trace enable
|
876 |
|
|
MONI : in mmu_moni_type; -- MMU monitor port data
|
877 |
|
|
IB_MREQ : in ib_mreq_type; -- ibus request
|
878 |
|
|
IB_SRES : out ib_sres_type -- ibus response
|
879 |
|
|
);
|
880 |
|
|
end component;
|
881 |
|
|
|
882 |
|
|
component pdp11_mmu is -- mmu - memory management unit
|
883 |
|
|
port (
|
884 |
|
|
CLK : in slbit; -- clock
|
885 |
30 |
wfjm |
CRESET : in slbit; -- cpu reset
|
886 |
|
|
BRESET : in slbit; -- bus reset
|
887 |
2 |
wfjm |
CNTL : in mmu_cntl_type; -- control port
|
888 |
|
|
VADDR : in slv16; -- virtual address
|
889 |
|
|
MONI : in mmu_moni_type; -- monitor port
|
890 |
|
|
STAT : out mmu_stat_type; -- status port
|
891 |
|
|
PADDRH : out slv16; -- physical address (upper 16 bit)
|
892 |
|
|
IB_MREQ : in ib_mreq_type; -- ibus request
|
893 |
|
|
IB_SRES : out ib_sres_type -- ibus response
|
894 |
|
|
);
|
895 |
|
|
end component;
|
896 |
|
|
|
897 |
|
|
component pdp11_vmbox is -- virtual memory
|
898 |
|
|
port (
|
899 |
|
|
CLK : in slbit; -- clock
|
900 |
30 |
wfjm |
GRESET : in slbit; -- general reset
|
901 |
|
|
CRESET : in slbit; -- cpu reset
|
902 |
|
|
BRESET : in slbit; -- bus reset
|
903 |
2 |
wfjm |
CP_ADDR : in cp_addr_type; -- console port address
|
904 |
|
|
VM_CNTL : in vm_cntl_type; -- vm control port
|
905 |
|
|
VM_ADDR : in slv16; -- vm address
|
906 |
|
|
VM_DIN : in slv16; -- vm data in
|
907 |
|
|
VM_STAT : out vm_stat_type; -- vm status port
|
908 |
|
|
VM_DOUT : out slv16; -- vm data out
|
909 |
|
|
EM_MREQ : out em_mreq_type; -- external memory: request
|
910 |
|
|
EM_SRES : in em_sres_type; -- external memory: response
|
911 |
|
|
MMU_MONI : in mmu_moni_type; -- mmu monitor port
|
912 |
|
|
IB_MREQ_M : out ib_mreq_type; -- ibus request (master)
|
913 |
|
|
IB_SRES_CPU : in ib_sres_type; -- ibus response (CPU registers)
|
914 |
|
|
IB_SRES_EXT : in ib_sres_type; -- ibus response (external devices)
|
915 |
|
|
DM_STAT_VM : out dm_stat_vm_type -- debug and monitor status
|
916 |
|
|
);
|
917 |
|
|
end component;
|
918 |
|
|
|
919 |
|
|
component pdp11_dpath is -- CPU datapath
|
920 |
|
|
port (
|
921 |
|
|
CLK : in slbit; -- clock
|
922 |
30 |
wfjm |
CRESET : in slbit; -- cpu reset
|
923 |
2 |
wfjm |
CNTL : in dpath_cntl_type; -- control interface
|
924 |
|
|
STAT : out dpath_stat_type; -- status interface
|
925 |
|
|
CP_DIN : in slv16; -- console port data in
|
926 |
|
|
CP_DOUT : out slv16; -- console port data out
|
927 |
|
|
PSWOUT : out psw_type; -- current psw
|
928 |
|
|
PCOUT : out slv16; -- current pc
|
929 |
|
|
IREG : out slv16; -- ireg out
|
930 |
|
|
VM_ADDR : out slv16; -- virt. memory address
|
931 |
|
|
VM_DOUT : in slv16; -- virt. memory data out
|
932 |
|
|
VM_DIN : out slv16; -- virt. memory data in
|
933 |
|
|
IB_MREQ : in ib_mreq_type; -- ibus request
|
934 |
|
|
IB_SRES : out ib_sres_type; -- ibus response
|
935 |
30 |
wfjm |
DM_STAT_DP : out dm_stat_dp_type -- debug and monitor status - dpath
|
936 |
2 |
wfjm |
);
|
937 |
|
|
end component;
|
938 |
|
|
|
939 |
|
|
component pdp11_decode is -- instruction decoder
|
940 |
|
|
port (
|
941 |
|
|
IREG : in slv16; -- input instruction word
|
942 |
|
|
STAT : out decode_stat_type -- status output
|
943 |
|
|
);
|
944 |
|
|
end component;
|
945 |
|
|
|
946 |
|
|
component pdp11_sequencer is -- cpu sequencer
|
947 |
|
|
port (
|
948 |
|
|
CLK : in slbit; -- clock
|
949 |
30 |
wfjm |
GRESET : in slbit; -- general reset
|
950 |
2 |
wfjm |
PSW : in psw_type; -- processor status
|
951 |
|
|
PC : in slv16; -- program counter
|
952 |
|
|
IREG : in slv16; -- IREG
|
953 |
|
|
ID_STAT : in decode_stat_type; -- instr. decoder status
|
954 |
|
|
DP_STAT : in dpath_stat_type; -- data path status
|
955 |
|
|
CP_CNTL : in cp_cntl_type; -- console port control
|
956 |
|
|
VM_STAT : in vm_stat_type; -- virtual memory status port
|
957 |
|
|
INT_PRI : in slv3; -- interrupt priority
|
958 |
|
|
INT_VECT : in slv9_2; -- interrupt vector
|
959 |
30 |
wfjm |
INT_ACK : out slbit; -- interrupt acknowledge
|
960 |
|
|
CRESET : out slbit; -- cpu reset
|
961 |
|
|
BRESET : out slbit; -- bus reset
|
962 |
2 |
wfjm |
MMU_MONI : out mmu_moni_type; -- mmu monitor port
|
963 |
|
|
DP_CNTL : out dpath_cntl_type; -- data path control
|
964 |
|
|
VM_CNTL : out vm_cntl_type; -- virtual memory control port
|
965 |
|
|
CP_STAT : out cp_stat_type; -- console port status
|
966 |
30 |
wfjm |
ESUSP_O : out slbit; -- external suspend output
|
967 |
|
|
ESUSP_I : in slbit; -- external suspend input
|
968 |
|
|
ITIMER : out slbit; -- instruction timer
|
969 |
|
|
EBREAK : in slbit; -- execution break
|
970 |
|
|
DBREAK : in slbit; -- data break
|
971 |
2 |
wfjm |
IB_MREQ : in ib_mreq_type; -- ibus request
|
972 |
|
|
IB_SRES : out ib_sres_type -- ibus response
|
973 |
|
|
);
|
974 |
|
|
end component;
|
975 |
|
|
|
976 |
|
|
component pdp11_irq is -- interrupt requester
|
977 |
|
|
port (
|
978 |
|
|
CLK : in slbit; -- clock
|
979 |
30 |
wfjm |
BRESET : in slbit; -- bus reset
|
980 |
2 |
wfjm |
INT_ACK : in slbit; -- interrupt acknowledge from CPU
|
981 |
|
|
EI_PRI : in slv3; -- external interrupt priority
|
982 |
|
|
EI_VECT : in slv9_2; -- external interrupt vector
|
983 |
|
|
EI_ACKM : out slbit; -- external interrupt acknowledge
|
984 |
|
|
PRI : out slv3; -- interrupt priority
|
985 |
|
|
VECT : out slv9_2; -- interrupt vector
|
986 |
|
|
IB_MREQ : in ib_mreq_type; -- ibus request
|
987 |
|
|
IB_SRES : out ib_sres_type -- ibus response
|
988 |
|
|
);
|
989 |
|
|
end component;
|
990 |
|
|
|
991 |
|
|
component pdp11_ubmap is -- 11/70 unibus mapper
|
992 |
|
|
port (
|
993 |
|
|
CLK : in slbit; -- clock
|
994 |
|
|
MREQ : in slbit; -- request mapping
|
995 |
|
|
ADDR_UB : in slv18_1; -- UNIBUS address (in)
|
996 |
|
|
ADDR_PM : out slv22_1; -- physical memory address (out)
|
997 |
|
|
IB_MREQ : in ib_mreq_type; -- ibus request
|
998 |
|
|
IB_SRES : out ib_sres_type -- ibus response
|
999 |
|
|
);
|
1000 |
|
|
end component;
|
1001 |
|
|
|
1002 |
30 |
wfjm |
component pdp11_reg70 is -- 11/70 memory system registers
|
1003 |
2 |
wfjm |
port (
|
1004 |
|
|
CLK : in slbit; -- clock
|
1005 |
30 |
wfjm |
CRESET : in slbit; -- cpu reset
|
1006 |
2 |
wfjm |
IB_MREQ : in ib_mreq_type; -- ibus request
|
1007 |
|
|
IB_SRES : out ib_sres_type -- ibus response
|
1008 |
|
|
);
|
1009 |
|
|
end component;
|
1010 |
|
|
|
1011 |
|
|
component pdp11_mem70 is -- 11/70 memory system registers
|
1012 |
|
|
port (
|
1013 |
|
|
CLK : in slbit; -- clock
|
1014 |
30 |
wfjm |
CRESET : in slbit; -- cpu reset
|
1015 |
2 |
wfjm |
HM_ENA : in slbit; -- hit/miss enable
|
1016 |
|
|
HM_VAL : in slbit; -- hit/miss value
|
1017 |
|
|
CACHE_FMISS : out slbit; -- cache force miss
|
1018 |
|
|
IB_MREQ : in ib_mreq_type; -- ibus request
|
1019 |
|
|
IB_SRES : out ib_sres_type -- ibus response
|
1020 |
|
|
);
|
1021 |
|
|
end component;
|
1022 |
|
|
|
1023 |
|
|
component pdp11_cache is -- cache
|
1024 |
|
|
port (
|
1025 |
|
|
CLK : in slbit; -- clock
|
1026 |
30 |
wfjm |
GRESET : in slbit; -- general reset
|
1027 |
2 |
wfjm |
EM_MREQ : in em_mreq_type; -- em request
|
1028 |
|
|
EM_SRES : out em_sres_type; -- em response
|
1029 |
|
|
FMISS : in slbit; -- force miss
|
1030 |
|
|
CHIT : out slbit; -- cache hit flag
|
1031 |
|
|
MEM_REQ : out slbit; -- memory: request
|
1032 |
|
|
MEM_WE : out slbit; -- memory: write enable
|
1033 |
|
|
MEM_BUSY : in slbit; -- memory: controller busy
|
1034 |
|
|
MEM_ACK_R : in slbit; -- memory: acknowledge read
|
1035 |
|
|
MEM_ADDR : out slv20; -- memory: address
|
1036 |
|
|
MEM_BE : out slv4; -- memory: byte enable
|
1037 |
|
|
MEM_DI : out slv32; -- memory: data in (memory view)
|
1038 |
|
|
MEM_DO : in slv32 -- memory: data out (memory view)
|
1039 |
|
|
);
|
1040 |
|
|
end component;
|
1041 |
|
|
|
1042 |
|
|
component pdp11_core is -- full processor core
|
1043 |
|
|
port (
|
1044 |
|
|
CLK : in slbit; -- clock
|
1045 |
|
|
RESET : in slbit; -- reset
|
1046 |
|
|
CP_CNTL : in cp_cntl_type; -- console control port
|
1047 |
|
|
CP_ADDR : in cp_addr_type; -- console address port
|
1048 |
|
|
CP_DIN : in slv16; -- console data in
|
1049 |
|
|
CP_STAT : out cp_stat_type; -- console status port
|
1050 |
|
|
CP_DOUT : out slv16; -- console data out
|
1051 |
30 |
wfjm |
ESUSP_O : out slbit; -- external suspend output
|
1052 |
|
|
ESUSP_I : in slbit; -- external suspend input
|
1053 |
|
|
ITIMER : out slbit; -- instruction timer
|
1054 |
|
|
EBREAK : in slbit; -- execution break
|
1055 |
|
|
DBREAK : in slbit; -- data break
|
1056 |
2 |
wfjm |
EI_PRI : in slv3; -- external interrupt priority
|
1057 |
|
|
EI_VECT : in slv9_2; -- external interrupt vector
|
1058 |
|
|
EI_ACKM : out slbit; -- external interrupt acknowledge
|
1059 |
|
|
EM_MREQ : out em_mreq_type; -- external memory: request
|
1060 |
|
|
EM_SRES : in em_sres_type; -- external memory: response
|
1061 |
30 |
wfjm |
CRESET : out slbit; -- cpu reset
|
1062 |
|
|
BRESET : out slbit; -- bus reset
|
1063 |
2 |
wfjm |
IB_MREQ_M : out ib_mreq_type; -- ibus master request (master)
|
1064 |
|
|
IB_SRES_M : in ib_sres_type; -- ibus slave response (master)
|
1065 |
|
|
DM_STAT_DP : out dm_stat_dp_type; -- debug and monitor status - dpath
|
1066 |
|
|
DM_STAT_VM : out dm_stat_vm_type; -- debug and monitor status - vmbox
|
1067 |
|
|
DM_STAT_CO : out dm_stat_co_type -- debug and monitor status - core
|
1068 |
|
|
);
|
1069 |
|
|
end component;
|
1070 |
|
|
|
1071 |
|
|
component pdp11_tmu is -- trace and monitor unit
|
1072 |
|
|
port (
|
1073 |
|
|
CLK : in slbit; -- clock
|
1074 |
|
|
ENA : in slbit := '0'; -- enable trace output
|
1075 |
30 |
wfjm |
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath
|
1076 |
|
|
DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox
|
1077 |
|
|
DM_STAT_CO : in dm_stat_co_type; -- debug and monitor status - core
|
1078 |
|
|
DM_STAT_SY : in dm_stat_sy_type -- debug and monitor status - system
|
1079 |
2 |
wfjm |
);
|
1080 |
|
|
end component;
|
1081 |
|
|
|
1082 |
|
|
component pdp11_tmu_sb is -- trace and mon. unit; simbus wrapper
|
1083 |
|
|
generic (
|
1084 |
|
|
ENAPIN : integer := 13); -- SB_CNTL signal to use for enable
|
1085 |
|
|
port (
|
1086 |
|
|
CLK : in slbit; -- clock
|
1087 |
30 |
wfjm |
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath
|
1088 |
|
|
DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox
|
1089 |
|
|
DM_STAT_CO : in dm_stat_co_type; -- debug and monitor status - core
|
1090 |
|
|
DM_STAT_SY : in dm_stat_sy_type -- debug and monitor status - system
|
1091 |
2 |
wfjm |
);
|
1092 |
|
|
end component;
|
1093 |
|
|
|
1094 |
|
|
component pdp11_du_drv is -- display unit low level driver
|
1095 |
|
|
generic (
|
1096 |
|
|
CDWIDTH : positive := 3); -- clock divider width
|
1097 |
|
|
port (
|
1098 |
|
|
CLK : in slbit; -- clock
|
1099 |
30 |
wfjm |
GRESET : in slbit; -- general reset
|
1100 |
2 |
wfjm |
ROW0 : in slv22; -- led row 0 (22 leds, top)
|
1101 |
|
|
ROW1 : in slv16; -- led row 1 (16 leds)
|
1102 |
|
|
ROW2 : in slv16; -- led row 2 (16 leds)
|
1103 |
|
|
ROW3 : in slv10; -- led row 3 (10 leds, bottom)
|
1104 |
|
|
SWOPT : out slv8; -- option pattern from du
|
1105 |
|
|
SWOPT_RDY : out slbit; -- marks update of swopt
|
1106 |
8 |
wfjm |
DU_SCLK : out slbit; -- DU: sclk
|
1107 |
|
|
DU_SS_N : out slbit; -- DU: ss_n
|
1108 |
2 |
wfjm |
DU_MOSI : out slbit; -- DU: mosi (master out, slave in)
|
1109 |
|
|
DU_MISO : in slbit -- DU: miso (master in, slave out)
|
1110 |
|
|
);
|
1111 |
|
|
end component;
|
1112 |
|
|
|
1113 |
|
|
component pdp11_bram is -- BRAM based ext. memory dummy
|
1114 |
|
|
generic (
|
1115 |
|
|
AWIDTH : positive := 14); -- address width
|
1116 |
|
|
port (
|
1117 |
|
|
CLK : in slbit; -- clock
|
1118 |
30 |
wfjm |
GRESET : in slbit; -- general reset
|
1119 |
2 |
wfjm |
EM_MREQ : in em_mreq_type; -- em request
|
1120 |
|
|
EM_SRES : out em_sres_type -- em response
|
1121 |
|
|
);
|
1122 |
|
|
end component;
|
1123 |
|
|
|
1124 |
29 |
wfjm |
component pdp11_bram_memctl is -- BRAM based memctl
|
1125 |
|
|
generic (
|
1126 |
|
|
MAWIDTH : positive := 4; -- mux address width
|
1127 |
|
|
NBLOCK : positive := 11); -- write delay in clock cycles
|
1128 |
|
|
port (
|
1129 |
|
|
CLK : in slbit; -- clock
|
1130 |
|
|
RESET : in slbit; -- reset
|
1131 |
|
|
REQ : in slbit; -- request
|
1132 |
|
|
WE : in slbit; -- write enable
|
1133 |
|
|
BUSY : out slbit; -- controller busy
|
1134 |
|
|
ACK_R : out slbit; -- acknowledge read
|
1135 |
|
|
ACK_W : out slbit; -- acknowledge write
|
1136 |
|
|
ACT_R : out slbit; -- signal active read
|
1137 |
|
|
ACT_W : out slbit; -- signal active write
|
1138 |
|
|
ADDR : in slv20; -- address
|
1139 |
|
|
BE : in slv4; -- byte enable
|
1140 |
|
|
DI : in slv32; -- data in (memory view)
|
1141 |
|
|
DO : out slv32 -- data out (memory view)
|
1142 |
|
|
);
|
1143 |
|
|
end component;
|
1144 |
|
|
|
1145 |
|
|
component pdp11_statleds is -- status leds
|
1146 |
|
|
port (
|
1147 |
|
|
MEM_ACT_R : in slbit; -- memory active read
|
1148 |
|
|
MEM_ACT_W : in slbit; -- memory active write
|
1149 |
|
|
CP_STAT : in cp_stat_type; -- console port status
|
1150 |
30 |
wfjm |
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath
|
1151 |
29 |
wfjm |
STATLEDS : out slv8 -- 8 bit CPU status
|
1152 |
|
|
);
|
1153 |
|
|
end component;
|
1154 |
|
|
|
1155 |
|
|
component pdp11_ledmux is -- hio led mux
|
1156 |
|
|
generic (
|
1157 |
|
|
LWIDTH : positive := 8); -- led width
|
1158 |
|
|
port (
|
1159 |
|
|
SEL : in slbit; -- select (0=stat;1=dr)
|
1160 |
|
|
STATLEDS : in slv8; -- 8 bit CPU status
|
1161 |
30 |
wfjm |
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath
|
1162 |
29 |
wfjm |
LED : out slv(LWIDTH-1 downto 0) -- hio leds
|
1163 |
|
|
);
|
1164 |
|
|
end component;
|
1165 |
|
|
|
1166 |
|
|
component pdp11_dspmux is -- hio dsp mux
|
1167 |
|
|
generic (
|
1168 |
|
|
DCWIDTH : positive := 2); -- digit counter width (2 or 3)
|
1169 |
|
|
port (
|
1170 |
|
|
SEL : in slv2; -- select
|
1171 |
|
|
ABCLKDIV : in slv16; -- serport clock divider
|
1172 |
30 |
wfjm |
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath
|
1173 |
29 |
wfjm |
DISPREG : in slv16; -- display register
|
1174 |
|
|
DSP_DAT : out slv(4*(2**DCWIDTH)-1 downto 0) -- display data
|
1175 |
|
|
);
|
1176 |
|
|
end component;
|
1177 |
|
|
|
1178 |
9 |
wfjm |
component pdp11_core_rbus is -- core to rbus interface
|
1179 |
2 |
wfjm |
generic (
|
1180 |
28 |
wfjm |
RB_ADDR_CORE : slv16 := slv(to_unsigned(16#0000#,16));
|
1181 |
|
|
RB_ADDR_IBUS : slv16 := slv(to_unsigned(16#4000#,16)));
|
1182 |
2 |
wfjm |
port (
|
1183 |
|
|
CLK : in slbit; -- clock
|
1184 |
|
|
RESET : in slbit; -- reset
|
1185 |
|
|
RB_MREQ : in rb_mreq_type; -- rbus: request
|
1186 |
|
|
RB_SRES : out rb_sres_type; -- rbus: response
|
1187 |
27 |
wfjm |
RB_STAT : out slv4; -- rbus: status flags
|
1188 |
8 |
wfjm |
RB_LAM : out slbit; -- remote attention
|
1189 |
30 |
wfjm |
GRESET : out slbit; -- general reset
|
1190 |
2 |
wfjm |
CP_CNTL : out cp_cntl_type; -- console control port
|
1191 |
|
|
CP_ADDR : out cp_addr_type; -- console address port
|
1192 |
|
|
CP_DIN : out slv16; -- console data in
|
1193 |
|
|
CP_STAT : in cp_stat_type; -- console status port
|
1194 |
|
|
CP_DOUT : in slv16 -- console data out
|
1195 |
|
|
);
|
1196 |
|
|
end component;
|
1197 |
|
|
|
1198 |
30 |
wfjm |
component pdp11_sys70 is -- 11/70 system 1 core +rbus,debug,cache
|
1199 |
|
|
port (
|
1200 |
|
|
CLK : in slbit; -- clock
|
1201 |
|
|
RESET : in slbit; -- reset
|
1202 |
|
|
RB_MREQ : in rb_mreq_type; -- rbus request (slave)
|
1203 |
|
|
RB_SRES : out rb_sres_type; -- rbus response
|
1204 |
|
|
RB_STAT : out slv4; -- rbus status flags
|
1205 |
|
|
RB_LAM_CPU : out slbit; -- rbus lam (cpu)
|
1206 |
|
|
GRESET : out slbit; -- general reset (from rbus)
|
1207 |
|
|
CRESET : out slbit; -- cpu reset (from cp)
|
1208 |
|
|
BRESET : out slbit; -- bus reset (from cp or cpu)
|
1209 |
|
|
CP_STAT : out cp_stat_type; -- console port status
|
1210 |
|
|
EI_PRI : in slv3; -- external interrupt priority
|
1211 |
|
|
EI_VECT : in slv9_2; -- external interrupt vector
|
1212 |
|
|
EI_ACKM : out slbit; -- external interrupt acknowledge
|
1213 |
|
|
ITIMER : out slbit; -- instruction timer
|
1214 |
|
|
IB_MREQ : out ib_mreq_type; -- ibus request (master)
|
1215 |
|
|
IB_SRES : in ib_sres_type; -- ibus response (from IO system)
|
1216 |
|
|
MEM_REQ : out slbit; -- memory: request
|
1217 |
|
|
MEM_WE : out slbit; -- memory: write enable
|
1218 |
|
|
MEM_BUSY : in slbit; -- memory: controller busy
|
1219 |
|
|
MEM_ACK_R : in slbit; -- memory: acknowledge read
|
1220 |
|
|
MEM_ADDR : out slv20; -- memory: address
|
1221 |
|
|
MEM_BE : out slv4; -- memory: byte enable
|
1222 |
|
|
MEM_DI : out slv32; -- memory: data in (memory view)
|
1223 |
|
|
MEM_DO : in slv32; -- memory: data out (memory view)
|
1224 |
|
|
DM_STAT_DP : out dm_stat_dp_type -- debug and monitor status - dpath
|
1225 |
|
|
);
|
1226 |
|
|
end component;
|
1227 |
|
|
|
1228 |
|
|
component pdp11_hio70 is -- hio led and dsp for sys70
|
1229 |
|
|
generic (
|
1230 |
|
|
LWIDTH : positive := 8; -- led width
|
1231 |
|
|
DCWIDTH : positive := 2); -- digit counter width (2 or 3)
|
1232 |
|
|
port (
|
1233 |
|
|
SEL_LED : in slbit; -- led select (0=stat;1=dr)
|
1234 |
|
|
SEL_DSP : in slv2; -- dsp select
|
1235 |
|
|
MEM_ACT_R : in slbit; -- memory active read
|
1236 |
|
|
MEM_ACT_W : in slbit; -- memory active write
|
1237 |
|
|
CP_STAT : in cp_stat_type; -- console port status
|
1238 |
|
|
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status
|
1239 |
|
|
ABCLKDIV : in slv16; -- serport clock divider
|
1240 |
|
|
DISPREG : in slv16; -- display register
|
1241 |
|
|
LED : out slv(LWIDTH-1 downto 0); -- hio leds
|
1242 |
|
|
DSP_DAT : out slv(4*(2**DCWIDTH)-1 downto 0) -- display data
|
1243 |
|
|
);
|
1244 |
|
|
end component;
|
1245 |
|
|
|
1246 |
2 |
wfjm |
-- ----- move later to pdp11_conf --------------------------------------------
|
1247 |
|
|
|
1248 |
|
|
constant conf_vect_pirq : integer := 8#240#;
|
1249 |
|
|
constant conf_pri_pirq_1 : integer := 1;
|
1250 |
|
|
constant conf_pri_pirq_2 : integer := 2;
|
1251 |
|
|
constant conf_pri_pirq_3 : integer := 3;
|
1252 |
|
|
constant conf_pri_pirq_4 : integer := 4;
|
1253 |
|
|
constant conf_pri_pirq_5 : integer := 5;
|
1254 |
|
|
constant conf_pri_pirq_6 : integer := 6;
|
1255 |
|
|
constant conf_pri_pirq_7 : integer := 7;
|
1256 |
|
|
|
1257 |
|
|
end package pdp11;
|