1 |
30 |
wfjm |
-- $Id: pdp11_core.vhd 677 2015-05-09 21:52:32Z mueller $
|
2 |
2 |
wfjm |
--
|
3 |
30 |
wfjm |
-- Copyright 2006-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
4 |
2 |
wfjm |
--
|
5 |
|
|
-- This program is free software; you may redistribute and/or modify it under
|
6 |
|
|
-- the terms of the GNU General Public License as published by the Free
|
7 |
|
|
-- Software Foundation, either version 2, or at your option any later version.
|
8 |
|
|
--
|
9 |
|
|
-- This program is distributed in the hope that it will be useful, but
|
10 |
|
|
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
|
11 |
|
|
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
12 |
|
|
-- for complete details.
|
13 |
|
|
--
|
14 |
|
|
------------------------------------------------------------------------------
|
15 |
|
|
-- Module Name: pdp11_core - syn
|
16 |
|
|
-- Description: pdp11: full processor core
|
17 |
|
|
--
|
18 |
|
|
-- Dependencies: pdp11_vmbox
|
19 |
|
|
-- pdp11_dpath
|
20 |
|
|
-- pdp11_decode
|
21 |
|
|
-- pdp11_sequencer
|
22 |
|
|
-- pdp11_irq
|
23 |
30 |
wfjm |
-- pdp11_reg70
|
24 |
2 |
wfjm |
-- ibus/ib_sres_or_4
|
25 |
|
|
--
|
26 |
9 |
wfjm |
-- Test bench: tb/tb_pdp11core
|
27 |
|
|
-- tb/tb_rlink_tba_pdp11core
|
28 |
2 |
wfjm |
--
|
29 |
|
|
-- Target Devices: generic
|
30 |
29 |
wfjm |
-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
|
31 |
2 |
wfjm |
-- Revision History:
|
32 |
|
|
-- Date Rev Version Comment
|
33 |
30 |
wfjm |
-- 2015-05-09 679 1.4 start/stop/suspend overhaul; reset overhaul
|
34 |
|
|
-- 2015-04-30 670 1.3.2 rename pdp11_sys70 -> pdp11_reg70
|
35 |
13 |
wfjm |
-- 2011-11-18 427 1.3.1 now numeric_std clean
|
36 |
2 |
wfjm |
-- 2010-06-13 305 1.3 add CP_ADDR in port; drop R_CPDIN, R_CPOUT; _vmbox
|
37 |
|
|
-- CP_ADDR now from in port; dpath CP_DIN now from in
|
38 |
|
|
-- port; out port CP_DOUT now from _dpath
|
39 |
|
|
-- 2009-05-30 220 1.2.5 final removal of snoopers (were already commented)
|
40 |
|
|
-- 2008-08-22 161 1.2.4 rename pdp11_ibres_ -> ib_sres_
|
41 |
|
|
-- 2008-04-25 138 1.2.3 BRESET: add for _vmbox, use for _irq
|
42 |
|
|
-- 2008-04-19 137 1.2.2 add DM_STAT_(DP|VM|CO) port; added pdp11_sys70
|
43 |
|
|
-- 2008-03-02 121 1.2.1 remove snoopers
|
44 |
|
|
-- 2008-02-17 117 1.2 add em_(mreq|sres) interface for memory
|
45 |
|
|
-- 2008-01-20 112 1.1.3 add BRESET port (intbus reset), rename P->BRESET
|
46 |
|
|
-- 2008-01-06 111 1.1.2 rename signal EI_ACK->EI_ACKM (master ack)
|
47 |
|
|
-- 2008-01-01 109 1.1.1 _vmbox w/ IB_SRES_(CPU|EXT)
|
48 |
|
|
-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now; remove DMA port
|
49 |
|
|
-- 2007-07-15 66 1.0.3 rename pdp11_top -> pdp11_core
|
50 |
|
|
-- 2007-07-02 63 1.0.2 reordered ports on pdp11_top (by function, not i/o)
|
51 |
|
|
-- 2007-06-14 56 1.0.1 Use slvtypes.all
|
52 |
|
|
-- 2007-05-12 26 1.0 Initial version
|
53 |
|
|
------------------------------------------------------------------------------
|
54 |
|
|
|
55 |
|
|
library ieee;
|
56 |
|
|
use ieee.std_logic_1164.all;
|
57 |
13 |
wfjm |
use ieee.numeric_std.all;
|
58 |
2 |
wfjm |
|
59 |
|
|
use work.slvtypes.all;
|
60 |
|
|
use work.iblib.all;
|
61 |
|
|
use work.pdp11.all;
|
62 |
|
|
|
63 |
|
|
-- ----------------------------------------------------------------------------
|
64 |
|
|
|
65 |
|
|
entity pdp11_core is -- full processor core
|
66 |
|
|
port (
|
67 |
|
|
CLK : in slbit; -- clock
|
68 |
|
|
RESET : in slbit; -- reset
|
69 |
|
|
CP_CNTL : in cp_cntl_type; -- console control port
|
70 |
|
|
CP_ADDR : in cp_addr_type; -- console address port
|
71 |
|
|
CP_DIN : in slv16; -- console data in
|
72 |
|
|
CP_STAT : out cp_stat_type; -- console status port
|
73 |
|
|
CP_DOUT : out slv16; -- console data out
|
74 |
30 |
wfjm |
ESUSP_O : out slbit; -- external suspend output
|
75 |
|
|
ESUSP_I : in slbit; -- external suspend input
|
76 |
|
|
ITIMER : out slbit; -- instruction timer
|
77 |
|
|
EBREAK : in slbit; -- execution break
|
78 |
|
|
DBREAK : in slbit; -- data break
|
79 |
2 |
wfjm |
EI_PRI : in slv3; -- external interrupt priority
|
80 |
|
|
EI_VECT : in slv9_2; -- external interrupt vector
|
81 |
|
|
EI_ACKM : out slbit; -- external interrupt acknowledge
|
82 |
|
|
EM_MREQ : out em_mreq_type; -- external memory: request
|
83 |
|
|
EM_SRES : in em_sres_type; -- external memory: response
|
84 |
30 |
wfjm |
CRESET : out slbit; -- cpu reset
|
85 |
|
|
BRESET : out slbit; -- bus reset
|
86 |
|
|
IB_MREQ_M : out ib_mreq_type; -- ibus master request (master)
|
87 |
|
|
IB_SRES_M : in ib_sres_type; -- ibus slave response (master)
|
88 |
2 |
wfjm |
DM_STAT_DP : out dm_stat_dp_type; -- debug and monitor status - dpath
|
89 |
|
|
DM_STAT_VM : out dm_stat_vm_type; -- debug and monitor status - vmbox
|
90 |
|
|
DM_STAT_CO : out dm_stat_co_type -- debug and monitor status - core
|
91 |
|
|
);
|
92 |
|
|
end pdp11_core;
|
93 |
|
|
|
94 |
|
|
architecture syn of pdp11_core is
|
95 |
|
|
|
96 |
|
|
signal GRESET : slbit := '0';
|
97 |
30 |
wfjm |
signal CRESET_L : slbit := '0';
|
98 |
2 |
wfjm |
signal BRESET_L : slbit := '0';
|
99 |
|
|
signal VM_CNTL : vm_cntl_type := vm_cntl_init;
|
100 |
|
|
signal VM_STAT : vm_stat_type := vm_stat_init;
|
101 |
|
|
signal MMU_MONI : mmu_moni_type := mmu_moni_init;
|
102 |
|
|
signal DP_CNTL : dpath_cntl_type := dpath_cntl_init;
|
103 |
|
|
signal DP_STAT : dpath_stat_type := dpath_stat_init;
|
104 |
|
|
signal DP_PSW : psw_type := psw_init;
|
105 |
|
|
signal DP_PC : slv16 := (others=>'0');
|
106 |
|
|
signal DP_IREG : slv16 := (others=>'0');
|
107 |
|
|
signal VM_DIN : slv16 := (others=>'0');
|
108 |
|
|
signal VM_ADDR : slv16 := (others=>'0');
|
109 |
|
|
signal VM_DOUT : slv16 := (others=>'0');
|
110 |
|
|
signal ID_STAT : decode_stat_type := decode_stat_init;
|
111 |
|
|
signal INT_PRI : slv3 := (others=>'0');
|
112 |
|
|
signal INT_VECT : slv9_2 := (others=>'0');
|
113 |
|
|
signal CP_STAT_L : cp_stat_type := cp_stat_init;
|
114 |
|
|
signal INT_ACK : slbit := '0';
|
115 |
|
|
|
116 |
|
|
signal IB_SRES_DP : ib_sres_type := ib_sres_init;
|
117 |
|
|
signal IB_SRES_SEQ : ib_sres_type := ib_sres_init;
|
118 |
|
|
signal IB_SRES_IRQ : ib_sres_type := ib_sres_init;
|
119 |
|
|
signal IB_SRES_SYS : ib_sres_type := ib_sres_init;
|
120 |
|
|
|
121 |
|
|
signal IB_MREQ : ib_mreq_type := ib_mreq_init; -- ibus request (local)
|
122 |
|
|
signal IB_SRES : ib_sres_type := ib_sres_init; -- ibus response (local)
|
123 |
|
|
|
124 |
|
|
begin
|
125 |
|
|
|
126 |
|
|
GRESET <= RESET;
|
127 |
|
|
|
128 |
|
|
VMBOX : pdp11_vmbox
|
129 |
|
|
port map (
|
130 |
|
|
CLK => CLK,
|
131 |
|
|
GRESET => GRESET,
|
132 |
30 |
wfjm |
CRESET => CRESET_L,
|
133 |
2 |
wfjm |
BRESET => BRESET_L,
|
134 |
|
|
CP_ADDR => CP_ADDR,
|
135 |
|
|
VM_CNTL => VM_CNTL,
|
136 |
|
|
VM_ADDR => VM_ADDR,
|
137 |
|
|
VM_DIN => VM_DIN,
|
138 |
|
|
VM_STAT => VM_STAT,
|
139 |
|
|
VM_DOUT => VM_DOUT,
|
140 |
|
|
EM_MREQ => EM_MREQ,
|
141 |
|
|
EM_SRES => EM_SRES,
|
142 |
|
|
MMU_MONI => MMU_MONI,
|
143 |
|
|
IB_MREQ_M => IB_MREQ,
|
144 |
|
|
IB_SRES_CPU => IB_SRES,
|
145 |
|
|
IB_SRES_EXT => IB_SRES_M,
|
146 |
|
|
DM_STAT_VM => DM_STAT_VM
|
147 |
|
|
);
|
148 |
|
|
|
149 |
|
|
DPATH : pdp11_dpath
|
150 |
|
|
port map (
|
151 |
|
|
CLK => CLK,
|
152 |
30 |
wfjm |
CRESET => CRESET_L,
|
153 |
2 |
wfjm |
CNTL => DP_CNTL,
|
154 |
|
|
STAT => DP_STAT,
|
155 |
|
|
CP_DIN => CP_DIN,
|
156 |
|
|
CP_DOUT => CP_DOUT,
|
157 |
|
|
PSWOUT => DP_PSW,
|
158 |
|
|
PCOUT => DP_PC,
|
159 |
|
|
IREG => DP_IREG,
|
160 |
|
|
VM_ADDR => VM_ADDR,
|
161 |
|
|
VM_DOUT => VM_DOUT,
|
162 |
|
|
VM_DIN => VM_DIN,
|
163 |
|
|
IB_MREQ => IB_MREQ,
|
164 |
|
|
IB_SRES => IB_SRES_DP,
|
165 |
|
|
DM_STAT_DP => DM_STAT_DP
|
166 |
|
|
);
|
167 |
|
|
|
168 |
|
|
IDEC : pdp11_decode
|
169 |
|
|
port map (
|
170 |
|
|
IREG => DP_IREG,
|
171 |
|
|
STAT => ID_STAT
|
172 |
|
|
);
|
173 |
|
|
|
174 |
|
|
SEQ : pdp11_sequencer
|
175 |
|
|
port map (
|
176 |
|
|
CLK => CLK,
|
177 |
|
|
GRESET => GRESET,
|
178 |
|
|
PSW => DP_PSW,
|
179 |
|
|
PC => DP_PC,
|
180 |
|
|
IREG => DP_IREG,
|
181 |
|
|
ID_STAT => ID_STAT,
|
182 |
|
|
DP_STAT => DP_STAT,
|
183 |
|
|
CP_CNTL => CP_CNTL,
|
184 |
|
|
VM_STAT => VM_STAT,
|
185 |
|
|
INT_PRI => INT_PRI,
|
186 |
|
|
INT_VECT => INT_VECT,
|
187 |
30 |
wfjm |
INT_ACK => INT_ACK,
|
188 |
|
|
CRESET => CRESET_L,
|
189 |
|
|
BRESET => BRESET_L,
|
190 |
2 |
wfjm |
MMU_MONI => MMU_MONI,
|
191 |
|
|
DP_CNTL => DP_CNTL,
|
192 |
|
|
VM_CNTL => VM_CNTL,
|
193 |
|
|
CP_STAT => CP_STAT_L,
|
194 |
30 |
wfjm |
ESUSP_O => ESUSP_O,
|
195 |
|
|
ESUSP_I => ESUSP_I,
|
196 |
|
|
ITIMER => ITIMER,
|
197 |
|
|
EBREAK => EBREAK,
|
198 |
|
|
DBREAK => DBREAK,
|
199 |
2 |
wfjm |
IB_MREQ => IB_MREQ,
|
200 |
|
|
IB_SRES => IB_SRES_SEQ
|
201 |
|
|
);
|
202 |
|
|
|
203 |
|
|
IRQ : pdp11_irq
|
204 |
|
|
port map (
|
205 |
|
|
CLK => CLK,
|
206 |
|
|
BRESET => BRESET_L,
|
207 |
|
|
INT_ACK => INT_ACK,
|
208 |
|
|
EI_PRI => EI_PRI,
|
209 |
|
|
EI_VECT => EI_VECT,
|
210 |
|
|
EI_ACKM => EI_ACKM,
|
211 |
|
|
PRI => INT_PRI,
|
212 |
|
|
VECT => INT_VECT,
|
213 |
|
|
IB_MREQ => IB_MREQ,
|
214 |
|
|
IB_SRES => IB_SRES_IRQ
|
215 |
|
|
);
|
216 |
|
|
|
217 |
30 |
wfjm |
REG70 : pdp11_reg70
|
218 |
2 |
wfjm |
port map (
|
219 |
|
|
CLK => CLK,
|
220 |
30 |
wfjm |
CRESET => CRESET_L,
|
221 |
2 |
wfjm |
IB_MREQ => IB_MREQ,
|
222 |
|
|
IB_SRES => IB_SRES_SYS
|
223 |
|
|
);
|
224 |
|
|
|
225 |
|
|
IB_SRES_OR : ib_sres_or_4
|
226 |
|
|
port map (
|
227 |
|
|
IB_SRES_1 => IB_SRES_DP,
|
228 |
|
|
IB_SRES_2 => IB_SRES_SEQ,
|
229 |
|
|
IB_SRES_3 => IB_SRES_IRQ,
|
230 |
|
|
IB_SRES_4 => IB_SRES_SYS,
|
231 |
|
|
IB_SRES_OR => IB_SRES
|
232 |
|
|
);
|
233 |
|
|
|
234 |
|
|
IB_MREQ_M <= IB_MREQ;
|
235 |
|
|
|
236 |
|
|
CP_STAT <= CP_STAT_L;
|
237 |
|
|
|
238 |
30 |
wfjm |
CRESET <= CRESET_L;
|
239 |
2 |
wfjm |
BRESET <= BRESET_L;
|
240 |
|
|
|
241 |
30 |
wfjm |
DM_STAT_CO.cpugo <= CP_STAT_L.cpugo;
|
242 |
|
|
DM_STAT_CO.cpususp <= CP_STAT_L.cpususp;
|
243 |
|
|
DM_STAT_CO.suspint <= CP_STAT_L.suspint;
|
244 |
|
|
DM_STAT_CO.suspext <= CP_STAT_L.suspext;
|
245 |
2 |
wfjm |
|
246 |
|
|
end syn;
|
247 |
|
|
|