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-- $Id: tb_pdp11core.vhd 675 2015-05-08 21:05:08Z mueller $
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--
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-- Copyright 2006-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: tb_pdp11core - sim
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-- Description: Test bench for pdp11_core
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--
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-- Dependencies: simlib/simclk
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-- tbd_pdp11core [UUT]
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-- pdp11_intmap
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--
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-- To test: pdp11_core
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--
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-- Target Devices: generic
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-- Tool versions: ghdl 0.18-0.31; ISim 14.7
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--
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-- Verified (with tb_pdp11core_stim.dat):
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-- Date Rev Code ghdl ise Target Comment
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-- 2014-12-23 620 - 0.31 14.7 131013 - u:ok
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-- 2010-12-30 351 - 0.29 - - u:ok
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-- 2010-12-30 351 _ssim 0.29 12.1 M53d xc3s1000 u:ok
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-- 2010-06-20 308 - 0.29 - - u:ok
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-- 2009-11-22 252 - 0.26 - - u:ok
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-- 2007-12-30 107 - 0.25 - - u:ok
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-- 2007-10-26 92 _tsim 0.26 8.1.03 I27 xc3s1000 c:fail -> blog_ghdl
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-- 2007-10-26 92 _tsim 0.26 9.2.02 J39 xc3s1000 d:ok (full tsim!)
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-- 2007-10-26 92 _tsim 0.26 9.1 J30 xc3s1000 d:ok (full tsim!)
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-- 2007-10-26 92 _tsim 0.26 8.2.03 I34 xc3s1000 d:ok (full tsim!)
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-- 2007-10-26 92 _fsim 0.26 8.2.03 I34 xc3s1000 d:ok
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-- 2007-10-26 92 _ssim 0.26 8.2.03 I34 xc3s1000 d:ok
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-- 2007-10-08 88 _ssim 0.18 8.2.03 I34 xc3s1000 d:ok
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-- 2007-10-08 88 _ssim 0.18 9.1 J30 xc3s1000 d:ok
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-- 2007-10-08 88 _ssim 0.18 9.2.02 J39 xc3s1000 d:ok
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-- 2007-10-07 88 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok
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-- 2007-10-07 88 _ssim 0.26 8.1 I24 xc3s1000 c:fail -> blog_webpack
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-- 2007-10-07 88 - 0.26 - - c:ok
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2015-05-08 675 1.5 start/stop/suspend overhaul
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-- 2014-12-26 621 1.4.1 adopt wmembe,ribr,wibr emulation to new 4k window
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-- 2011-12-23 444 1.4 use new simclk/simclkcnt
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-- 2011-11-18 427 1.3.2 now numeric_std clean
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-- 2011-01-02 352 1.3.1 rename .cpmon->.rlmon
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-- 2010-12-30 351 1.3 rename tb_pdp11_core -> tb_pdp11core
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-- 2010-06-20 308 1.2.2 add wibrb, ribr, wibr commands for ibr accesses
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-- 2010-06-20 307 1.2.1 add CP_ADDR_racc, CP_ADDR_be to tbd interface
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-- 2010-06-13 305 1.2 add CP_CNTL_rnum and CP_ADDR_...; emulate old
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-- 'sta' behaviour with new 'stapc' command; rename
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-- lal,lah -> wal,wah and implement locally; new
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-- output format with cpfunc name
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-- 2010-06-05 301 1.1.14 renamed .rpmon -> .rbmon
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-- 2010-04-24 281 1.1.13 use direct instatiation for tbd_
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-- 2009-11-28 253 1.1.12 add hack for ISim 11.3
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-- 2009-05-10 214 1.1.11 add .scntl command (set/clear SB_CNTL bits)
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-- 2008-08-29 163 1.1.10 allow, but ignore, the wtlam command
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-- 2008-05-03 143 1.1.9 rename _cpursta->_cpurust
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-- 2008-04-27 140 1.1.8 use cpursta interface, remove cpufail
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-- 2008-04-19 137 1.1.7 use SB_CLKCYCLE now
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-- 2008-03-24 129 1.1.6 CLK_CYCLE now 31 bits
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-- 2008-03-02 121 1.1.5 redo sta,cont,wtgo commands; sta,cont now wait for
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-- command completion, wtgo waits for CPU to halt.
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-- added .cerr,.merr directive, check cmd(m)err state
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-- added .sdef as ignored directive
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-- 2008-02-24 119 1.1.4 added lah,rps,wps command
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-- 2008-01-26 114 1.1.3 add handling of d=val,msk
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-- 2008-01-06 111 1.1.2 remove .eireq, EI's now handled in tbd_pdp11_core
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-- 2007-10-26 92 1.0.2 use DONE timestamp at end of execution
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-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
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-- 2007-09-02 79 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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use work.slvtypes.all;
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use work.simlib.all;
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use work.simbus.all;
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use work.pdp11_sim.all;
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use work.pdp11.all;
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entity tb_pdp11core is
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end tb_pdp11core;
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architecture sim of tb_pdp11core is
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signal CLK : slbit := '0';
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signal RESET : slbit := '0';
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signal UNUSEDSIGNAL : slbit := '0'; -- FIXME: hack to make ISim 11.3 happy
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signal CP_CNTL_req : slbit := '0';
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signal CP_CNTL_func : slv5 := (others=>'0');
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signal CP_CNTL_rnum : slv3 := (others=>'0');
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signal CP_ADDR_addr : slv22_1 := (others=>'0');
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signal CP_ADDR_racc : slbit := '0';
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signal CP_ADDR_be : slv2 := "11";
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signal CP_ADDR_ena_22bit : slbit := '0';
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signal CP_ADDR_ena_ubmap : slbit := '0';
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signal CP_DIN : slv16 := (others=>'0');
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signal CP_STAT_cmdbusy : slbit := '0';
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signal CP_STAT_cmdack : slbit := '0';
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signal CP_STAT_cmderr : slbit := '0';
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signal CP_STAT_cmdmerr : slbit := '0';
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signal CP_STAT_cpugo : slbit := '0';
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signal CP_STAT_cpustep : slbit := '0';
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signal CP_STAT_cpuwait : slbit := '0';
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signal CP_STAT_cpususp : slbit := '0';
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signal CP_STAT_cpurust : slv4 := (others=>'0');
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signal CP_STAT_suspint : slbit := '0';
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signal CP_STAT_suspext : slbit := '0';
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signal CP_DOUT : slv16 := (others=>'0');
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signal CLK_STOP : slbit := '0';
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signal CLK_CYCLE : integer := 0;
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signal R_CHKDAT : slv16 := (others=>'0');
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signal R_CHKMSK : slv16 := (others=>'0');
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signal R_CHKREQ : slbit := '0';
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signal R_WAITCMD : slbit := '0';
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signal R_WAITSTEP : slbit := '0';
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signal R_WAITGO : slbit := '0';
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signal R_WAITOK : slbit := '0';
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signal R_CP_STAT : cp_stat_type := cp_stat_init;
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signal R_CP_DOUT : slv16 := (others=>'0');
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begin
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CLKGEN : simclk
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generic map (
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PERIOD => clock_period,
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OFFSET => clock_offset)
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port map (
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CLK => CLK,
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CLK_STOP => CLK_STOP
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);
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CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
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UUT: entity work.tbd_pdp11core
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port map (
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CLK => CLK,
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RESET => RESET,
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CP_CNTL_req => CP_CNTL_req,
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CP_CNTL_func => CP_CNTL_func,
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CP_CNTL_rnum => CP_CNTL_rnum,
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CP_ADDR_addr => CP_ADDR_addr,
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CP_ADDR_racc => CP_ADDR_racc,
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CP_ADDR_be => CP_ADDR_be,
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CP_ADDR_ena_22bit => CP_ADDR_ena_22bit,
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CP_ADDR_ena_ubmap => CP_ADDR_ena_ubmap,
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CP_DIN => CP_DIN,
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CP_STAT_cmdbusy => CP_STAT_cmdbusy,
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CP_STAT_cmdack => CP_STAT_cmdack,
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CP_STAT_cmderr => CP_STAT_cmderr,
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CP_STAT_cmdmerr => CP_STAT_cmdmerr,
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CP_STAT_cpugo => CP_STAT_cpugo,
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CP_STAT_cpustep => CP_STAT_cpustep,
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CP_STAT_cpuwait => CP_STAT_cpuwait,
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CP_STAT_cpususp => CP_STAT_cpususp,
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CP_STAT_cpurust => CP_STAT_cpurust,
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CP_STAT_suspint => CP_STAT_suspint,
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CP_STAT_suspext => CP_STAT_suspext,
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CP_DOUT => CP_DOUT
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);
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proc_stim: process
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file ifile : text open read_mode is "tb_pdp11core_stim";
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variable iline : line;
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variable oline : line;
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variable idelta : integer := 0;
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variable idummy : integer := 0;
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variable dcycle : integer := 0;
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variable irqline : integer := 0;
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variable ireq : boolean := false;
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variable ifunc : slv5 := (others=>'0');
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variable irnum : slv3 := (others=>'0');
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variable idin : slv16 := (others=>'0');
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variable imsk : slv16 := (others=>'1');
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variable idin3 : slv3 := (others=>'0');
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variable ichk : boolean := false;
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variable idosta: slbit := '0';
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variable ok : boolean;
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variable dname : string(1 to 6) := (others=>' ');
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variable rind : integer := 0;
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variable nblk : integer := 0;
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variable xmicmd : string(1 to 3) := (others=>' ');
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variable iwtstp : boolean := false;
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variable iwtgo : boolean := false;
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variable icerr : integer := 0;
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variable imerr : integer := 0;
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variable to_cmd : integer := 50;
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variable to_stp : integer := 100;
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variable to_go : integer := 5000;
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variable ien : slbit := '0';
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variable ibit : integer := 0;
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variable imemi : boolean := false;
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variable iaddr : slv16 := (others=>'0');
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variable idoibr : boolean := false;
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214 |
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variable r_addr : slv22_1 := (others=>'0');
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variable r_ena_22bit : slbit := '0';
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variable r_ena_ubmap : slbit := '0';
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variable r_membe : slv2 := "11";
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variable r_membestick : slbit := '0';
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begin
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SB_CNTL <= (others=>'L');
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wait for clock_offset - setup_time;
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RESET <= '1';
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wait for clock_period;
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229 |
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RESET <= '0';
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wait for 9*clock_period;
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231 |
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232 |
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file_loop: while not endfile(ifile) loop
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233 |
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234 |
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-- this logic is a quick hack to implement the 'stapc' command
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if idosta = '0' then
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readline (ifile, iline);
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237 |
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238 |
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iwtstp := false;
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iwtgo := false;
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240 |
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241 |
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if nblk>0 and -- outstanding [rw]mi lines ?
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iline'length>=3 and -- and 3 leading blanks
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iline(iline'left to iline'left+2)=" " then
|
244 |
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nblk := nblk - 1; -- than fill [rw]mi command in again
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245 |
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iline(iline'left to iline'left+2) := xmicmd;
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end if;
|
247 |
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248 |
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readcomment(iline, ok);
|
249 |
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next file_loop when ok;
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250 |
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251 |
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readword(iline, dname, ok);
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252 |
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253 |
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else
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254 |
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idosta := '0';
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255 |
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dname := "sta ";
|
256 |
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ok := true;
|
257 |
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end if;
|
258 |
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|
259 |
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if ok then
|
260 |
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|
261 |
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case dname is
|
262 |
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when "rsp " => dname := "rr6 "; -- rsp -> rr6
|
263 |
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when "rpc " => dname := "rr7 "; -- rpc -> rr7
|
264 |
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when "wsp " => dname := "wr6 "; -- wsp -> wr6
|
265 |
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when "wpc " => dname := "wr7 "; -- wpc -> wr7
|
266 |
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when others => null;
|
267 |
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end case;
|
268 |
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|
269 |
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rind := character'pos(dname(3)) - character'pos('0');
|
270 |
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|
271 |
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if (dname(1)='r' or dname(1)='w') and -- check for [rw]r[0-7]
|
272 |
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dname(2)='r' and
|
273 |
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(rind>=0 and rind<=7) then
|
274 |
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dname(3) := '|'; -- replace with [rw]r|
|
275 |
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end if;
|
276 |
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|
277 |
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if dname(1) = '.' then
|
278 |
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case dname is
|
279 |
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when ".mode " => -- .mode
|
280 |
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readword_ea(iline, dname);
|
281 |
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assert dname="pdpcp "
|
282 |
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report "assert .mode == pdpcp" severity failure;
|
283 |
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|
284 |
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when ".reset" => -- .reset
|
285 |
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write(oline, string'(".reset"));
|
286 |
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writeline(output, oline);
|
287 |
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RESET <= '1';
|
288 |
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wait for clock_period;
|
289 |
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|
290 |
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RESET <= '0';
|
291 |
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wait for 9*clock_period;
|
292 |
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|
293 |
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when ".wait " => -- .wait
|
294 |
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read_ea(iline, idelta);
|
295 |
|
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wait for idelta*clock_period;
|
296 |
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|
297 |
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when ".tocmd" => -- .tocmd
|
298 |
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read_ea(iline, idelta);
|
299 |
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to_cmd := idelta;
|
300 |
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301 |
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when ".tostp" => -- .tostp
|
302 |
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read_ea(iline, idelta);
|
303 |
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to_stp := idelta;
|
304 |
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|
305 |
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when ".togo " => -- .togo
|
306 |
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read_ea(iline, idelta);
|
307 |
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to_go := idelta;
|
308 |
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|
309 |
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when ".sdef " => -- .sdef (ignore it)
|
310 |
|
|
readempty(iline);
|
311 |
|
|
|
312 |
|
|
when ".cerr " => -- .cerr
|
313 |
|
|
read_ea(iline, icerr);
|
314 |
|
|
when ".merr " => -- .merr
|
315 |
|
|
read_ea(iline, imerr);
|
316 |
|
|
|
317 |
|
|
when ".anena" => -- .anena (ignore it)
|
318 |
|
|
readempty(iline);
|
319 |
9 |
wfjm |
when ".rlmon" => -- .rlmon (ignore it)
|
320 |
2 |
wfjm |
readempty(iline);
|
321 |
|
|
when ".rbmon" => -- .rbmon (ignore it)
|
322 |
|
|
readempty(iline);
|
323 |
|
|
|
324 |
28 |
wfjm |
when ".scntl" => -- .scntl
|
325 |
2 |
wfjm |
read_ea(iline, ibit);
|
326 |
|
|
read_ea(iline, ien);
|
327 |
|
|
assert (ibit>=SB_CNTL'low and ibit<=SB_CNTL'high)
|
328 |
|
|
report "assert bit number in range of SB_CNTL"
|
329 |
|
|
severity failure;
|
330 |
|
|
if ien = '1' then
|
331 |
|
|
SB_CNTL(ibit) <= 'H';
|
332 |
|
|
else
|
333 |
|
|
SB_CNTL(ibit) <= 'L';
|
334 |
|
|
end if;
|
335 |
|
|
|
336 |
|
|
when others => -- bad directive
|
337 |
30 |
wfjm |
write(oline, string'("-E: unknown directive: "));
|
338 |
2 |
wfjm |
write(oline, dname);
|
339 |
|
|
writeline(output, oline);
|
340 |
|
|
report "aborting" severity failure;
|
341 |
|
|
end case;
|
342 |
|
|
|
343 |
|
|
testempty_ea(iline);
|
344 |
|
|
next file_loop;
|
345 |
|
|
|
346 |
|
|
else
|
347 |
|
|
|
348 |
|
|
ireq := true;
|
349 |
|
|
ifunc := c_cpfunc_noop;
|
350 |
|
|
irnum := "000";
|
351 |
|
|
ichk := false;
|
352 |
|
|
idin := (others=>'0');
|
353 |
|
|
imsk := (others=>'1');
|
354 |
|
|
imemi := false;
|
355 |
|
|
idoibr := false;
|
356 |
|
|
|
357 |
|
|
case dname is
|
358 |
|
|
when "brm " => -- brm
|
359 |
|
|
read_ea(iline, nblk);
|
360 |
|
|
xmicmd := "rmi";
|
361 |
|
|
next file_loop;
|
362 |
|
|
when "bwm " => -- bwm
|
363 |
|
|
read_ea(iline, nblk);
|
364 |
|
|
xmicmd := "wmi";
|
365 |
|
|
next file_loop;
|
366 |
|
|
|
367 |
|
|
when "rr| " => -- rr[0-7]
|
368 |
|
|
ifunc := c_cpfunc_rreg;
|
369 |
13 |
wfjm |
irnum := slv(to_unsigned(rind, 3));
|
370 |
2 |
wfjm |
readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
|
371 |
|
|
|
372 |
|
|
when "wr| " => -- wr[0-7]
|
373 |
|
|
ifunc := c_cpfunc_wreg;
|
374 |
13 |
wfjm |
irnum := slv(to_unsigned(rind, 3));
|
375 |
2 |
wfjm |
readoct_ea(iline, idin);
|
376 |
|
|
|
377 |
28 |
wfjm |
-- Note: there are no field definitions for wal, wah, wmembe because
|
378 |
2 |
wfjm |
-- there is no corresponding cp command. Therefore the
|
379 |
|
|
-- rbus field definitions are used here
|
380 |
|
|
when "wal " => -- wal
|
381 |
|
|
readoct_ea(iline, idin);
|
382 |
|
|
r_addr := (others=>'0'); -- write to al clears ah !!
|
383 |
|
|
r_ena_22bit := '0';
|
384 |
|
|
r_ena_ubmap := '0';
|
385 |
|
|
r_addr(c_al_rbf_addr) := idin(c_al_rbf_addr);
|
386 |
|
|
testempty_ea(iline);
|
387 |
|
|
next file_loop;
|
388 |
|
|
|
389 |
|
|
when "wah " => -- wah
|
390 |
|
|
readoct_ea(iline, idin);
|
391 |
|
|
r_addr(21 downto 16) := idin(c_ah_rbf_addr);
|
392 |
|
|
r_ena_22bit := idin(c_ah_rbf_ena_22bit);
|
393 |
|
|
r_ena_ubmap := idin(c_ah_rbf_ena_ubmap);
|
394 |
|
|
testempty_ea(iline);
|
395 |
|
|
next file_loop;
|
396 |
|
|
|
397 |
28 |
wfjm |
when "wmembe" => -- wmembe
|
398 |
|
|
read_ea(iline, idin3);
|
399 |
|
|
r_membestick := idin3(c_membe_rbf_stick);
|
400 |
|
|
r_membe := idin3(c_membe_rbf_be);
|
401 |
2 |
wfjm |
testempty_ea(iline);
|
402 |
|
|
next file_loop;
|
403 |
|
|
|
404 |
|
|
when "rm " => -- rm
|
405 |
|
|
ifunc := c_cpfunc_rmem;
|
406 |
|
|
readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
|
407 |
|
|
when "rmi " => -- rmi
|
408 |
|
|
ifunc := c_cpfunc_rmem;
|
409 |
|
|
imemi := true;
|
410 |
|
|
readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
|
411 |
|
|
|
412 |
|
|
when "wm " => -- wm
|
413 |
|
|
ifunc := c_cpfunc_wmem;
|
414 |
|
|
readoct_ea(iline, idin);
|
415 |
|
|
when "wmi " => -- wmi
|
416 |
|
|
ifunc := c_cpfunc_wmem;
|
417 |
|
|
imemi := true;
|
418 |
|
|
readoct_ea(iline, idin);
|
419 |
|
|
|
420 |
|
|
when "ribr " => -- ribr
|
421 |
|
|
ifunc := c_cpfunc_rmem;
|
422 |
|
|
idoibr := true;
|
423 |
28 |
wfjm |
readoct_ea(iline, iaddr);
|
424 |
2 |
wfjm |
readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
|
425 |
|
|
when "wibr " => -- wibr
|
426 |
|
|
ifunc := c_cpfunc_wmem;
|
427 |
|
|
idoibr := true;
|
428 |
28 |
wfjm |
readoct_ea(iline, iaddr);
|
429 |
2 |
wfjm |
readoct_ea(iline, idin);
|
430 |
|
|
|
431 |
|
|
when "rps " => -- rps
|
432 |
|
|
ifunc := c_cpfunc_rpsw;
|
433 |
|
|
readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
|
434 |
|
|
when "wps " => -- wps
|
435 |
|
|
ifunc := c_cpfunc_wpsw;
|
436 |
|
|
readoct_ea(iline, idin);
|
437 |
|
|
|
438 |
|
|
-- Note: in old version 'sta addr' was an atomic operation, loading
|
439 |
|
|
-- the pc and starting the cpu. Now this is action is two step
|
440 |
|
|
-- first a wpc followed by a 'sta'.
|
441 |
|
|
when "stapc " => -- stapc
|
442 |
|
|
ifunc := c_cpfunc_wreg;
|
443 |
|
|
irnum := c_gpr_pc;
|
444 |
|
|
readoct_ea(iline, idin);
|
445 |
|
|
idosta := '1'; -- request 'sta' to be done next
|
446 |
|
|
|
447 |
|
|
when "sta " => -- sta
|
448 |
30 |
wfjm |
ifunc := c_cpfunc_start;
|
449 |
2 |
wfjm |
when "sto " => -- sto
|
450 |
30 |
wfjm |
ifunc := c_cpfunc_stop;
|
451 |
2 |
wfjm |
when "step " => -- step
|
452 |
|
|
ifunc := c_cpfunc_step;
|
453 |
|
|
iwtstp := true;
|
454 |
30 |
wfjm |
when "cres " => -- cres
|
455 |
|
|
ifunc := c_cpfunc_creset;
|
456 |
|
|
when "bres " => -- bres
|
457 |
|
|
ifunc := c_cpfunc_breset;
|
458 |
|
|
when "susp " => -- susp
|
459 |
|
|
ifunc := c_cpfunc_suspend;
|
460 |
|
|
when "resu " => -- resu
|
461 |
|
|
ifunc := c_cpfunc_resume;
|
462 |
2 |
wfjm |
|
463 |
|
|
when "wtgo " => -- wtgo
|
464 |
|
|
iwtgo := true;
|
465 |
|
|
ireq := false; -- no cp request !
|
466 |
|
|
|
467 |
|
|
when "wtlam " => -- wtlam (ignore it)
|
468 |
|
|
readempty(iline);
|
469 |
|
|
next file_loop;
|
470 |
|
|
|
471 |
|
|
when others => -- bad directive
|
472 |
30 |
wfjm |
write(oline, string'("-E: unknown directive: "));
|
473 |
2 |
wfjm |
write(oline, dname);
|
474 |
|
|
writeline(output, oline);
|
475 |
|
|
report "aborting" severity failure;
|
476 |
|
|
end case;
|
477 |
|
|
|
478 |
|
|
end if;
|
479 |
|
|
testempty_ea(iline);
|
480 |
|
|
|
481 |
|
|
end if;
|
482 |
|
|
|
483 |
28 |
wfjm |
CP_ADDR_be <= r_membe;
|
484 |
2 |
wfjm |
if idoibr then
|
485 |
28 |
wfjm |
CP_ADDR_addr(15 downto 13) <= "111";
|
486 |
|
|
CP_ADDR_addr(12 downto 1) <= iaddr(12 downto 1);
|
487 |
2 |
wfjm |
CP_ADDR_racc <= '1';
|
488 |
|
|
CP_ADDR_ena_22bit <= '0';
|
489 |
|
|
CP_ADDR_ena_ubmap <= '0';
|
490 |
|
|
else
|
491 |
|
|
CP_ADDR_addr <= r_addr;
|
492 |
|
|
CP_ADDR_racc <= '0';
|
493 |
|
|
CP_ADDR_be <= "11";
|
494 |
|
|
CP_ADDR_ena_22bit <= r_ena_22bit;
|
495 |
|
|
CP_ADDR_ena_ubmap <= r_ena_ubmap;
|
496 |
|
|
end if;
|
497 |
|
|
|
498 |
|
|
if ireq then
|
499 |
|
|
CP_CNTL_req <= '1';
|
500 |
|
|
CP_CNTL_func <= ifunc;
|
501 |
|
|
CP_CNTL_rnum <= irnum;
|
502 |
|
|
end if;
|
503 |
|
|
|
504 |
|
|
if ichk then
|
505 |
|
|
CP_DIN <= (others=>'0');
|
506 |
|
|
R_CHKDAT <= idin;
|
507 |
|
|
R_CHKMSK <= imsk;
|
508 |
|
|
R_CHKREQ <= '1';
|
509 |
|
|
else
|
510 |
|
|
CP_DIN <= idin;
|
511 |
|
|
R_CHKREQ <= '0';
|
512 |
|
|
end if;
|
513 |
|
|
|
514 |
|
|
R_WAITCMD <= '0';
|
515 |
|
|
R_WAITSTEP <= '0';
|
516 |
|
|
R_WAITGO <= '0';
|
517 |
|
|
if iwtgo then
|
518 |
|
|
idelta := to_go;
|
519 |
|
|
R_WAITGO <= '1';
|
520 |
|
|
elsif iwtstp then
|
521 |
|
|
idelta := to_stp;
|
522 |
|
|
R_WAITSTEP <= '1';
|
523 |
|
|
else
|
524 |
|
|
idelta := to_cmd;
|
525 |
|
|
R_WAITCMD <= '1';
|
526 |
|
|
end if;
|
527 |
|
|
|
528 |
|
|
wait for clock_period;
|
529 |
|
|
CP_CNTL_req <= '0';
|
530 |
|
|
|
531 |
|
|
dcycle := 1;
|
532 |
|
|
while idelta>0 and R_WAITOK='0' loop
|
533 |
|
|
wait for clock_period;
|
534 |
|
|
dcycle := dcycle + 1;
|
535 |
|
|
idelta := idelta - 1;
|
536 |
|
|
end loop;
|
537 |
|
|
|
538 |
28 |
wfjm |
if imemi then -- rmi or wmi seen ? then inc ar
|
539 |
13 |
wfjm |
r_addr := slv(unsigned(r_addr) + 1);
|
540 |
2 |
wfjm |
end if;
|
541 |
28 |
wfjm |
|
542 |
|
|
if ifunc = c_cpfunc_wmem and -- emulate be sticky logic of rbus iface
|
543 |
|
|
r_membestick = '0' then
|
544 |
|
|
r_membe := "11";
|
545 |
|
|
end if;
|
546 |
2 |
wfjm |
|
547 |
|
|
write(oline, dcycle, right, 4);
|
548 |
|
|
write(oline, string'(" "));
|
549 |
|
|
if ireq then
|
550 |
|
|
case ifunc is
|
551 |
|
|
when c_cpfunc_rreg => write(oline, string'("rreg"));
|
552 |
|
|
when c_cpfunc_wreg => write(oline, string'("wreg"));
|
553 |
|
|
when c_cpfunc_rpsw => write(oline, string'("rpsw"));
|
554 |
|
|
when c_cpfunc_wpsw => write(oline, string'("wpsw"));
|
555 |
|
|
when c_cpfunc_rmem =>
|
556 |
|
|
if idoibr then
|
557 |
|
|
write(oline, string'("ribr"));
|
558 |
|
|
else
|
559 |
|
|
write(oline, string'("rmem"));
|
560 |
|
|
end if;
|
561 |
|
|
when c_cpfunc_wmem =>
|
562 |
|
|
if idoibr then
|
563 |
|
|
write(oline, string'("wibr"));
|
564 |
|
|
else
|
565 |
|
|
write(oline, string'("wmem"));
|
566 |
|
|
end if;
|
567 |
30 |
wfjm |
when c_cpfunc_start => write(oline, string'("sta "));
|
568 |
|
|
when c_cpfunc_stop => write(oline, string'("sto "));
|
569 |
|
|
when c_cpfunc_step => write(oline, string'("step"));
|
570 |
|
|
when c_cpfunc_creset => write(oline, string'("cres"));
|
571 |
|
|
when c_cpfunc_breset => write(oline, string'("bres"));
|
572 |
|
|
when c_cpfunc_suspend => write(oline, string'("susp"));
|
573 |
|
|
when c_cpfunc_resume => write(oline, string'("resu"));
|
574 |
2 |
wfjm |
when others =>
|
575 |
|
|
write(oline, string'("?"));
|
576 |
|
|
writeoct(oline, ifunc, right, 2);
|
577 |
|
|
write(oline, string'("?"));
|
578 |
|
|
end case;
|
579 |
|
|
writeoct(oline, irnum, right, 2);
|
580 |
|
|
writeoct(oline, idin, right, 8);
|
581 |
|
|
else
|
582 |
|
|
write(oline, string'("---- - ------"));
|
583 |
|
|
end if;
|
584 |
|
|
|
585 |
|
|
write(oline, R_CP_STAT.cmdbusy, right, 3);
|
586 |
|
|
write(oline, R_CP_STAT.cmdack, right, 2);
|
587 |
|
|
write(oline, R_CP_STAT.cmderr, right, 2);
|
588 |
|
|
write(oline, R_CP_STAT.cmdmerr, right, 2);
|
589 |
|
|
writeoct(oline, R_CP_DOUT, right, 8);
|
590 |
|
|
write(oline, R_CP_STAT.cpugo, right, 3);
|
591 |
30 |
wfjm |
write(oline, R_CP_STAT.cpustep, right, 1);
|
592 |
|
|
write(oline, R_CP_STAT.cpuwait, right, 1);
|
593 |
|
|
write(oline, R_CP_STAT.cpususp, right, 1);
|
594 |
|
|
write(oline, R_CP_STAT.suspint, right, 1);
|
595 |
|
|
write(oline, R_CP_STAT.suspext, right, 1);
|
596 |
2 |
wfjm |
writeoct(oline, R_CP_STAT.cpurust, right, 3);
|
597 |
|
|
|
598 |
|
|
if R_WAITOK = '1' then
|
599 |
|
|
if R_CP_STAT.cmderr='1' or icerr=1 then
|
600 |
|
|
if R_CP_STAT.cmderr='1' and icerr=0 then
|
601 |
|
|
write(oline, string'(" FAIL CMDERR"));
|
602 |
|
|
elsif R_CP_STAT.cmderr='1' and icerr=1 then
|
603 |
|
|
write(oline, string'(" CHECK CMDERR SEEN"));
|
604 |
|
|
elsif R_CP_STAT.cmderr='0' and icerr=1 then
|
605 |
|
|
write(oline, string'(" FAIL CMDERR EXPECTED,MISSED"));
|
606 |
|
|
end if;
|
607 |
|
|
elsif R_CP_STAT.cmdmerr='1' or imerr=1 then
|
608 |
|
|
if R_CP_STAT.cmdmerr='1' and imerr=0 then
|
609 |
|
|
write(oline, string'(" FAIL CMDMERR"));
|
610 |
|
|
elsif R_CP_STAT.cmdmerr='1' and imerr=1 then
|
611 |
|
|
write(oline, string'(" CHECK CMDMERR SEEN"));
|
612 |
|
|
elsif R_CP_STAT.cmdmerr='0' and imerr=1 then
|
613 |
|
|
write(oline, string'(" FAIL CMDMERR EXPECTED,MISSED"));
|
614 |
|
|
end if;
|
615 |
|
|
elsif R_CHKREQ='1' then
|
616 |
|
|
if unsigned((R_CP_DOUT xor R_CHKDAT) and (not R_CHKMSK))=0 then
|
617 |
|
|
write(oline, string'(" CHECK OK"));
|
618 |
|
|
else
|
619 |
|
|
write(oline, string'(" CHECK FAILED, d="));
|
620 |
|
|
writeoct(oline, R_CHKDAT, right, 7);
|
621 |
|
|
if unsigned(R_CHKMSK)/=0 then
|
622 |
|
|
write(oline, string'(","));
|
623 |
|
|
writeoct(oline, R_CHKMSK, right, 7);
|
624 |
|
|
end if;
|
625 |
|
|
end if;
|
626 |
|
|
end if;
|
627 |
|
|
|
628 |
|
|
if iwtgo then
|
629 |
|
|
write(oline, string'(" WAIT GO OK "));
|
630 |
|
|
elsif iwtstp then
|
631 |
|
|
write(oline, string'(" WAIT STEP OK"));
|
632 |
|
|
end if;
|
633 |
|
|
|
634 |
|
|
else
|
635 |
|
|
write(oline, string'(" WAIT FAILED (will reset)"));
|
636 |
|
|
RESET <= '1';
|
637 |
|
|
wait for clock_period;
|
638 |
|
|
|
639 |
|
|
RESET <= '0';
|
640 |
|
|
wait for 9*clock_period;
|
641 |
|
|
|
642 |
|
|
end if;
|
643 |
|
|
writeline(output, oline);
|
644 |
|
|
|
645 |
|
|
end loop;
|
646 |
|
|
|
647 |
|
|
wait for 4*clock_period;
|
648 |
|
|
CLK_STOP <= '1';
|
649 |
|
|
|
650 |
17 |
wfjm |
writetimestamp(oline, CLK_CYCLE, ": DONE ");
|
651 |
2 |
wfjm |
writeline(output, oline);
|
652 |
|
|
|
653 |
|
|
wait; -- suspend proc_stim forever
|
654 |
|
|
-- clock is stopped, sim will end
|
655 |
|
|
|
656 |
|
|
end process proc_stim;
|
657 |
|
|
|
658 |
|
|
proc_moni: process
|
659 |
|
|
begin
|
660 |
|
|
|
661 |
|
|
loop
|
662 |
13 |
wfjm |
wait until rising_edge(CLK);
|
663 |
2 |
wfjm |
wait for c2out_time;
|
664 |
|
|
|
665 |
|
|
R_WAITOK <= '0';
|
666 |
|
|
if R_WAITCMD = '1' then
|
667 |
|
|
if CP_STAT_cmdack = '1' then
|
668 |
|
|
R_WAITOK <= '1';
|
669 |
|
|
end if;
|
670 |
|
|
elsif R_WAITGO = '1' then
|
671 |
|
|
if CP_STAT_cmdbusy='0' and CP_STAT_cpugo='0' then
|
672 |
|
|
R_WAITOK <= '1';
|
673 |
|
|
end if;
|
674 |
|
|
elsif R_WAITSTEP = '1' then
|
675 |
|
|
if CP_STAT_cmdbusy='0' and CP_STAT_cpustep='0' then
|
676 |
|
|
R_WAITOK <= '1';
|
677 |
|
|
end if;
|
678 |
|
|
end if;
|
679 |
|
|
|
680 |
|
|
R_CP_STAT.cmdbusy <= CP_STAT_cmdbusy;
|
681 |
|
|
R_CP_STAT.cmdack <= CP_STAT_cmdack;
|
682 |
|
|
R_CP_STAT.cmderr <= CP_STAT_cmderr;
|
683 |
|
|
R_CP_STAT.cmdmerr <= CP_STAT_cmdmerr;
|
684 |
|
|
R_CP_STAT.cpugo <= CP_STAT_cpugo;
|
685 |
|
|
R_CP_STAT.cpustep <= CP_STAT_cpustep;
|
686 |
30 |
wfjm |
R_CP_STAT.cpuwait <= CP_STAT_cpuwait;
|
687 |
|
|
R_CP_STAT.cpususp <= CP_STAT_cpususp;
|
688 |
2 |
wfjm |
R_CP_STAT.cpurust <= CP_STAT_cpurust;
|
689 |
30 |
wfjm |
R_CP_STAT.suspint <= CP_STAT_suspint;
|
690 |
|
|
R_CP_STAT.suspext <= CP_STAT_suspext;
|
691 |
2 |
wfjm |
R_CP_DOUT <= CP_DOUT;
|
692 |
|
|
|
693 |
|
|
end loop;
|
694 |
|
|
|
695 |
|
|
end process proc_moni;
|
696 |
|
|
|
697 |
|
|
end sim;
|