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wfjm |
# $Id: tb_pdp11_core_stim.dat 311 2010-06-30 17:52:37Z mueller $
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#
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# Revision History:
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# Date Rev Version Comment
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# 2010-06-20 308 2.2.1 add wibrb, ribr, wibr based tests
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# 2010-06-13 305 2.2 adopt to new rri address and function semantics
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# 2009-11-22 252 2.1.14 change SSR0 expects, adapt to ECO-021.
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# 2009-05-02 211 2.1.13 add nop after spl in pirq test, 11/70 spl now !!
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# 2008-08-29 163 2.1.12 add wtlam to harvest attn after sto in test 13
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# 2008-04-27 139 2.1.11 adapt expected ssr1 after mtpi/d after ECO-009 fix
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# 2008-03-15 125 2.1.10 exclude some tests from simh ([[off/on]]
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# 2008-03-09 124 2.1.9 fixed addr-mode in code 34, shifted 47+50
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# 2008-03-02 121 2.1.8 add meory access error tests
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# add Code 13, testing WAIT and bwm/brm while CPU runs
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# 2008-02-24 119 2.1.7 add tests for lah,rps,wps; use rps,wps
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# use 22bit mode for nxm test (now needed!)
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# 2008-02-23 118 2.1.6 for nxm tests use mmu and page below i/o-page
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# in code 35 use access to 160000 to test trap
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# 2007-09-23 84 2.1.5 use .reset to make it re-executable
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# 2007-09-16 83 2.1.4 clear CPUERR in beginning of test 20 {runs in FPGA}
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# 2007-09-02 79 2.1.3 add .mode command (for pi_rri use)
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# 2007-08-25 75 2.1.2 add .cpmon/.rpmon (for use with rri)
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# 2007-08-16 74 2.1.1 adapt to changed LAM handling
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# 2007-08-12 73 2.1 use wtgo (revised conv_stim)
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# 2007-08-03 71 2.0 convert to command mode with conv_stim
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# 2007-07-08 65 1.2 removed 1st 'delay' parameter; use .to_(cmd|stp|go)
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# 2007-06-10 51 1.1 consolidate w11a test bench
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# 2007-05-13 29 1.0 initial version (imported)
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#
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.mode pdpcp
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.tocmd 50
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.tostp 100
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.togo 5000
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.cpmon 0
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.rbmon 0
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.scntl 13 0
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#
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.reset
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.wait 10
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.anena 1
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#
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C "Code 0" Some elementary initial tests
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C write registers
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#
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wr0 000001 -- set r0,..,r7
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46 |
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wr1 000101 --
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wr2 000201 --
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48 |
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wr3 000301 --
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wr4 000401 --
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wr5 000501 --
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wsp 000601 --
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wpc 000701 --
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#
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C read registers
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#
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rr0 d=000001 -- ! r0
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rr1 d=000101 -- ! r1
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rr2 d=000201 -- ! r2
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rr3 d=000301 -- ! r3
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rr4 d=000401 -- ! r4
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rr5 d=000501 -- ! r5
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rsp d=000601 -- ! sp
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rpc d=000701 -- ! pc
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#
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C write memory
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#
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wal 002000 -- write mem(2000,...,2006)
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bwm 4
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007700 --
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007710 --
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007720 --
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007730 --
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#
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C read memory
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#
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wal 002000
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brm 4
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d=007700 -- ! mem(2000)
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d=007710 -- ! mem(2002)
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d=007720 -- ! mem(2004)
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d=007730 -- ! mem(2006)
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#
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C write/read PSW via various mechanisms
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C via wps/rps
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#
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wps 000017
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rps d=000017
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wps 000000
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rps d=000000
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#
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C via 16bit cp addressing (wal 177776)
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#
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wal 177776
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wm 000017 -- set all cc flags in psw
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rm d=000017 -- ! psw
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rps d=000017
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wm 000000 -- clear psw
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rm d=000000 -- ! psw
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rps d=000000
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#
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C via 22bit cp addressing (wal 177776; wah 177)
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#
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wal 177776
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wah 000177
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wm 000017 -- set all cc flags in psw
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rm d=000017 -- ! psw
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rps d=000017
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wm 000000 -- clear psw
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rm d=000000 -- ! psw
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rps d=000000
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#
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C via ibr (ibrb 177700)
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#
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wibrb 177700
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wibr 76 000017 -- set all cc flags in psw
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ribr 76 d=000017 -- ! psw
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rps d=000017
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wibr 76 000000 -- set all cc flags in psw
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ribr 76 d=000000 -- ! psw
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rps d=000000
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#
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C write register set 1, sm,um stack
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#
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wps 004000 -- psw: cm=kernel, set=1
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wr0 010001 -- set r0,..,r5 [[r10]]
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126 |
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wr1 010101 -- [[r11]]
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wr2 010201 -- [[r12]]
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128 |
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wr3 010301 -- [[r13]]
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wr4 010401 -- [[r14]]
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wr5 010501 -- [[r15]]
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wps 044000 -- psw: cm=super(01),set=1
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wsp 010601 -- set ssp [[ssp]]
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wps 144000 -- psw: cm=user(11),set=1
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wsp 110601 -- set usp [[usp]]
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#
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C read all registers set 0/1, km,sm,um stack
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137 |
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#
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138 |
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wps 000000 -- psw: cm=kernel(00),set=0
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139 |
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rr0 d=000001 -- ! r0
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140 |
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rr1 d=000101 -- ! r1
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rr2 d=000201 -- ! r2
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rr3 d=000301 -- ! r3
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rr4 d=000401 -- ! r4
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144 |
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rr5 d=000501 -- ! r5
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rsp d=000601 -- ! ksp
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rpc d=000701 -- ! pc
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wps 040000 -- psw: cm=super(01),set=0
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rsp d=010601 -- ! ssp [[ssp]]
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wps 140000 -- psw: cm=user(11),set=0
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rsp d=110601 -- ! usp [[usp]]
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wps 144000 -- psw: cm=user(11),set=1
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rr0 d=010001 -- ! r0 [[r10]]
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rr1 d=010101 -- ! r1 [[r11]]
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rr2 d=010201 -- ! r2 [[r12]]
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rr3 d=010301 -- ! r3 [[r13]]
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rr4 d=010401 -- ! r4 [[r14]]
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157 |
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rr5 d=010501 -- ! r5 [[r15]]
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#
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C write IB space: MMU SAR supervisor mode (16 bit regs)
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#
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wal 172240 -- set first three SM I space address regs
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bwm 3
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012340
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012342
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012344
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#
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C read IB space: MMU SAR supervisor mode (16 bit regs)
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#
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wal 172240 -- ! verify first three SM I space address regs
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brm 3
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d=012340
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d=012342
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d=012344
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#
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C read IB space via ibr: MMU SAR supervisor mode (16 bit regs)
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#
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177 |
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wibrb 172200
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ribr 40 d=012340
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ribr 42 d=012342
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ribr 44 d=012344
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#
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C byte write IB space via ibr: MMU SAR supervisor mode (16 bit regs)
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#
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wibrb 172201 -- write low byte
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wibr 40 177000
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wibr 42 177002
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wibr 44 177004
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wal 172240 -- ! verify
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brm 3
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d=012000
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d=012002
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d=012004
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#
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wibrb 172202 -- write high byte
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wibr 40 000377
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wibr 42 022377
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wibr 44 044377
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wal 172240 -- ! verify
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brm 3
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d=000000
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d=022002
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d=044004
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#
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wibrb 172203 -- write high and low byte (both be set)
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wibr 40 012340
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wibr 42 012342
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wibr 44 012344
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wal 172240 -- ! verify
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brm 3
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d=012340
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d=012342
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d=012344
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#
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#[[off]] - this tests cp not the cpu - meaningless in simh
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#
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216 |
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C test access error handling to memory (use 17740000)
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217 |
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C with wm/rm
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218 |
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#
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219 |
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wal 140000
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wah 000177
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.merr 1
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.sdef s=10000001
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wm 000000
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rm d=-
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.merr 0
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.sdef s=00000000,01110000
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#
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228 |
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C with bwm/brm
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#
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wal 140000
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wah 000177
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.merr 1
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.sdef s=10000001
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bwm 2
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000000
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000000
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.merr 0
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238 |
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.sdef s=00000000,01110000
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#
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wal 140000
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wah 000177
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.merr 1
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.sdef s=10000001
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brm 2
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d=-
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d=-
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.merr 0
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.sdef s=00000000,01110000
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249 |
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#
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250 |
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C test access error handling to IB space (use 00160000)
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251 |
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C with wm/rm
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wal 160000
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.merr 1
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254 |
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.sdef s=10000001
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wm 000000
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256 |
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rm d=-
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.merr 0
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.sdef s=00000000,01110000
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259 |
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C with bwm/brm
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#
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wal 160000
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.merr 1
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.sdef s=10000001
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bwm 2
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000000
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000000
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.merr 0
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268 |
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.sdef s=00000000,01110000
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269 |
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#
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270 |
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wal 160000
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.merr 1
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272 |
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.sdef s=10000001
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273 |
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brm 2
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274 |
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d=-
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275 |
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d=-
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276 |
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.merr 0
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277 |
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.sdef s=00000000,01110000
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278 |
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#[[on]]
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279 |
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#-----------------------------------------------------------------------------
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280 |
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C Setup trap catchers
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281 |
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#
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282 |
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wal 000004 -- vectors: 4...34 (trap catcher)
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283 |
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bwm 14
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284 |
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000006 -- PC:06 ; vector 4
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285 |
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000000 -- PS:0
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286 |
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000012 -- PC:12 ; vector 10
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287 |
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000000 -- PS:0
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288 |
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000016 -- PC:16 ; vector 14 (T bit; BPT)
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289 |
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000000 -- PS:0
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290 |
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000022 -- PC:22 ; vector 20 (IOT)
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291 |
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000000 -- PS:0
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292 |
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000026 -- PC:26 ; vector 24 (Power fail, not used)
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293 |
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000000 -- PS:0
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294 |
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000032 -- PC:32 ; vector 30 (EMT)
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295 |
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000000 -- PS:0
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296 |
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000036 -- PC:36 ; vector 34 (TRAP)
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297 |
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000000 -- PS:0
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298 |
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wal 000240 -- vectors: 240,244,250 (trap catcher)
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299 |
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bwm 6
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300 |
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000242 -- PC:242 ; vector 240 (PIRQ)
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301 |
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000000 -- PS:0
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302 |
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000246 -- PC:246 ; vector 244 (FPU)
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303 |
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000000 -- PS:0
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304 |
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000252 -- PC:252 ; vector 250 (MMU)
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305 |
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000000 -- PS:0
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306 |
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#
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307 |
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C Setup MMU
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308 |
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#
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309 |
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wal 172300 -- kernel I space DR
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310 |
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bwm 8
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311 |
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077406 -- slf=127; ed=0(up); acf=6(w/r)
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312 |
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077406 -- slf=127; ed=0(up); acf=6(w/r)
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313 |
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077406 -- slf=127; ed=0(up); acf=6(w/r)
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314 |
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077406 -- slf=127; ed=0(up); acf=6(w/r)
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315 |
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077406 -- slf=127; ed=0(up); acf=6(w/r)
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316 |
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077406 -- slf=127; ed=0(up); acf=6(w/r)
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317 |
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077406 -- slf=127; ed=0(up); acf=6(w/r)
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318 |
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077406 -- slf=127; ed=0(up); acf=6(w/r)
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319 |
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wal 172340 -- kernel I space AR
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320 |
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bwm 8
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321 |
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000000 -- 0
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322 |
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000200 -- 200 020000 base
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323 |
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000400 -- 400 040000 base
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324 |
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000600 -- 600 060000 base
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325 |
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001000 -- 1000 100000 base
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326 |
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001200 -- 1200 120000 base
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327 |
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001400 -- 1400 140000 base
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328 |
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177600 -- 176000 (map to I/O page)
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329 |
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#-----------------------------------------------------------------------------
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330 |
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C Setup code 1 [base 2100] (very basics: cont,start; 'simple' instructions)
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331 |
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#
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332 |
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wal 002100 -- code test 1: (sec+clc+halt)
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333 |
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bwm 3
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334 |
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000261 -- sec
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335 |
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000250 -- cln
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336 |
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000000 -- halt
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337 |
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#-----
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338 |
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wal 002120 -- code test 2: (4 *inc R2, starting from -2)
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339 |
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bwm 5
|
340 |
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005202 -- inc r2
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341 |
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005202 -- inc r2
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342 |
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005202 -- inc r2
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343 |
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005202 -- inc r2
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344 |
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#2130
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345 |
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000000 -- halt
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346 |
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#-----
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347 |
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wal 002140 -- code test 3: (dec r3; bne -2; halt)
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348 |
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bwm 3
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349 |
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005303 -- dec r3
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350 |
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001376 -- bne -2
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351 |
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000000 -- halt
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352 |
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#-----
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353 |
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wal 002160 -- code test 4: (inc r1; sob r0,-2; halt)
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354 |
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bwm 3
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355 |
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005201 -- inc r1
|
356 |
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077002 -- sob r0,-2
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357 |
|
|
000000 -- halt
|
358 |
|
|
#
|
359 |
|
|
C Exec code 1 (very basics: cont,start; 'simple' instructions)
|
360 |
|
|
C Exec test 1.1 (sec+clc+halt)
|
361 |
|
|
#
|
362 |
|
|
wpc 002100 -- pc=2100
|
363 |
|
|
wps 000010 -- psw: set N flag
|
364 |
|
|
cont -- cont @ 2100
|
365 |
|
|
wtgo
|
366 |
|
|
rpc d=002106 -- ! pc
|
367 |
|
|
rps d=000001 -- ! N cleared, C set now
|
368 |
|
|
#
|
369 |
|
|
C Exec test 1.2 (4 *inc R2, starting from -2)
|
370 |
|
|
#
|
371 |
|
|
wr2 177776 -- r2=-2
|
372 |
|
|
stapc 002120 -- start @ 2120
|
373 |
|
|
wtgo
|
374 |
|
|
rr2 d=000002 -- ! r2=2
|
375 |
|
|
rpc d=002132 -- ! pc
|
376 |
|
|
#
|
377 |
|
|
C Exec test 1.3 (dec r3; bne -2; halt)
|
378 |
|
|
#
|
379 |
|
|
wr3 000002 -- r3=2
|
380 |
|
|
stapc 002140 -- start @ 2140
|
381 |
|
|
wtgo
|
382 |
|
|
rr3 d=000000 -- ! r3=0
|
383 |
|
|
rpc d=002146 -- ! pc
|
384 |
|
|
#
|
385 |
|
|
C Exec test 1.4 (inc r1; sob r0,-2; halt)
|
386 |
|
|
#
|
387 |
|
|
wr0 000002 -- r0=2
|
388 |
|
|
wr1 000000 -- r1=0
|
389 |
|
|
stapc 002160 -- start @ 2160
|
390 |
|
|
wtgo
|
391 |
|
|
rr0 d=000000 -- ! r0=0
|
392 |
|
|
rr1 d=000002 -- ! r1=2
|
393 |
|
|
rpc d=002166 -- ! pc
|
394 |
|
|
#-----------------------------------------------------------------------------
|
395 |
|
|
C Setup code 2 [base 2200] (bpt against trap catcher @14)
|
396 |
|
|
#
|
397 |
|
|
wal 002200 -- code:
|
398 |
|
|
bwm 4
|
399 |
|
|
000257 -- cl(nzvc)
|
400 |
|
|
000261 -- sec
|
401 |
|
|
000003 -- bpt
|
402 |
|
|
000000 -- halt
|
403 |
|
|
#
|
404 |
|
|
C Exec code 2 (bpt against trap catcher @14)
|
405 |
|
|
#
|
406 |
|
|
wsp 001400 -- sp=1400
|
407 |
|
|
stapc 002200 -- start @ 2200
|
408 |
|
|
wtgo
|
409 |
|
|
rsp d=001374 -- ! sp
|
410 |
|
|
rpc d=000020 -- ! pc
|
411 |
|
|
wal 001374
|
412 |
|
|
brm 2
|
413 |
|
|
d=002206 -- ! (sp) old pc
|
414 |
|
|
d=000341 -- ! 2(sp) old ps
|
415 |
|
|
#-----------------------------------------------------------------------------
|
416 |
|
|
C Setup code 3 [base 2300] (bpt against trap handler doing inc r0; rtt)
|
417 |
|
|
#
|
418 |
|
|
wal 002300 -- code:
|
419 |
|
|
bwm 4
|
420 |
|
|
000257 -- cl(nzvc)
|
421 |
|
|
000003 -- bpt
|
422 |
|
|
005201 -- inc r1
|
423 |
|
|
000000 -- halt
|
424 |
|
|
wal 000014 -- vector: 14
|
425 |
|
|
bwm 2
|
426 |
|
|
002320 -- PC:2320
|
427 |
|
|
000002 -- PS:2
|
428 |
|
|
wal 002320 -- code (trap 14):
|
429 |
|
|
bwm 3
|
430 |
|
|
005200 -- inc r0
|
431 |
|
|
000006 -- rtt
|
432 |
|
|
000000 -- halt
|
433 |
|
|
#
|
434 |
|
|
C Exec code 3 (bpt against trap handler doing inc r0; rtt)
|
435 |
|
|
#
|
436 |
|
|
wr0 000000 -- r0=0
|
437 |
|
|
wr1 000000 -- r1=0
|
438 |
|
|
wsp 001400 -- sp=1400
|
439 |
|
|
stapc 002300 -- start @ 2300
|
440 |
|
|
wtgo
|
441 |
|
|
rr0 d=000001 -- ! r0
|
442 |
|
|
rr1 d=000001 -- ! r1
|
443 |
|
|
rsp d=001400 -- ! sp
|
444 |
|
|
rpc d=002310 -- ! pc
|
445 |
|
|
#-----------------------------------------------------------------------------
|
446 |
|
|
C Setup code 4 [base 2400] (enable T-trap on handler of code 3; run 2* inc r1)
|
447 |
|
|
#
|
448 |
|
|
wal 002400
|
449 |
|
|
bwm 4
|
450 |
|
|
000006 -- rtt
|
451 |
|
|
005201 -- inc r1
|
452 |
|
|
005201 -- inc r1
|
453 |
|
|
000000 -- halt
|
454 |
|
|
#
|
455 |
|
|
C Exec code 4 (enable T-trap on handler of code 3; run 2* inc r1)
|
456 |
|
|
#
|
457 |
|
|
wr0 000000 -- r0=0
|
458 |
|
|
wr1 000000 -- r1=0
|
459 |
|
|
wsp 001374 -- sp=1374
|
460 |
|
|
wal 001374 -- setup stack with rtt return frame setting T flag
|
461 |
|
|
bwm 2
|
462 |
|
|
002402 -- start address
|
463 |
|
|
000020 -- set T flag in PSW
|
464 |
|
|
stapc 002400 -- start @ 2400 -> rtt -> 2402 from stack
|
465 |
|
|
wtgo
|
466 |
|
|
rr0 d=000002 -- ! r0
|
467 |
|
|
rr1 d=000002 -- ! r1
|
468 |
|
|
rsp d=001400 -- ! sp
|
469 |
|
|
rpc d=002410 -- ! pc
|
470 |
|
|
#
|
471 |
|
|
rst -- console reset (to clear T flag)
|
472 |
|
|
wal 000014 -- vector: 14 -> trap catcher again
|
473 |
|
|
bwm 2
|
474 |
|
|
000016 -- PC:16
|
475 |
|
|
000000 -- PS:0
|
476 |
|
|
#-----------------------------------------------------------------------------
|
477 |
|
|
C Setup code 5 [base 2500] (srcr modes: mov xxx,rn: (r0),(r0)+,-(r0),@(r0))
|
478 |
|
|
#
|
479 |
|
|
wal 002500 -- code:
|
480 |
|
|
bwm 6
|
481 |
|
|
011001 -- mov (r0),r1
|
482 |
|
|
012002 -- mov (r0)+,r2
|
483 |
|
|
012003 -- mov (r0)+,r3
|
484 |
|
|
014004 -- mov -(r0),r4
|
485 |
|
|
013005 -- mov @(r0)+,r5
|
486 |
|
|
000000 -- halt
|
487 |
|
|
#
|
488 |
|
|
wal 002540 -- data:
|
489 |
|
|
bwm 2
|
490 |
|
|
000070 --
|
491 |
|
|
002550 --
|
492 |
|
|
wal 002550 -- data:
|
493 |
|
|
bwm 2
|
494 |
|
|
000072 --
|
495 |
|
|
000074 --
|
496 |
|
|
#
|
497 |
|
|
C Exec code 5 (srcr modes: mov xxx,rn: (r0),(r0)+,-(r0),@(r0))
|
498 |
|
|
#
|
499 |
|
|
wr0 002540 -- r0=2540
|
500 |
|
|
wr1 000000 -- r1=0
|
501 |
|
|
wr2 000000 -- r2=0
|
502 |
|
|
wr3 000000 -- r3=0
|
503 |
|
|
wr4 000000 -- r4=0
|
504 |
|
|
wr5 000000 -- r5=0
|
505 |
|
|
wsp 001400 -- sp=1400
|
506 |
|
|
stapc 002500 -- start @ 2500
|
507 |
|
|
wtgo
|
508 |
|
|
rr0 d=002544 -- ! r0
|
509 |
|
|
rr1 d=000070 -- ! r1
|
510 |
|
|
rr2 d=000070 -- ! r2
|
511 |
|
|
rr3 d=002550 -- ! r3
|
512 |
|
|
rr4 d=002550 -- ! r4
|
513 |
|
|
rr5 d=000072 -- ! r5
|
514 |
|
|
rsp d=001400 -- ! sp
|
515 |
|
|
rpc d=002514 -- ! pc
|
516 |
|
|
#-----------------------------------------------------------------------------
|
517 |
|
|
C Setup code 6 [base 2600] (srcr modes: mov xxx,rn: x(r0),@x(r0), pc modes)
|
518 |
|
|
#
|
519 |
|
|
wal 002600 -- code:
|
520 |
|
|
bwm 11
|
521 |
|
|
016001 -- mov 2(r0),r1
|
522 |
|
|
000002
|
523 |
|
|
017002 -- mov @2(r0),r2
|
524 |
|
|
000002
|
525 |
|
|
012703 -- mov (pc)+,r3 ; #377
|
526 |
|
|
000377
|
527 |
|
|
013704 -- mov @(pc)+,r4 ; @#2552 (in previous code !)
|
528 |
|
|
002552
|
529 |
|
|
#2620
|
530 |
|
|
112705 -- movb (pc)+,r5 ; #377
|
531 |
|
|
000377
|
532 |
|
|
000000 -- halt
|
533 |
|
|
#
|
534 |
|
|
C Exec code 6 (srcr modes: mov xxx,rn: x(r0),@x(r0), pc modes)
|
535 |
|
|
#
|
536 |
|
|
wr0 002540 -- r0=2540 (in previous code !)
|
537 |
|
|
wr1 000000 -- r1=0
|
538 |
|
|
wr2 000000 -- r2=0
|
539 |
|
|
wr3 000000 -- r3=0
|
540 |
|
|
wr4 000000 -- r4=0
|
541 |
|
|
wr5 000000 -- r5=0
|
542 |
|
|
wsp 001400 -- sp=1400
|
543 |
|
|
stapc 002600 -- start @ 2600
|
544 |
|
|
wtgo
|
545 |
|
|
rr0 d=002540 -- ! r0
|
546 |
|
|
rr1 d=002550 -- ! r1
|
547 |
|
|
rr2 d=000072 -- ! r2
|
548 |
|
|
rr3 d=000377 -- ! r3
|
549 |
|
|
rr4 d=000074 -- ! r4
|
550 |
|
|
rr5 d=177777 -- ! r5
|
551 |
|
|
rsp d=001400 -- ! sp
|
552 |
|
|
rpc d=002626 -- ! pc
|
553 |
|
|
#-----------------------------------------------------------------------------
|
554 |
|
|
C Setup code 7 [base 2700] (dstw modes: mov rn,xxx: all non-r modes)
|
555 |
|
|
#
|
556 |
|
|
wal 002700 -- code:
|
557 |
|
|
bwm 18
|
558 |
|
|
012710 -- mov #110,(r0) (to 2750)
|
559 |
|
|
000110
|
560 |
|
|
012721 -- mov #120,(r1)+ (to 2752)
|
561 |
|
|
000120
|
562 |
|
|
012732 -- mov #130,@(r2)+ (to 2754)
|
563 |
|
|
000130
|
564 |
|
|
012743 -- mov #140,-(r3) (to 2756)
|
565 |
|
|
000140
|
566 |
|
|
#2720
|
567 |
|
|
012754 -- mov #150,@-(r4) (to 2760)
|
568 |
|
|
000150
|
569 |
|
|
012760 -- mov #160,12(r0) (to 2762)
|
570 |
|
|
000160
|
571 |
|
|
000012
|
572 |
|
|
012770 -- mov #170,@24(r0) (to 2764)
|
573 |
|
|
000170
|
574 |
|
|
000024
|
575 |
|
|
#2740
|
576 |
|
|
010546 -- mov r5,-(r6)
|
577 |
|
|
000000 -- halt
|
578 |
|
|
#
|
579 |
|
|
wal 002770 -- data:
|
580 |
|
|
bwm 3
|
581 |
|
|
002754 -- mem(2770)=2754
|
582 |
|
|
002760 -- mem(2772)=2760
|
583 |
|
|
002764 -- mem(2774)=2764
|
584 |
|
|
#
|
585 |
|
|
C Exec code 7 (dstw modes: mov rn,xxx: all non-r modes)
|
586 |
|
|
#
|
587 |
|
|
wr0 002750 -- r0=2750
|
588 |
|
|
wr1 002752 -- r1=2752
|
589 |
|
|
wr2 002770 -- r2=2770
|
590 |
|
|
wr3 002760 -- r3=2760
|
591 |
|
|
wr4 002774 -- r4=2774
|
592 |
|
|
wr5 000666 -- r5=666
|
593 |
|
|
wsp 001400 -- sp=1400
|
594 |
|
|
stapc 002700 -- start @ 2700
|
595 |
|
|
wtgo
|
596 |
|
|
rr0 d=002750 -- ! r0
|
597 |
|
|
rr1 d=002754 -- ! r1
|
598 |
|
|
rr2 d=002772 -- ! r2
|
599 |
|
|
rr3 d=002756 -- ! r3
|
600 |
|
|
rr4 d=002772 -- ! r4
|
601 |
|
|
rr5 d=000666 -- ! r5
|
602 |
|
|
rsp d=001376 -- ! sp
|
603 |
|
|
rpc d=002744 -- ! pc
|
604 |
|
|
wal 002750
|
605 |
|
|
brm 7
|
606 |
|
|
d=000110 -- ! mem(2750)=110
|
607 |
|
|
d=000120 -- ! mem(2752)=120
|
608 |
|
|
d=000130 -- ! mem(2754)=130
|
609 |
|
|
d=000140 -- ! mem(2756)=140
|
610 |
|
|
d=000150 -- ! mem(2760)=150
|
611 |
|
|
d=000160 -- ! mem(2762)=160
|
612 |
|
|
d=000170 -- ! mem(2764)=170
|
613 |
|
|
wal 001376
|
614 |
|
|
rmi d=000666 -- ! mem(sp)=666
|
615 |
|
|
#-----------------------------------------------------------------------------
|
616 |
|
|
C Setup code 10 [base 3000] (dstm modes: inc xxx: all non-r modes)
|
617 |
|
|
#
|
618 |
|
|
wal 003000 -- code:
|
619 |
|
|
bwm 10
|
620 |
|
|
005210 -- inc (r0) (to 3050)
|
621 |
|
|
005221 -- inc (r1)+ (to 3052)
|
622 |
|
|
005232 -- inc @(r2)+ (to 3054)
|
623 |
|
|
005243 -- inc -(r3) (to 3056)
|
624 |
|
|
005254 -- inc @-(r4) (to 3060)
|
625 |
|
|
005260 -- inc 12(r0) (to 3062)
|
626 |
|
|
000012
|
627 |
|
|
005270 -- inc @24(r0) (to 3064)
|
628 |
|
|
#3020
|
629 |
|
|
000024
|
630 |
|
|
000000 -- halt
|
631 |
|
|
#
|
632 |
|
|
wal 003050 -- data:
|
633 |
|
|
bwm 7
|
634 |
|
|
000110 -- mem(3050)=110
|
635 |
|
|
000120 -- mem(3052)=120
|
636 |
|
|
000130 -- mem(3054)=130
|
637 |
|
|
000140 -- mem(3056)=140
|
638 |
|
|
000150 -- mem(3060)=150
|
639 |
|
|
000160 -- mem(3062)=160
|
640 |
|
|
000170 -- mem(3064)=170
|
641 |
|
|
wal 003070 -- data:
|
642 |
|
|
bwm 3
|
643 |
|
|
003054 -- mem(3070)=3054
|
644 |
|
|
003060 -- mem(3072)=3060
|
645 |
|
|
003064 -- mem(3074)=3064
|
646 |
|
|
#
|
647 |
|
|
C Exec code 10 (dstm modes: inc xxx: all non-r modes)
|
648 |
|
|
#
|
649 |
|
|
wr0 003050 -- r0=3050
|
650 |
|
|
wr1 003052 -- r1=3052
|
651 |
|
|
wr2 003070 -- r2=3070
|
652 |
|
|
wr3 003060 -- r3=3060
|
653 |
|
|
wr4 003074 -- r4=3074
|
654 |
|
|
wsp 001400 -- sp=1400
|
655 |
|
|
stapc 003000 -- start @ 3000
|
656 |
|
|
wtgo
|
657 |
|
|
rr0 d=003050 -- ! r0
|
658 |
|
|
rr1 d=003054 -- ! r1
|
659 |
|
|
rr2 d=003072 -- ! r2
|
660 |
|
|
rr3 d=003056 -- ! r3
|
661 |
|
|
rr4 d=003072 -- ! r4
|
662 |
|
|
rpc d=003024 -- ! pc
|
663 |
|
|
wal 003050
|
664 |
|
|
brm 7
|
665 |
|
|
d=000111 -- ! mem(3050)=111
|
666 |
|
|
d=000121 -- ! mem(3052)=121
|
667 |
|
|
d=000131 -- ! mem(3054)=131
|
668 |
|
|
d=000141 -- ! mem(3056)=141
|
669 |
|
|
d=000151 -- ! mem(3060)=151
|
670 |
|
|
d=000161 -- ! mem(3062)=161
|
671 |
|
|
d=000171 -- ! mem(3064)=171
|
672 |
|
|
#-----------------------------------------------------------------------------
|
673 |
|
|
C Setup code 11 [base 3100; use 31-32] (dsta modes: jsr pc,xxx: all non-r modes)
|
674 |
|
|
#
|
675 |
|
|
wal 003100 -- code:
|
676 |
|
|
bwm 10
|
677 |
|
|
004710 -- jsr pc,(r0) (to 3210) r0->3210
|
678 |
|
|
004721 -- jsr pc,(r1)+ (to 3220) r1->3220
|
679 |
|
|
004732 -- jsr pc,@(r2)+ (to 3230) r2->3140->3230
|
680 |
|
|
004743 -- jsr pc,-(r3) (to 3240) r3->3242
|
681 |
|
|
004754 -- jsr pc,@-(r4) (to 3250) r4->3142->3250
|
682 |
|
|
004760 -- jsr pc,50(r0) (to 3260) r0->3210+50->3260
|
683 |
|
|
000050
|
684 |
|
|
004770 -- jsr pc,@-44(r0) (to 3270) r0->3210-44->3144->3270
|
685 |
|
|
#3120
|
686 |
|
|
177734
|
687 |
|
|
000000 -- halt
|
688 |
|
|
#
|
689 |
|
|
wal 003140 -- data:
|
690 |
|
|
bwm 3
|
691 |
|
|
003230 -- mem(3140)=3230
|
692 |
|
|
003250 -- mem(3142)=3250
|
693 |
|
|
003270 -- mem(3144)=3270
|
694 |
|
|
#
|
695 |
|
|
wal 003210 -- code:
|
696 |
|
|
bwm 28
|
697 |
|
|
012725 -- mov #110,(r5)+
|
698 |
|
|
000110
|
699 |
|
|
000207 -- rts pc
|
700 |
|
|
000000 -- halt
|
701 |
|
|
#3220
|
702 |
|
|
012725 -- mov #120,(r5)+
|
703 |
|
|
000120
|
704 |
|
|
000207 -- rts pc
|
705 |
|
|
000000 -- halt
|
706 |
|
|
012725 -- mov #130,(r5)+
|
707 |
|
|
000130
|
708 |
|
|
000207 -- rts pc
|
709 |
|
|
000000 -- halt
|
710 |
|
|
#3240
|
711 |
|
|
012725 -- mov #140,(r5)+
|
712 |
|
|
000140
|
713 |
|
|
000207 -- rts pc
|
714 |
|
|
000000 -- halt
|
715 |
|
|
012725 -- mov #150,(r5)+
|
716 |
|
|
000150
|
717 |
|
|
000207 -- rts pc
|
718 |
|
|
000000 -- halt
|
719 |
|
|
#3260
|
720 |
|
|
012725 -- mov #160,(r5)+
|
721 |
|
|
000160
|
722 |
|
|
000207 -- rts pc
|
723 |
|
|
000000 -- halt
|
724 |
|
|
012725 -- mov #170,(r5)+
|
725 |
|
|
000170
|
726 |
|
|
000207 -- rts pc
|
727 |
|
|
000000 -- halt
|
728 |
|
|
#
|
729 |
|
|
C Exec code 11 (dsta modes: jsr pc,xxx: all non-r modes)
|
730 |
|
|
#
|
731 |
|
|
wr0 003210 -- r0=3210
|
732 |
|
|
wr1 003220 -- r1=3220
|
733 |
|
|
wr2 003140 -- r2=3140
|
734 |
|
|
wr3 003242 -- r3=3242
|
735 |
|
|
wr4 003144 -- r4=3144
|
736 |
|
|
wr5 003160 -- r5=3160
|
737 |
|
|
wsp 001400 -- sp=1400
|
738 |
|
|
stapc 003100 -- start @ 3100
|
739 |
|
|
wtgo
|
740 |
|
|
rr0 d=003210 -- ! r0=3210
|
741 |
|
|
rr1 d=003222 -- ! r1=3222
|
742 |
|
|
rr2 d=003142 -- ! r2=3142
|
743 |
|
|
rr3 d=003240 -- ! r3=3240
|
744 |
|
|
rr4 d=003142 -- ! r4=3142
|
745 |
|
|
rr5 d=003176 -- ! r5=3176
|
746 |
|
|
rsp d=001400 -- ! sp
|
747 |
|
|
rpc d=003124 -- ! pc
|
748 |
|
|
wal 003160
|
749 |
|
|
brm 7
|
750 |
|
|
d=000110 -- ! mem(3160)=110
|
751 |
|
|
d=000120 -- ! mem(3162)=120
|
752 |
|
|
d=000130 -- ! mem(3164)=130
|
753 |
|
|
d=000140 -- ! mem(3166)=140
|
754 |
|
|
d=000150 -- ! mem(3170)=150
|
755 |
|
|
d=000160 -- ! mem(3172)=160
|
756 |
|
|
d=000170 -- ! mem(3174)=170
|
757 |
|
|
#-----------------------------------------------------------------------------
|
758 |
|
|
C Setup code 12 [base 3300; use 33-34] (PSW access via sex,clx,spl,mov, and clr)
|
759 |
|
|
#
|
760 |
|
|
wal 003300 -- code:
|
761 |
|
|
bwm 23
|
762 |
|
|
011025 -- mov (r0),(r5)+
|
763 |
|
|
012710 -- mov #030000,(r0) ; write full PSW: pmode=um
|
764 |
|
|
030000
|
765 |
|
|
011025 -- mov (r0),(r5)+
|
766 |
|
|
000263 -- se(v,c)
|
767 |
|
|
011025 -- mov (r0),(r5)+
|
768 |
|
|
000237 -- spl 7
|
769 |
|
|
011025 -- mov (r0),(r5)+
|
770 |
|
|
#3320
|
771 |
|
|
000274 -- se(n,z)
|
772 |
|
|
011025 -- mov (r0),(r5)+
|
773 |
|
|
000233 -- spl 3
|
774 |
|
|
011025 -- mov (r0),(r5)+
|
775 |
|
|
000241 -- clc
|
776 |
|
|
011025 -- mov (r0),(r5)+
|
777 |
|
|
112710 -- movb #40,(r0) ; write PSW_low (set pri=1)
|
778 |
|
|
000040
|
779 |
|
|
#3340
|
780 |
|
|
011025 -- mov (r0),(r5)+
|
781 |
|
|
112711 -- movb #20,(r1) ; write PSW_high: pmode=sm
|
782 |
|
|
000020
|
783 |
|
|
011025 -- mov (r0),(r5)+
|
784 |
|
|
005010 -- clr (r0)
|
785 |
|
|
011025 -- mov (r0),(r5)+
|
786 |
|
|
000000 -- halt
|
787 |
|
|
#
|
788 |
|
|
C Exec code 12 (PSW access via sex,clx,spl,mov, and clr)
|
789 |
|
|
#
|
790 |
|
|
wps 000017 -- psw: set all condition codes (to check psw clear @ start)
|
791 |
|
|
#
|
792 |
|
|
wr0 177776 -- r0=177776
|
793 |
|
|
wr1 177777 -- r1=177777
|
794 |
|
|
wr5 003400 -- r5=3400
|
795 |
|
|
wsp 001400 -- sp=1400
|
796 |
|
|
stapc 003300 -- start @ 3300
|
797 |
|
|
wtgo
|
798 |
|
|
rr5 d=003424 -- ! r5=3424
|
799 |
|
|
rpc d=003356 -- ! pc
|
800 |
|
|
wal 003400
|
801 |
|
|
brm 10
|
802 |
|
|
d=000340 -- ! mem(3400) after start
|
803 |
|
|
d=030000 -- ! mem(3402) after mov #030000,(r0)
|
804 |
|
|
d=030003 -- ! mem(3404) after se(v,c) (VC)
|
805 |
|
|
d=030341 -- ! mem(3406) after spl 7 (pri=7,C)
|
806 |
|
|
d=030355 -- ! mem(3410) after se(n,z) (pri=7,NZC)
|
807 |
|
|
d=030141 -- ! mem(3412) after spl 3 (pri=3,C)
|
808 |
|
|
d=030140 -- ! mem(3414) after clc (pri=3)
|
809 |
|
|
d=030040 -- ! mem(3416) after movb #40,(r0) (pri=1)
|
810 |
|
|
d=010040 -- ! mem(3420) after movb #20,(r1) pmode=sm
|
811 |
|
|
d=000000 -- ! mem(3422) after clr (r0)
|
812 |
|
|
#-----------------------------------------------------------------------------
|
813 |
|
|
C Setup code 13 [base 3500] (test WAIT and rdma (bwm/rwm while CPU running)
|
814 |
|
|
#
|
815 |
|
|
#[[off]] - can't emulate 'sto' command in simh, rdma meaningless in simh
|
816 |
|
|
#
|
817 |
|
|
wal 003500 -- code 13.1 (to be stepped)
|
818 |
|
|
bwm 4
|
819 |
|
|
000001 -- wait
|
820 |
|
|
000001 -- wait
|
821 |
|
|
000001 -- wait
|
822 |
|
|
000000 -- halt
|
823 |
|
|
#
|
824 |
|
|
wal 003520 -- code 13.2 (busy loop)
|
825 |
|
|
bwm 3
|
826 |
|
|
005700 -- tst r0
|
827 |
|
|
001776 -- beq .-1
|
828 |
|
|
000000 -- halt
|
829 |
|
|
#
|
830 |
|
|
wal 003540 -- code 13.3 (just a WAIT)
|
831 |
|
|
bwm 2
|
832 |
|
|
000001 -- wait
|
833 |
|
|
000000 -- halt
|
834 |
|
|
#
|
835 |
|
|
C Exec code 13.1a (run WAIT)
|
836 |
|
|
#
|
837 |
|
|
stapc 003500 -- start @ 3500
|
838 |
|
|
.wait 20 -- let it go
|
839 |
|
|
rpc d=003502 -- ! should hang here ...
|
840 |
|
|
.wait 20 -- let it go
|
841 |
|
|
rpc d=003502 -- ! should hang here ...
|
842 |
|
|
sto
|
843 |
|
|
wtlam d=000001 -- harvest attn due to go 1->0 transition of sto command
|
844 |
|
|
rpc d=003502 -- ! should stay there ...
|
845 |
|
|
#
|
846 |
|
|
C Exec code 13.1b (step WAIT)
|
847 |
|
|
wpc 003500 -- pc=3500
|
848 |
|
|
step -- step over 1st WAIT
|
849 |
|
|
rpc d=003502 -- !
|
850 |
|
|
step -- step over 2nd WAIT
|
851 |
|
|
rpc d=003504 -- !
|
852 |
|
|
step -- step over 3rd WAIT
|
853 |
|
|
rpc d=003506 -- !
|
854 |
|
|
step -- step over HALT
|
855 |
|
|
rpc d=003510 -- !
|
856 |
|
|
#
|
857 |
|
|
C Exec code 13.2 (test bwm/brm while CPU busy looping)
|
858 |
|
|
wr0 000000 -- r0=0
|
859 |
|
|
stapc 003520 -- start @ 3520
|
860 |
|
|
#
|
861 |
|
|
wal 003560 -- write data while CPU active
|
862 |
|
|
bwm 8
|
863 |
|
|
003560
|
864 |
|
|
003562
|
865 |
|
|
003564
|
866 |
|
|
003566
|
867 |
|
|
003570
|
868 |
|
|
003572
|
869 |
|
|
003574
|
870 |
|
|
003576
|
871 |
|
|
wal 003560 -- read data while CPU active
|
872 |
|
|
brm 8
|
873 |
|
|
d=003560
|
874 |
|
|
d=003562
|
875 |
|
|
d=003564
|
876 |
|
|
d=003566
|
877 |
|
|
d=003570
|
878 |
|
|
d=003572
|
879 |
|
|
d=003574
|
880 |
|
|
d=003576
|
881 |
|
|
#
|
882 |
|
|
wr0 000001 -- r0=1 --> should end loop
|
883 |
|
|
wtgo
|
884 |
|
|
rpc d=003526 -- !
|
885 |
|
|
#
|
886 |
|
|
C Exec code 13.3 (test bwm/brm while CPU on WAIT)
|
887 |
|
|
#
|
888 |
|
|
stapc 003540 -- start @ 3540
|
889 |
|
|
#
|
890 |
|
|
wal 003560 -- write data while CPU active
|
891 |
|
|
bwm 8
|
892 |
|
|
073560
|
893 |
|
|
073562
|
894 |
|
|
073564
|
895 |
|
|
073566
|
896 |
|
|
073570
|
897 |
|
|
073572
|
898 |
|
|
073574
|
899 |
|
|
073576
|
900 |
|
|
wal 003560 -- read data while CPU active
|
901 |
|
|
brm 8
|
902 |
|
|
d=073560
|
903 |
|
|
d=073562
|
904 |
|
|
d=073564
|
905 |
|
|
d=073566
|
906 |
|
|
d=073570
|
907 |
|
|
d=073572
|
908 |
|
|
d=073574
|
909 |
|
|
d=073576
|
910 |
|
|
#
|
911 |
|
|
sto
|
912 |
|
|
wtlam d=000001 -- harvest attn due to go 1->0 transition of sto command
|
913 |
|
|
rpc d=003542 -- !
|
914 |
|
|
#[[on]]
|
915 |
|
|
#-----------------------------------------------------------------------------
|
916 |
|
|
# Setup code 14 --- code 14 doesn't exist anymore...
|
917 |
|
|
#-----------------------------------------------------------------------------
|
918 |
|
|
C Setup code 15 [base 3600; use 36-37] (test 4 traps)
|
919 |
|
|
#
|
920 |
|
|
wal 003600 -- code:
|
921 |
|
|
bwm 5
|
922 |
|
|
000003 -- bpt (to 14)
|
923 |
|
|
000004 -- iot (to 20)
|
924 |
|
|
104077 -- emt 77 (to 30)
|
925 |
|
|
104477 -- trap 77 (to 34)
|
926 |
|
|
000000 -- halt
|
927 |
|
|
#
|
928 |
|
|
wal 003620 -- code: trap handlers
|
929 |
|
|
bwm 11
|
930 |
|
|
010025 -- mov r0,(r5)+ (@ 3620)
|
931 |
|
|
000405 -- br .+10
|
932 |
|
|
010125 -- mov r1,(r5)+ (@ 3624)
|
933 |
|
|
000403 -- br .+6
|
934 |
|
|
010225 -- mov r2,(r5)+ (@ 3630)
|
935 |
|
|
000401 -- br .+2
|
936 |
|
|
010325 -- mov r3,(r5)+ (@ 3634)
|
937 |
|
|
#3640
|
938 |
|
|
011604 -- mov (sp),r4 ; r4 points after instruction
|
939 |
|
|
016425 -- mov -2(r4),(r5)+ ; load instruction
|
940 |
|
|
177776
|
941 |
|
|
000002 -- rti
|
942 |
|
|
#
|
943 |
|
|
wal 000014 -- vector: 14+20
|
944 |
|
|
bwm 4
|
945 |
|
|
003620 -- PC:3620
|
946 |
|
|
000000 -- PS:0
|
947 |
|
|
003624 -- PC:3624
|
948 |
|
|
000000 -- PS:0
|
949 |
|
|
wal 000030 -- vector: 30+34
|
950 |
|
|
bwm 4
|
951 |
|
|
003630 -- PC:3630
|
952 |
|
|
000000 -- PS:0
|
953 |
|
|
003634 -- PC:3634
|
954 |
|
|
000000 -- PS:0
|
955 |
|
|
#
|
956 |
|
|
C Exec code 15 (test 4 traps)
|
957 |
|
|
#
|
958 |
|
|
wr0 000011 -- r0=11
|
959 |
|
|
wr1 000022 -- r1=22
|
960 |
|
|
wr2 000033 -- r2=33
|
961 |
|
|
wr3 000044 -- r3=44
|
962 |
|
|
wr5 003700 -- r5=3700
|
963 |
|
|
wsp 001400 -- sp=140
|
964 |
|
|
stapc 003600 -- start @ 3600
|
965 |
|
|
wtgo
|
966 |
|
|
rr5 d=003720 -- ! r5=3720
|
967 |
|
|
rsp d=001400 -- ! sp
|
968 |
|
|
rpc d=003612 -- ! pc
|
969 |
|
|
wal 003700
|
970 |
|
|
brm 8
|
971 |
|
|
d=000011 -- ! mem(3700)=11
|
972 |
|
|
d=000003 -- ! mem(3702)=3
|
973 |
|
|
d=000022 -- ! mem(3704)=22
|
974 |
|
|
d=000004 -- ! mem(3706)=4
|
975 |
|
|
d=000033 -- ! mem(3710)=33
|
976 |
|
|
d=104077 -- ! mem(3712)=104077
|
977 |
|
|
d=000044 -- ! mem(3714)=44
|
978 |
|
|
d=104477 -- ! mem(3716)=104477
|
979 |
|
|
wal 000014 -- vector: 14+20 -> trap catcher again
|
980 |
|
|
bwm 4
|
981 |
|
|
000016 -- PC:16
|
982 |
|
|
000000 -- PS:0
|
983 |
|
|
000022 -- PC:22
|
984 |
|
|
000000 -- PS:0
|
985 |
|
|
wal 000030 -- vector: 30+34 -> trap catcher again
|
986 |
|
|
bwm 4
|
987 |
|
|
000032 -- PC:32
|
988 |
|
|
000000 -- PS:0
|
989 |
|
|
000036 -- PC:36
|
990 |
|
|
000000 -- PS:0
|
991 |
|
|
#-----------------------------------------------------------------------------
|
992 |
|
|
C Setup code 16 [base 4000] (enable MMU, check ssr1, ssr2 response)
|
993 |
|
|
#
|
994 |
|
|
wal 172516 -- SSR3
|
995 |
|
|
wmi 000002 -- I/D enabled for sm only (to check CRESET)
|
996 |
|
|
wal 177572 -- SSR0
|
997 |
|
|
wmi 000001 -- set enable bit
|
998 |
|
|
#
|
999 |
|
|
wal 004000 -- code (to be single stepped...)
|
1000 |
|
|
bwm 7
|
1001 |
|
|
011105 -- mov (r1),r5
|
1002 |
|
|
012105 -- mov (r1)+,r5
|
1003 |
|
|
014105 -- mov -(r1),r5
|
1004 |
|
|
012122 -- mov (r1)+,(r2)+
|
1005 |
|
|
112105 -- movb (r1)+,r5
|
1006 |
|
|
112721 -- movb #200,(r1)+
|
1007 |
|
|
000200
|
1008 |
|
|
#
|
1009 |
|
|
wal 004030 -- code test 1:
|
1010 |
|
|
wmi 000000 -- halt
|
1011 |
|
|
#
|
1012 |
|
|
wal 004040 -- data:
|
1013 |
|
|
bwm 2
|
1014 |
|
|
000001
|
1015 |
|
|
000300
|
1016 |
|
|
#
|
1017 |
|
|
C Exec code 16 (enable MMU, check ssr1, ssr2 response)
|
1018 |
|
|
#
|
1019 |
|
|
wr1 004040 -- r1=4040
|
1020 |
|
|
wr2 004060 -- r2=4060
|
1021 |
|
|
wsp 001400 -- sp=1400
|
1022 |
|
|
wpc 004000 -- pc=4000
|
1023 |
|
|
step -- step (mov (r1),r5)
|
1024 |
|
|
wal 177572 -- check SSR0/1/2
|
1025 |
|
|
brm 3
|
1026 |
|
|
d=000001 -- ! SSR0: (ena=1)
|
1027 |
|
|
d=000000 -- ! SSR1:
|
1028 |
|
|
d=004000 -- ! SSR2: 4000 (eff. PC)
|
1029 |
|
|
rr1 d=004040 -- ! r1
|
1030 |
|
|
rr5 d=000001 -- ! r5
|
1031 |
|
|
step -- step (mov (r1)+,r5)
|
1032 |
|
|
wal 177572 -- check SSR0/1/2
|
1033 |
|
|
brm 3
|
1034 |
|
|
d=000001 -- ! SSR0: (ena=1)
|
1035 |
|
|
d=000021 -- ! SSR1: rb none; ra=1,+2
|
1036 |
|
|
d=004002 -- ! SSR2: 4002 (eff. PC)
|
1037 |
|
|
rr1 d=004042 -- ! r1
|
1038 |
|
|
rr5 d=000001 -- ! r5
|
1039 |
|
|
step -- step (mov -(r1),r5)
|
1040 |
|
|
wal 177572 -- check SSR0/1/2
|
1041 |
|
|
brm 3
|
1042 |
|
|
d=000001 -- ! SSR0: (ena=1)
|
1043 |
|
|
d=000361 -- ! SSR1: rb none; ra=1,-2
|
1044 |
|
|
d=004004 -- ! SSR2: 4004 (eff. PC)
|
1045 |
|
|
rr1 d=004040 -- ! r1
|
1046 |
|
|
rr5 d=000001 -- ! r5
|
1047 |
|
|
step -- step (mov (r1)+,(r2)+)
|
1048 |
|
|
wal 177572 -- check SSR0/1/2
|
1049 |
|
|
brm 3
|
1050 |
|
|
d=000001 -- ! SSR0: (ena=1)
|
1051 |
|
|
d=011021 -- ! SSR1: rb=2,2; ra=1,2
|
1052 |
|
|
d=004006 -- ! SSR2: 4006 (eff. PC)
|
1053 |
|
|
rr1 d=004042 -- ! r1
|
1054 |
|
|
rr2 d=004062 -- ! r2
|
1055 |
|
|
step -- step (movb (r1)+,r5)
|
1056 |
|
|
wal 177572 -- check SSR0/1/2
|
1057 |
|
|
brm 3
|
1058 |
|
|
d=000001 -- ! SSR0: (ena=1)
|
1059 |
|
|
d=000011 -- ! SSR1: rb=none; ra=1,1
|
1060 |
|
|
d=004010 -- ! SSR2: 4010 (eff. PC)
|
1061 |
|
|
rr1 d=004043 -- ! r1
|
1062 |
|
|
rr5 d=177700 -- ! r5
|
1063 |
|
|
step -- step (movb #200,(r1)+)
|
1064 |
|
|
wal 177572 -- check SSR0/1/2
|
1065 |
|
|
brm 3
|
1066 |
|
|
d=000001 -- ! SSR0: (ena=1)
|
1067 |
|
|
d=004427 -- ! SSR1: rb=1,1; ra=7,2
|
1068 |
|
|
d=004012 -- ! SSR2: 4012 (eff. PC)
|
1069 |
|
|
rr1 d=004044 -- ! r1
|
1070 |
|
|
#
|
1071 |
|
|
C Exec test 16.1 (check CRESET of PSW, SSR0, SSR3 after start)
|
1072 |
|
|
#
|
1073 |
|
|
wps 000000 -- psw: set pri=0
|
1074 |
|
|
stapc 004030 -- start @ 4030 (just HALT, testing console reset)
|
1075 |
|
|
wtgo
|
1076 |
|
|
rpc d=004032 -- ! pc=4032
|
1077 |
|
|
rps d=000340 -- ! psw: reset by CRESET
|
1078 |
|
|
wal 172516 -- SSR3
|
1079 |
|
|
rmi d=000000 -- ! cleared by CRESET
|
1080 |
|
|
wal 177572 -- SSR0
|
1081 |
|
|
rmi d=000000 -- ! cleared by CRESET
|
1082 |
|
|
#-----------------------------------------------------------------------------
|
1083 |
|
|
C Setup code 17 [base 4100; use 41-46] (basic instruction and cc test)
|
1084 |
|
|
#
|
1085 |
|
|
wal 004100 -- code: (length 70)
|
1086 |
|
|
bwm 32
|
1087 |
|
|
010124 -- mov r1,(r4)+ (#4711, #123456)
|
1088 |
|
|
020124 -- cmp r1,(r4)+ (#4711, #123456)
|
1089 |
|
|
020224 -- cmp r2,(r4)+ (#123456,#4711)
|
1090 |
|
|
020124 -- cmp r1,(r4)+ (#4711, #4711)
|
1091 |
|
|
005024 -- clr (r4)+ (#123456)
|
1092 |
|
|
030124 -- bit r1,(r4)+ (#4711, #11)
|
1093 |
|
|
030124 -- bit r1,(r4)+ (#4711, #66)
|
1094 |
|
|
040124 -- bic r1,(r4)+ (#4711, #123456)
|
1095 |
|
|
#4120
|
1096 |
|
|
050124 -- bis r1,(r4)+ (#4711, #123456)
|
1097 |
|
|
060124 -- add r1,(r4)+ (#4711, #123456)
|
1098 |
|
|
160124 -- sub r1,(r4)+ (#4711, #123456)
|
1099 |
|
|
005124 -- com (r4)+ (#123456)
|
1100 |
|
|
005224 -- inc (r4)+ (#123456)
|
1101 |
|
|
005324 -- dec (r4)+ (#123456)
|
1102 |
|
|
005424 -- neg (r4)+ (#123456)
|
1103 |
|
|
005724 -- tst (r4)+ (#123456)
|
1104 |
|
|
#4140
|
1105 |
|
|
006024 -- ror (r4)+ (#100201) Cin=0; Cout=1
|
1106 |
|
|
006024 -- ror (r4)+ (#002201) Cin=1; Cout=1
|
1107 |
|
|
006124 -- rol (r4)+ (#100200) Cin=1; Cout=1
|
1108 |
|
|
006224 -- asr (r4)+ (#200)
|
1109 |
|
|
006224 -- asr (r4)+ (#100200)
|
1110 |
|
|
006324 -- asl (r4)+ (#200)
|
1111 |
|
|
006324 -- asl (r4)+ (#100200)
|
1112 |
|
|
060124 -- add r1,(r4)+ (#4711, #077777)
|
1113 |
|
|
#4160
|
1114 |
|
|
005524 -- adc (r4)+ (#200)
|
1115 |
|
|
160124 -- sub r1,(r4)+ (#4711, #4700)
|
1116 |
|
|
005624 -- sbc (r4)+ (#200)
|
1117 |
|
|
000324 -- swap (r4)+ (#111000)
|
1118 |
|
|
006724 -- sxt (r4)+ (#111111 with N=1)
|
1119 |
|
|
074124 -- xor r1,(r4)+ (#070707,#4711)
|
1120 |
|
|
006724 -- sxt (r4)+ (#111111 with N=0)
|
1121 |
|
|
000000 -- halt
|
1122 |
|
|
#
|
1123 |
|
|
wal 000014 -- vector: 14
|
1124 |
|
|
bwm 2
|
1125 |
|
|
004270 -- PC:4270
|
1126 |
|
|
000000 -- PS:0
|
1127 |
|
|
#-----
|
1128 |
|
|
wal 004270 -- code: (trap 14):
|
1129 |
|
|
bwm 3
|
1130 |
|
|
016625 -- mov 2(sp),(r5)+
|
1131 |
|
|
000002
|
1132 |
|
|
000006 -- rtt
|
1133 |
|
|
#-----
|
1134 |
|
|
wal 004300 -- data 1: (length 66)
|
1135 |
|
|
bwm 31
|
1136 |
|
|
123456 --
|
1137 |
|
|
123456 --
|
1138 |
|
|
004711 --
|
1139 |
|
|
004711 --
|
1140 |
|
|
123456 --
|
1141 |
|
|
000011 --
|
1142 |
|
|
000066 --
|
1143 |
|
|
123456 --
|
1144 |
|
|
#4320
|
1145 |
|
|
123456 --
|
1146 |
|
|
123456 --
|
1147 |
|
|
123456 --
|
1148 |
|
|
123456 --
|
1149 |
|
|
123456 --
|
1150 |
|
|
123456 --
|
1151 |
|
|
123456 --
|
1152 |
|
|
123456 --
|
1153 |
|
|
#4340
|
1154 |
|
|
100201 --
|
1155 |
|
|
002201 --
|
1156 |
|
|
100200 --
|
1157 |
|
|
000200 --
|
1158 |
|
|
100200 --
|
1159 |
|
|
000200 --
|
1160 |
|
|
100200 --
|
1161 |
|
|
177000 --
|
1162 |
|
|
#4360
|
1163 |
|
|
000200 --
|
1164 |
|
|
004701 --
|
1165 |
|
|
000200 --
|
1166 |
|
|
111000 --
|
1167 |
|
|
111111 --
|
1168 |
|
|
070707 --
|
1169 |
|
|
111111 --
|
1170 |
|
|
#
|
1171 |
|
|
C Exec code 17 (basic instruction and cc test)
|
1172 |
|
|
#
|
1173 |
|
|
wr1 004711 -- r1=4711
|
1174 |
|
|
wr2 123456 -- r2=123456
|
1175 |
|
|
wr4 004300 -- r4=4300
|
1176 |
|
|
wr5 004500 -- r5=4500
|
1177 |
|
|
wsp 001374 -- sp=1374
|
1178 |
|
|
wal 001374 -- setup stack with rtt return frame setting T flag
|
1179 |
|
|
bwm 2
|
1180 |
|
|
004100 -- start address (code 17 @ 4100)
|
1181 |
|
|
000020 -- set T flag in PSW
|
1182 |
|
|
stapc 004274 -- start @ 4274 -> rtt -> 4100 from stack
|
1183 |
|
|
wtgo
|
1184 |
|
|
rr1 d=004711 -- ! r1=4711
|
1185 |
|
|
rr2 d=123456 -- ! r2=123456
|
1186 |
|
|
rr4 d=004376 -- ! r4=4376
|
1187 |
|
|
rr5 d=004576 -- ! r5=4576
|
1188 |
|
|
rsp d=001400 -- ! sp=1400
|
1189 |
|
|
rpc d=004200 -- ! pc=4200
|
1190 |
|
|
wal 004300
|
1191 |
|
|
brm 31
|
1192 |
|
|
d=004711 -- ! mem(4300)=004711; mov r1,(r4)+ (#4711, #123456)
|
1193 |
|
|
d=123456 -- ! mem(4302)=123456; cmp r1,(r4)+ (#4711, #123456)
|
1194 |
|
|
d=004711 -- ! mem(4304)=004711; cmp r1,(r4)+ (#123456,#4711)
|
1195 |
|
|
d=004711 -- ! mem(4306)=004711; cmp r1,(r4)+ (#4711, #4711)
|
1196 |
|
|
d=000000 -- ! mem(4310)=000000; clr (r4)+ (#123456)
|
1197 |
|
|
d=000011 -- ! mem(4312)=000011; bit r1,(r4)+ (#4711, #11)
|
1198 |
|
|
d=000066 -- ! mem(4314)=000066; bit r1,(r4)+ (#4711, #66)
|
1199 |
|
|
d=123046 -- ! mem(4316)=123046; bic r1,(r4)+ (#4711, #123456)
|
1200 |
|
|
d=127757 -- ! mem(4320)=127757; bis r1,(r4)+ (#4711, #123456)
|
1201 |
|
|
d=130367 -- ! mem(4322)=130367; add r1,(r4)+ (#4711, #123456)
|
1202 |
|
|
d=116545 -- ! mem(4324)=116545; sub r1,(r4)+ (#4711, #123456)
|
1203 |
|
|
d=054321 -- ! mem(4326)=054321; com (r4)+ (#123456)
|
1204 |
|
|
d=123457 -- ! mem(4330)=123457; inc (r4)+ (#123456)
|
1205 |
|
|
d=123455 -- ! mem(4332)=123455; dec (r4)+ (#123456)
|
1206 |
|
|
d=054322 -- ! mem(4334)=054322; neg (r4)+ (#123456)
|
1207 |
|
|
d=123456 -- ! mem(4336)=123456; tst (r4)+ (#123456)
|
1208 |
|
|
d=040100 -- ! mem(4340)=040100; ror (r4)+ (#100201)
|
1209 |
|
|
d=101100 -- ! mem(4342)=101100; ror (r4)+ (#002201)
|
1210 |
|
|
d=000401 -- ! mem(4344)=000401; rol (r4)+ (#100200)
|
1211 |
|
|
d=000100 -- ! mem(4346)=000100; asr (r4)+ (#200)
|
1212 |
|
|
d=140100 -- ! mem(4350)=140100; asr (r4)+ (#100200)
|
1213 |
|
|
d=000400 -- ! mem(4352)=000400; asl (r4)+ (#200)
|
1214 |
|
|
d=000400 -- ! mem(4354)=000400; asl (r4)+ (#100200)
|
1215 |
|
|
d=003711 -- ! mem(4356)=003711; add r1,(r4)+ (#4711, ,#177000)
|
1216 |
|
|
d=000201 -- ! mem(4360)=000201; adc (r4)+ (#200)
|
1217 |
|
|
d=177770 -- ! mem(4362)=177770; sub r1,(r4)+ (#4711, #4701)
|
1218 |
|
|
d=000177 -- ! mem(4364)=000177; sbc (r4)+ (#200)
|
1219 |
|
|
d=000222 -- ! mem(4366)=000222; swap (r4)+ (#111000)
|
1220 |
|
|
d=177777 -- ! mem(4370)=177777; sxt (r4)+ (#111111)
|
1221 |
|
|
d=074016 -- ! mem(4372)=074016; xor r1,(r4)+ (#070707)
|
1222 |
|
|
d=000000 -- ! mem(4374)=000000; sxt (r4)+ (#111111)
|
1223 |
|
|
#
|
1224 |
|
|
wal 004500 -- NZVC
|
1225 |
|
|
brm 31
|
1226 |
|
|
d=000020 -- ! mem(4500)=0000; mov r1,(r4)+ (#4711, #123456)
|
1227 |
|
|
d=000021 -- ! mem(4502)=000C; cmp r1,(r4)+ (#4711, #123456)
|
1228 |
|
|
d=000030 -- ! mem(4504)=N000; cmp r1,(r4)+ (#123456,#4711)
|
1229 |
|
|
d=000024 -- ! mem(4506)=0Z00; cmp r1,(r4)+ (#4711, #4711)
|
1230 |
|
|
d=000024 -- ! mem(4510)=0Z00; clr (r4)+ (#123456)
|
1231 |
|
|
d=000020 -- ! mem(4512)=0000; bit r1,(r4)+ (#4711, #11)
|
1232 |
|
|
d=000024 -- ! mem(4514)=0Z00; bit r1,(r4)+ (#4711, #66)
|
1233 |
|
|
d=000030 -- ! mem(4516)=N000; bic r1,(r4)+ (#4711, #123456)
|
1234 |
|
|
d=000030 -- ! mem(4520)=N000; bis r1,(r4)+ (#4711, #123456)
|
1235 |
|
|
d=000030 -- ! mem(4522)=N000; add r1,(r4)+ (#4711, #123456)
|
1236 |
|
|
d=000030 -- ! mem(4524)=N000; sub r1,(r4)+ (#4711, #123456)
|
1237 |
|
|
d=000021 -- ! mem(4526)=000C; com (r4)+ (#123456)
|
1238 |
|
|
d=000031 -- ! mem(4530)=N00C; inc (r4)+ (#123456) keep C!
|
1239 |
|
|
d=000031 -- ! mem(4532)=N00C; dec (r4)+ (#123456) keep C!
|
1240 |
|
|
d=000021 -- ! mem(4534)=000C; neg (r4)+ (#123456)
|
1241 |
|
|
d=000030 -- ! mem(4536)=N000; tst (r4)+ (#123456)
|
1242 |
|
|
d=000023 -- ! mem(4540)=00VC; ror (r4)+ (#100201)
|
1243 |
|
|
d=000031 -- ! mem(4542)=N00C; ror (r4)+ (#002201)
|
1244 |
|
|
d=000023 -- ! mem(4544)=00VC; rol (r4)+ (#100200)
|
1245 |
|
|
d=000020 -- ! mem(4546)=0000; asr (r4)+ (#200)
|
1246 |
|
|
d=000032 -- ! mem(4550)=N0V0; asr (r4)+ (#100200)
|
1247 |
|
|
d=000020 -- ! mem(4552)=0000; asl (r4)+ (#200)
|
1248 |
|
|
d=000023 -- ! mem(4554)=00VC; asl (r4)+ (#100200)
|
1249 |
|
|
d=000021 -- ! mem(4556)=000C; add r1,(r4)+ (#4711, ,#177000)
|
1250 |
|
|
d=000020 -- ! mem(4560)=0000; adc (r4)+ (#200)
|
1251 |
|
|
d=000031 -- ! mem(4562)=N00C; sub r1,(r4)+ (#4711, #4701)
|
1252 |
|
|
d=000020 -- ! mem(4564)=0000; sbc (r4)+ (#200)
|
1253 |
|
|
d=000030 -- ! mem(4566)=N000; swap (r4)+ (#111000)
|
1254 |
|
|
d=000030 -- ! mem(4570)=N000; sxt (r4)+ (#111111 with N=1)
|
1255 |
|
|
d=000020 -- ! mem(4572)=0000; xor r1,(r4)+ (#4711, #070707)
|
1256 |
|
|
d=000024 -- ! mem(4574)=0Z00; sxt (r4)+ (#111111 with N=0)
|
1257 |
|
|
#
|
1258 |
|
|
rst -- console reset (to clear T flag)
|
1259 |
|
|
wal 000014 -- vector: 14 -> trap catcher again
|
1260 |
|
|
bwm 2
|
1261 |
|
|
000016 -- PC:16
|
1262 |
|
|
000000 -- PS:0
|
1263 |
|
|
#-----------------------------------------------------------------------------
|
1264 |
|
|
C Setup code 20 [base 4700] (check CPUERR and error handling)
|
1265 |
|
|
#[[off]]
|
1266 |
|
|
wal 004700 -- code (to be single stepped...)
|
1267 |
|
|
bwm 11
|
1268 |
|
|
010025 -- mov r0,(r5)+ (@ 4777)
|
1269 |
|
|
010025 -- mov r0,(r5)+ (@ 150000)
|
1270 |
|
|
010025 -- mov r0,(r5)+ (@ 160000)
|
1271 |
|
|
000101 -- jmp r1
|
1272 |
|
|
004701 -- jsr pc,r1
|
1273 |
|
|
000000 -- halt
|
1274 |
|
|
014321 -- mov -(r3),(r1)+ (@ 20000)
|
1275 |
|
|
024321 -- cmp -(r3),(r1)+ (@ 20400)
|
1276 |
|
|
#4720
|
1277 |
|
|
064321 -- add -(r3),(r1)+ (@ 20000)
|
1278 |
|
|
010046 -- mov r0,-(sp) (@ 340)
|
1279 |
|
|
000004 -- iot (with sp=342,...)
|
1280 |
|
|
#
|
1281 |
|
|
wal 000004 -- vector: 4+10 (trap catch)
|
1282 |
|
|
bwm 4
|
1283 |
|
|
000006 -- PC:6
|
1284 |
|
|
000000 -- PS:0
|
1285 |
|
|
000012 -- PC:12
|
1286 |
|
|
000000 -- PS:0
|
1287 |
|
|
#----------
|
1288 |
|
|
C Exec code 20 (check CPUERR and error handling)
|
1289 |
|
|
C Exec test 20.1 (odd address abort)
|
1290 |
|
|
rst -- console reset
|
1291 |
|
|
wps 000000 -- psw: clear
|
1292 |
|
|
wal 001374 -- clean stack
|
1293 |
|
|
bwm 2
|
1294 |
|
|
000000 --
|
1295 |
|
|
000000 --
|
1296 |
|
|
wal 177766 -- check initial CPUERR (=0!)
|
1297 |
|
|
rm d=000000 -- !
|
1298 |
|
|
wr0 000011 -- r0=11
|
1299 |
|
|
wr5 004775 -- r5=4775
|
1300 |
|
|
wsp 001400 -- sp=1400
|
1301 |
|
|
wpc 004700 -- pc=4700
|
1302 |
|
|
step -- step (mov r0,(r5)+): trap 4 + CPUERR.adderr set [[s:2]]
|
1303 |
|
|
rpc d=000006 -- ! pc=6 (trap 4 catch)
|
1304 |
|
|
rsp d=001374 -- ! sp=1374
|
1305 |
|
|
wal 001374 -- check stack
|
1306 |
|
|
brm 2
|
1307 |
|
|
d=004702 -- ! pc=4702
|
1308 |
|
|
d=000000 -- ! ps=0
|
1309 |
|
|
wal 177766 -- check CPUERR
|
1310 |
|
|
rm d=000100 -- ! CPUERR: (adderr=1)
|
1311 |
|
|
wm 000000 -- any write access will clear CPUERR
|
1312 |
|
|
rm d=000000 -- ! CPUERR: 0
|
1313 |
|
|
#----------
|
1314 |
|
|
C Exec test 20.2 (non-existent memory abort)
|
1315 |
|
|
wal 172354 -- kernel I space AR(6)
|
1316 |
|
|
wm 177400 -- (map to 8 k below I/O page, never available in w11a)
|
1317 |
|
|
wal 177572 -- SSR0
|
1318 |
|
|
wmi 000001 -- enable
|
1319 |
|
|
wal 172516 -- SSR3
|
1320 |
|
|
wmi 000020 -- ena_22bit=1
|
1321 |
|
|
#
|
1322 |
|
|
wr5 140000 -- r5=140000
|
1323 |
|
|
wsp 001400 -- sp=1400
|
1324 |
|
|
wpc 004702 -- pc=4702
|
1325 |
|
|
step -- step (mov r0,(r5)+): trap 4 + CPUERR.nxm set [[s:2]]
|
1326 |
|
|
rpc d=000006 -- ! pc= 6 (trap 4 catch)
|
1327 |
|
|
rsp d=001374 -- ! sp=1374
|
1328 |
|
|
wal 177766 -- check CPUERR
|
1329 |
|
|
rm d=000040 -- ! CPUERR: (nxm=1)
|
1330 |
|
|
wm 000000 -- any write access will clear CPUERR
|
1331 |
|
|
rm d=000000 -- ! CPUERR: 0
|
1332 |
|
|
#
|
1333 |
|
|
wal 177572 -- SSR0
|
1334 |
|
|
wmi 000000 -- disable
|
1335 |
|
|
wal 172354 -- kernel I space AR(6)
|
1336 |
|
|
wm 001400 -- 1400 140000 base (default 1-to-1 map)
|
1337 |
|
|
#----------
|
1338 |
|
|
C Exec test 20.3 (I/O bus timeout abort)
|
1339 |
|
|
wr5 160000 -- r5=160000
|
1340 |
|
|
wsp 001400 -- sp=1400
|
1341 |
|
|
wpc 004704 -- pc=4704
|
1342 |
|
|
step -- step (mov r0,(r5)+): trap 4 + CPUERR.iobto set [[s:2]]
|
1343 |
|
|
rpc d=000006 -- ! pc= 6 (trap 4 catch)
|
1344 |
|
|
rsp d=001374 -- ! sp=1374
|
1345 |
|
|
wal 177766 -- check CPUERR
|
1346 |
|
|
rm d=000020 -- ! CPUERR: (iobto=1)
|
1347 |
|
|
wm 000000 -- clear CPUERR
|
1348 |
|
|
#----------
|
1349 |
|
|
C Exec test 20.4 (address error abort after jmp r1)
|
1350 |
|
|
wsp 001400 -- sp=1400
|
1351 |
|
|
wpc 004706 -- pc=4706
|
1352 |
|
|
step -- step (jmp r1): trap 10 [[s:2]]
|
1353 |
|
|
rpc d=000012 -- ! pc=12 (trap 10 catch)
|
1354 |
|
|
rsp d=001374 -- ! sp=1374
|
1355 |
|
|
wal 177766 -- check CPUERR
|
1356 |
|
|
rm d=000000 -- ! CPUERR: none
|
1357 |
|
|
wm 000000 -- clear CPUERR
|
1358 |
|
|
#----------
|
1359 |
|
|
C Exec test 20.5 (address error abort after jsr pc,r1)
|
1360 |
|
|
wsp 001400 -- sp=1400
|
1361 |
|
|
wpc 004710 -- pc=4710
|
1362 |
|
|
step -- step (jsr pc,r1): trap 10 [[s:2]]
|
1363 |
|
|
rpc d=000012 -- ! pc=12 (trap 10 catch)
|
1364 |
|
|
rsp d=001374 -- ! sp=1374
|
1365 |
|
|
wal 177766 -- check CPUERR
|
1366 |
|
|
rm d=000000 -- ! CPUERR: none
|
1367 |
|
|
wm 000000 -- clear CPUERR
|
1368 |
|
|
#----------
|
1369 |
|
|
C Exec test 20.6 (halt in user mode)
|
1370 |
|
|
wsp 001400 -- sp=1400 (kernel)
|
1371 |
|
|
wpc 004712 -- pc=4712
|
1372 |
|
|
wps 170000 -- psw: cmode=pmode=11 (user)
|
1373 |
|
|
step -- step (halt): trap 4 + CPUERR.illhlt set [[s:2]]
|
1374 |
|
|
rpc d=000006 -- ! pc=6 (trap 4 catch)
|
1375 |
|
|
rsp d=001374 -- ! sp=1374 (now kernel again...)
|
1376 |
|
|
wal 001374 -- check stack
|
1377 |
|
|
brm 2
|
1378 |
|
|
d=004714 -- !
|
1379 |
|
|
d=170000 -- !
|
1380 |
|
|
wal 177766 -- check CPUERR
|
1381 |
|
|
rm d=000200 -- ! CPUERR: (illhlt=1)
|
1382 |
|
|
wm 000000 -- clear CPUERR
|
1383 |
|
|
#
|
1384 |
|
|
wps 000000 -- psw: cmode=pmode=0 (kernel)
|
1385 |
|
|
#----------
|
1386 |
|
|
#
|
1387 |
|
|
# test mmu aborts
|
1388 |
|
|
#
|
1389 |
|
|
wal 000250 -- vector: 250 -> trap catcher
|
1390 |
|
|
bwm 2
|
1391 |
|
|
000252 -- PC:252
|
1392 |
|
|
000000 -- PS:0
|
1393 |
|
|
#
|
1394 |
|
|
wal 177572 -- SSR0
|
1395 |
|
|
wmi 000001 -- enable
|
1396 |
|
|
wal 172302 -- kernel I space DR segment 1 (base 20000)
|
1397 |
|
|
wmi 077400 -- slf=127; ed=0(up); acf=0 (non-resident)
|
1398 |
|
|
#----------
|
1399 |
|
|
C Exec test 20.7 (non resident abort)
|
1400 |
|
|
wr1 020000 -- r1=20000
|
1401 |
|
|
wr3 000016 -- r3=16 ; the -(r3) fetches the mem(14)=16
|
1402 |
|
|
wsp 001400 -- sp=1400
|
1403 |
|
|
wpc 004714 -- pc=4714
|
1404 |
|
|
step -- step (mov -(r3),(r1)+): abort to 250 [[s:2]]
|
1405 |
|
|
rr1 d=020002 -- ! r1=20002 (inc done before trap (here dstw))
|
1406 |
|
|
rr3 d=000014 -- ! r3=16 (dec done before trap)
|
1407 |
|
|
rpc d=000252 -- ! pc=252 (trap 250 catch)
|
1408 |
|
|
rsp d=001374 -- ! sp=1374
|
1409 |
|
|
wal 177572 -- check SSR0/1/2
|
1410 |
|
|
brm 3
|
1411 |
|
|
d=100003 -- ! SSR0: (abo_nonres=1,seg=1,ena=1)
|
1412 |
|
|
d=010763 -- ! SSR1: rb=1,2; ra=3,-2
|
1413 |
|
|
d=004714 -- ! SSR2: 4714 (eff. PC)
|
1414 |
|
|
#
|
1415 |
|
|
wal 177572 -- SSR0
|
1416 |
|
|
wmi 000001 -- enable and clear error bits
|
1417 |
|
|
#----------
|
1418 |
|
|
C Exec test 20.8 (segment length violation abort)
|
1419 |
|
|
wal 172302 -- kernel I space DR segment 1 (base 20000)
|
1420 |
|
|
wmi 001406 -- slf=3; ed=0(up); acf=6 (w/r)
|
1421 |
|
|
#
|
1422 |
|
|
wr1 020400 -- r1=20400
|
1423 |
|
|
wr3 000016 -- r3=16 ; the -(r3) fetches the mem(14)=16
|
1424 |
|
|
wsp 001400 -- sp=1400
|
1425 |
|
|
wpc 004716 -- pc=4716
|
1426 |
|
|
step -- step (cmp -(r3),(r1)+): abort to 250 [[s:2]]
|
1427 |
|
|
rr1 d=020402 -- ! r1=20402 (inc done before trap (here dstr))
|
1428 |
|
|
rr3 d=000014 -- ! r3=16 (dec done before trap)
|
1429 |
|
|
rpc d=000252 -- ! pc=252 (trap 250 catch)
|
1430 |
|
|
rsp d=001374 -- ! sp=1374
|
1431 |
|
|
wal 177572 -- check SSR0/1/2
|
1432 |
|
|
brm 3
|
1433 |
|
|
d=040003 -- ! SSR0: (abo_length=1,seg=1,ena=1)
|
1434 |
|
|
d=010763 -- ! SSR1: rb=1,2; ra=3,-2
|
1435 |
|
|
d=004716 -- ! SSR2: 4716 (eff. PC)
|
1436 |
|
|
#
|
1437 |
|
|
wal 177572 -- SSR0
|
1438 |
|
|
wmi 000001 -- enable and clear error bits
|
1439 |
|
|
#----------
|
1440 |
|
|
C Exec test 20.9 (read-only abort)
|
1441 |
|
|
wal 172302 -- kernel I space DR segment 1 (base 20000)
|
1442 |
|
|
wmi 077402 -- slf=127; ed=0(up); acf=2 (read-only)
|
1443 |
|
|
#
|
1444 |
|
|
wr1 020000 -- r1=20000
|
1445 |
|
|
wr3 000016 -- r3=16 ; the -(r3) fetches the mem(14)=16
|
1446 |
|
|
wsp 001400 -- sp=1400
|
1447 |
|
|
wpc 004720 -- pc=4720
|
1448 |
|
|
step -- step (add -(r3),(r1)+): abort to 250 [[s:2]]
|
1449 |
|
|
rr1 d=020002 -- ! r1=20000 (inc done before trap (here dstm))
|
1450 |
|
|
rr3 d=000014 -- ! r3=16 (dec done before trap)
|
1451 |
|
|
rpc d=000252 -- ! pc=252 (trap 250 catch)
|
1452 |
|
|
rsp d=001374 -- ! sp=1374
|
1453 |
|
|
wal 177572 -- check SSR0/1/2
|
1454 |
|
|
brm 3
|
1455 |
|
|
d=020003 -- ! SSR0: (abo_rdonly=1,seg=1,ena=1)
|
1456 |
|
|
d=010763 -- ! SSR1: rb=1,2; ra=3,-2
|
1457 |
|
|
d=004720 -- ! SSR2: 4720 (eff. PC)
|
1458 |
|
|
#
|
1459 |
|
|
# mmu back to default setup, disable
|
1460 |
|
|
wal 172302 -- kernel I space DR segment 1 (base 20000)
|
1461 |
|
|
wmi 077406 -- slf=127; ed=0(up); acf=6 (r/w)
|
1462 |
|
|
wal 177572 -- SSR0
|
1463 |
|
|
wmi 000000 -- disable
|
1464 |
|
|
#----------
|
1465 |
|
|
#
|
1466 |
|
|
# test mmu trap
|
1467 |
|
|
#
|
1468 |
|
|
wal 177572 -- SSR0
|
1469 |
|
|
wmi 001001 -- enable, trap enable
|
1470 |
|
|
wal 172302 -- kernel I space DR segment 1 (base 20000)
|
1471 |
|
|
wmi 077404 -- slf=127; ed=0(up); acf=4 (r/w, trap on r/w)
|
1472 |
|
|
#----------
|
1473 |
|
|
C Exec test 20.10 (trap on write)
|
1474 |
|
|
wr1 020000 -- r1=20000
|
1475 |
|
|
wr3 000016 -- r3=16 ; the -(r3) fetches the mem(14)=16
|
1476 |
|
|
wsp 001400 -- sp=1400
|
1477 |
|
|
wpc 004714 -- pc=4714
|
1478 |
|
|
step -- step (mov -(r3),(r1)+): trap to 250 [[s:2]]
|
1479 |
|
|
rr1 d=020002 -- ! r1=20002 (inc done before trap)
|
1480 |
|
|
rr3 d=000014 -- ! r3=16 (dec done before trap)
|
1481 |
|
|
rpc d=000252 -- ! pc=252 (trap 250 catch)
|
1482 |
|
|
rsp d=001374 -- ! sp=1374
|
1483 |
|
|
wal 020000 -- check target area
|
1484 |
|
|
rm d=000016 -- ! mem(20000)=16
|
1485 |
|
|
wm 000000 -- clean tainted memory
|
1486 |
|
|
wal 177572 -- check SSR0
|
1487 |
|
|
brm 3
|
1488 |
|
|
d=011001 -- ! SSR0: (trap_mmu=1,ena_trap=1,seg=0,ena=1)
|
1489 |
|
|
d=010763 -- ! SSR1: rb=1,2; ra=3,-2
|
1490 |
|
|
d=004714 -- ! SSR2: 4714 (eff. PC)
|
1491 |
|
|
#----------
|
1492 |
|
|
C Exec test 20.11 (2nd write, should not trap again)
|
1493 |
|
|
wr1 020002 -- r1=20002
|
1494 |
|
|
wr3 000016 -- r3=16 ; the -(r3) fetches the mem(14)=16
|
1495 |
|
|
wsp 001400 -- sp=1400
|
1496 |
|
|
wpc 004714 -- pc=4714
|
1497 |
|
|
step -- step (mov -(r3),(r1)+): no trap [[s:2]]
|
1498 |
|
|
rr1 d=020004 -- ! r1=20004 (inc done before trap)
|
1499 |
|
|
rr3 d=000014 -- ! r3=16 (dec done before trap)
|
1500 |
|
|
rpc d=004716 -- ! pc=252 (trap 250 catch)
|
1501 |
|
|
rsp d=001400 -- ! sp=1374
|
1502 |
|
|
wal 020002 -- check target area
|
1503 |
|
|
rm d=000016 -- ! mem(20002)=16
|
1504 |
|
|
wm 000000 -- clean tainted memory
|
1505 |
|
|
wal 177572 -- check SSR0
|
1506 |
|
|
brm 3
|
1507 |
|
|
d=011003 -- ! SSR0: (trap_mmu=1,ena_trap=1,seg=1,ena=1)
|
1508 |
|
|
d=010763 -- ! SSR1: rb=1,2; ra=3,-2
|
1509 |
|
|
d=004714 -- ! SSR2: 4714 (eff. PC)
|
1510 |
|
|
#
|
1511 |
|
|
# mmu back to default setup, disable
|
1512 |
|
|
wal 172302 -- kernel I space DR segment 1 (base 20000)
|
1513 |
|
|
wmi 077406 -- slf=127; ed=0(up); acf=6 (r/w)
|
1514 |
|
|
wal 177572 -- SSR0
|
1515 |
|
|
wmi 000000 -- disable
|
1516 |
|
|
#----------
|
1517 |
|
|
#
|
1518 |
|
|
# now test stack limit logic
|
1519 |
|
|
#
|
1520 |
|
|
C Exec test 20.12 (red stack abort when pushing data to stack)
|
1521 |
|
|
wr0 123456 -- r0=123456
|
1522 |
|
|
wsp 000340 -- sp=340
|
1523 |
|
|
wpc 004722 -- pc=4722
|
1524 |
|
|
step -- step (mov r0,-(sp)): abort to 4 [[s:2]]
|
1525 |
|
|
rpc d=000006 -- ! pc=6 (trap 4 catch)
|
1526 |
|
|
rsp d=000000 -- ! sp=0
|
1527 |
|
|
wal 000336 -- check that stack wasn't written
|
1528 |
|
|
rm d=000000 -- ! mem(336) untainted
|
1529 |
|
|
wal 000000 -- check emergency stack at 0,2
|
1530 |
|
|
brm 2
|
1531 |
|
|
d=004724 -- ! mem(0): PC
|
1532 |
|
|
d=000010 -- ! mem(2): PS
|
1533 |
|
|
wal 177766 -- check CPUERR
|
1534 |
|
|
rm d=000004 -- ! CPUERR: (rsv=1)
|
1535 |
|
|
wm 000000 -- clear CPUERR
|
1536 |
|
|
#----------
|
1537 |
|
|
C Exec test 20.13 (red stack abort on 2nd word of interrupt/trap push)
|
1538 |
|
|
wps 000017 -- psw: set all cc flags
|
1539 |
|
|
wsp 000342 -- sp=342
|
1540 |
|
|
wpc 004724 -- pc=4724
|
1541 |
|
|
step -- step (iot): abort to 4 [[s:2]]
|
1542 |
|
|
rpc d=000006 -- ! pc=6 (trap 4 catch)
|
1543 |
|
|
rsp d=000000 -- ! sp=0
|
1544 |
|
|
wal 000336 -- check stack
|
1545 |
|
|
brm 2
|
1546 |
|
|
d=000000 -- ! mem(336) untainted
|
1547 |
|
|
d=000017 -- ! mem(340) PS of 1st attempt
|
1548 |
|
|
wal 000000 -- check emergency stack at 0,2
|
1549 |
|
|
brm 2
|
1550 |
|
|
d=004726 -- ! mem(0): PC
|
1551 |
|
|
d=000000 -- ! mem(2): PS (will be 0, orgininal PS lost !!)
|
1552 |
|
|
wal 177766 -- check CPUERR
|
1553 |
|
|
rm d=000004 -- ! CPUERR: (rsv=1)
|
1554 |
|
|
wm 000000 -- clear CPUERR
|
1555 |
|
|
#----------
|
1556 |
|
|
C Exec test 20.14 (yellow stack trap when pushing data to stack; sp=400)
|
1557 |
|
|
wps 000017 -- psw: set all cc flags
|
1558 |
|
|
wr0 123456 -- r0=123456
|
1559 |
|
|
wsp 000400 -- sp=400
|
1560 |
|
|
wpc 004722 -- pc=4722
|
1561 |
|
|
step -- step (mov r0,-(sp)): trap to 4
|
1562 |
|
|
rpc d=000006 -- ! pc=6 (trap 4 catch)
|
1563 |
|
|
rsp d=000372 -- ! sp=372
|
1564 |
|
|
wal 000372 -- check stack
|
1565 |
|
|
brm 3
|
1566 |
|
|
d=004724 -- ! mem(372) PC of trapped instruction
|
1567 |
|
|
d=000011 -- ! mem(374) PS of trapped instruction
|
1568 |
|
|
d=123456 -- ! mem(376) pushed word
|
1569 |
|
|
wal 177766 -- check CPUERR
|
1570 |
|
|
rm d=000010 -- ! CPUERR: (ysv=1)
|
1571 |
|
|
wm 000000 -- clear CPUERR
|
1572 |
|
|
#----------
|
1573 |
|
|
C Exec test 20.15 (yellow stack trap on 2nd word of interrupt/trap push; sp=402)
|
1574 |
|
|
wps 000017 -- psw: set all cc flags
|
1575 |
|
|
wsp 000402 -- sp=402
|
1576 |
|
|
wpc 004724 -- pc=4724
|
1577 |
|
|
step -- step (iot): abort to 4 [[s:2]]
|
1578 |
|
|
rpc d=000006 -- ! pc=6 (trap 4 catch)
|
1579 |
|
|
rsp d=000372 -- ! sp=372
|
1580 |
|
|
wal 000372 -- check stack
|
1581 |
|
|
brm 4
|
1582 |
|
|
d=000022 -- ! mem(372) PC of IOT handler
|
1583 |
|
|
d=000000 -- ! mem(374) PS of IOT handler
|
1584 |
|
|
d=004726 -- ! mem(376) PC of IOT trap
|
1585 |
|
|
d=000017 -- ! mem(400) PS of IOT trap
|
1586 |
|
|
wal 177766 -- check CPUERR
|
1587 |
|
|
rm d=000010 -- ! CPUERR: (ysv=1)
|
1588 |
|
|
wm 000000 -- clear CPUERR
|
1589 |
|
|
#----------
|
1590 |
|
|
# now test red stack escalation
|
1591 |
|
|
#
|
1592 |
|
|
C Exec test 20.16 (red stack escalation: abort kernel stack odd; sp=1001)
|
1593 |
|
|
wr0 123456 -- r0=123456
|
1594 |
|
|
wsp 001001 -- sp=1001
|
1595 |
|
|
wpc 004722 -- pc=4722
|
1596 |
|
|
step -- step (mov r0,-(sp)): abort to 4 [[s:2]]
|
1597 |
|
|
rpc d=000006 -- ! pc=6 (trap 4 catch)
|
1598 |
|
|
rsp d=000000 -- ! sp=0
|
1599 |
|
|
wal 000000 -- check emergency stack at 0,2
|
1600 |
|
|
brm 2
|
1601 |
|
|
d=004724 -- ! mem(0): PC
|
1602 |
|
|
d=000010 -- ! mem(2): PS
|
1603 |
|
|
wal 177766 -- check CPUERR
|
1604 |
|
|
rm d=000104 -- ! CPUERR: (rsv=1,adderr=1)
|
1605 |
|
|
wm 000000 -- clear CPUERR
|
1606 |
|
|
#----------
|
1607 |
|
|
C Exec test 20.17 (red stack escalation: abort kernel stack in non-mem)
|
1608 |
|
|
wal 172354 -- kernel I space AR(6)
|
1609 |
|
|
wm 177400 -- (map to 8 k below I/O page, never available in w11a)
|
1610 |
|
|
wal 177572 -- SSR0
|
1611 |
|
|
wmi 000001 -- enable
|
1612 |
|
|
wal 172516 -- SSR3
|
1613 |
|
|
wmi 000020 -- ena_22bit=1
|
1614 |
|
|
#
|
1615 |
|
|
wr0 123456 -- r0=123456
|
1616 |
|
|
wsp 140004 -- sp=140004
|
1617 |
|
|
wpc 004722 -- pc=4722
|
1618 |
|
|
step -- step (mov r0,-(sp)): abort to 4 [[s:2]]
|
1619 |
|
|
rpc d=000006 -- ! pc=6 (trap 4 catch)
|
1620 |
|
|
rsp d=000000 -- ! sp=0
|
1621 |
|
|
wal 000000 -- check emergency stack at 0,2
|
1622 |
|
|
brm 2
|
1623 |
|
|
d=004724 -- ! mem(0): PC
|
1624 |
|
|
d=000010 -- ! mem(2): PS
|
1625 |
|
|
wal 177766 -- check CPUERR
|
1626 |
|
|
rm d=000044 -- ! CPUERR: (rsv=1,nxm=1)
|
1627 |
|
|
wm 000000 -- clear CPUERR
|
1628 |
|
|
#
|
1629 |
|
|
wal 177572 -- SSR0
|
1630 |
|
|
wmi 000000 -- disable
|
1631 |
|
|
wal 172354 -- kernel I space AR(6)
|
1632 |
|
|
wm 001400 -- 1400 140000 base (default 1-to-1 map)
|
1633 |
|
|
#----------
|
1634 |
|
|
C Exec test 20.18 (red stack escalation: abort kernel stack iob-to;sp=160004)
|
1635 |
|
|
wr0 123456 -- r0=123456
|
1636 |
|
|
wsp 160004 -- sp=160004
|
1637 |
|
|
wpc 004722 -- pc=4722
|
1638 |
|
|
step -- step (mov r0,-(sp)): abort to 4 [[s:2]]
|
1639 |
|
|
rpc d=000006 -- ! pc=6 (trap 4 catch)
|
1640 |
|
|
rsp d=000000 -- ! sp=0
|
1641 |
|
|
wal 000000 -- check emergency stack at 0,2
|
1642 |
|
|
brm 2
|
1643 |
|
|
d=004724 -- ! mem(0): PC
|
1644 |
|
|
d=000010 -- ! mem(2): PS
|
1645 |
|
|
wal 177766 -- check CPUERR
|
1646 |
|
|
rm d=000024 -- ! CPUERR: (rsv=1,iobto=1)
|
1647 |
|
|
wm 000000 -- clear CPUERR
|
1648 |
|
|
#----------
|
1649 |
|
|
C Exec test 20.19 (red stack escalation: abort kernel stack mmu abort;sp=020004)
|
1650 |
|
|
#
|
1651 |
|
|
wal 177572 -- SSR0
|
1652 |
|
|
wmi 000001 -- enable
|
1653 |
|
|
wal 172302 -- kernel I space DR segment 1 (base 20000)
|
1654 |
|
|
wmi 077400 -- slf=127; ed=0(up); acf=0 (non-resident)
|
1655 |
|
|
#
|
1656 |
|
|
wr0 123456 -- r0=123456
|
1657 |
|
|
wsp 020004 -- sp=020004
|
1658 |
|
|
wpc 004722 -- pc=4722
|
1659 |
|
|
step -- step (mov r0,-(sp)): abort to 4 [[s:2]]
|
1660 |
|
|
rpc d=000006 -- ! pc=6 (trap 4 catch)
|
1661 |
|
|
rsp d=000000 -- ! sp=0
|
1662 |
|
|
wal 020002 -- check that stack wasn't written
|
1663 |
|
|
rm d=000000 -- ! mem(20002) untainted
|
1664 |
|
|
wal 000000 -- check emergency stack at 0,2
|
1665 |
|
|
brm 2
|
1666 |
|
|
d=004724 -- ! mem(0): PC
|
1667 |
|
|
d=000010 -- ! mem(2): PS
|
1668 |
|
|
wal 177766 -- check CPUERR
|
1669 |
|
|
rm d=000104 -- ! CPUERR: (rsv=1,adderr=1)
|
1670 |
|
|
wm 000000 -- clear CPUERR
|
1671 |
|
|
# mmu back to default setup
|
1672 |
|
|
wal 172302 -- kernel I space DR segment 1 (base 20000)
|
1673 |
|
|
wmi 077406 -- slf=127; ed=0(up); acf=6 (r/w)
|
1674 |
|
|
wal 177572 -- SSR0
|
1675 |
|
|
wmi 000000 -- disable
|
1676 |
|
|
wal 172516 -- SSR3
|
1677 |
|
|
wmi 000000 -- disable
|
1678 |
|
|
#
|
1679 |
|
|
#[[on]]
|
1680 |
|
|
#-----------------------------------------------------------------------------
|
1681 |
|
|
C Setup code 21 [base 4740] (MTPx/MFPx; MMU for user mode with I/D)
|
1682 |
|
|
#
|
1683 |
|
|
#use setting as for test 22
|
1684 |
|
|
wal 177600 -- user I space DR
|
1685 |
|
|
wmi 077406 -- slf=127; ed=0(up); acf=6(w/r)
|
1686 |
|
|
wal 177620 -- user D space DR
|
1687 |
|
|
wmi 077406 -- slf=127; ed=0(up); acf=6(w/r)
|
1688 |
|
|
wal 177640 -- user I space AR
|
1689 |
|
|
wmi 000053 -- 53 -> maps 0 -> 5300
|
1690 |
|
|
wal 177660 -- user D space AR
|
1691 |
|
|
wmi 000055 -- 55 -> maps 0 -> 5500
|
1692 |
|
|
wal 177572 -- SSR0
|
1693 |
|
|
wmi 000001 -- set enable bit
|
1694 |
|
|
wal 172516 -- SSR3
|
1695 |
|
|
wmi 000001 -- enable D space for user mode
|
1696 |
|
|
#
|
1697 |
|
|
wal 004740 -- code (to be single stepped...)
|
1698 |
|
|
bwm 6
|
1699 |
|
|
006610 -- mtpi (r0)
|
1700 |
|
|
106610 -- mtpd (r0)
|
1701 |
|
|
006606 -- mtpi r6
|
1702 |
|
|
006510 -- mfpi (r0)
|
1703 |
|
|
106510 -- mfpd (r0)
|
1704 |
|
|
006506 -- mfpi r6
|
1705 |
|
|
#
|
1706 |
|
|
C Exec code 21 (MTPx/MFPx; MMU for user mode with I/D)
|
1707 |
|
|
#
|
1708 |
|
|
wps 030000 -- psw: cmode=0, pmode=11
|
1709 |
|
|
wal 001372 -- setup kernel stack
|
1710 |
|
|
bwm 3
|
1711 |
|
|
012300 --
|
1712 |
|
|
001230 --
|
1713 |
|
|
000666 --
|
1714 |
|
|
wr0 000002 -- r0=2
|
1715 |
|
|
wsp 001372 -- sp=1372
|
1716 |
|
|
#
|
1717 |
|
|
wpc 004740 -- pc=4740
|
1718 |
|
|
step -- step (mtpi (r0))
|
1719 |
|
|
rpc d=004742 -- ! pc=next
|
1720 |
|
|
rsp d=001374 -- ! sp=1374 (one popped)
|
1721 |
|
|
wal 005302 -- user I base
|
1722 |
|
|
rm d=012300 -- ! mem_ui(2) = 012300
|
1723 |
|
|
#
|
1724 |
|
|
step -- step (mtpd (r0))
|
1725 |
|
|
rpc d=004744 -- ! pc=next
|
1726 |
|
|
rsp d=001376 -- ! sp=1376 (one popped)
|
1727 |
|
|
wal 005502 -- user D base
|
1728 |
|
|
rm d=001230 -- ! mem_ud(2) = 001230
|
1729 |
|
|
#
|
1730 |
|
|
step -- step (mtpi r6)
|
1731 |
|
|
rpc d=004746 -- ! pc=next
|
1732 |
|
|
rsp d=001400 -- ! sp=1400 (one popped)
|
1733 |
|
|
wps 170000 -- psw: cmode=11, pmode=11
|
1734 |
|
|
rsp d=000666 -- ! sp_um=666 [[usp]]
|
1735 |
|
|
wps 030000 -- psw: cmode=0, pmode=11
|
1736 |
|
|
#
|
1737 |
|
|
wal 001374 -- clear stack
|
1738 |
|
|
bwm 3
|
1739 |
|
|
000000 --
|
1740 |
|
|
000000 --
|
1741 |
|
|
000000 --
|
1742 |
|
|
#
|
1743 |
|
|
step -- step (mfpi (r0))
|
1744 |
|
|
rpc d=004750 -- ! pc=next
|
1745 |
|
|
rsp d=001376 -- ! sp=1376 (one pushed)
|
1746 |
|
|
wal 001376 -- top of stack
|
1747 |
|
|
rm d=012300 -- !
|
1748 |
|
|
#
|
1749 |
|
|
step -- step (mfpd (r0))
|
1750 |
|
|
rpc d=004752 -- ! pc=next
|
1751 |
|
|
rsp d=001374 -- ! sp=1374 (one pushed)
|
1752 |
|
|
wal 001374 -- top of stack
|
1753 |
|
|
rm d=001230 -- !
|
1754 |
|
|
#
|
1755 |
|
|
step -- step (mtpi r6)
|
1756 |
|
|
rpc d=004754 -- ! pc=next
|
1757 |
|
|
rsp d=001372 -- ! sp=1372 (one pushed)
|
1758 |
|
|
wal 001372 -- top of stack
|
1759 |
|
|
rm d=000666 -- !
|
1760 |
|
|
#
|
1761 |
|
|
wal 005302 -- clean tainted memory
|
1762 |
|
|
wm 000000 --
|
1763 |
|
|
wal 005502 --
|
1764 |
|
|
wm 000000 --
|
1765 |
|
|
#
|
1766 |
|
|
wps 000000 -- psw: cmode=pmode=0 (kernel)
|
1767 |
|
|
#-----------------------------------------------------------------------------
|
1768 |
|
|
C Setup code 22 [base 5000, use 50-57] (MMU ; run user mode code with I/D)
|
1769 |
|
|
#
|
1770 |
|
|
wal 177600 -- user I space DR
|
1771 |
|
|
wmi 000002 -- slf=0; ed=0(up); acf=2(read-only)
|
1772 |
|
|
wal 177620 -- user D space DR
|
1773 |
|
|
wmi 000006 -- slf=0; ed=0(up); acf=6(w/r)
|
1774 |
|
|
wal 177640 -- user I space AR
|
1775 |
|
|
wmi 000053 -- 53 -> maps 0 -> 5300
|
1776 |
|
|
wal 177660 -- user D space AR
|
1777 |
|
|
wmi 000055 -- 55 -> maps 0 -> 5500
|
1778 |
|
|
wal 177572 -- SSR0
|
1779 |
|
|
wmi 000001 -- set enable bit
|
1780 |
|
|
wal 172516 -- SSR3
|
1781 |
|
|
wmi 000001 -- enable D space for user mode
|
1782 |
|
|
#
|
1783 |
|
|
wal 005000 -- code (kernel):
|
1784 |
|
|
bwm 5
|
1785 |
|
|
012746 -- mov #144000,-(sp) ;PS for RTI
|
1786 |
|
|
174000 -- cmode=11,pmode=11,rset=1
|
1787 |
|
|
012746 -- mov #0,-(sp) ;PC for RTI
|
1788 |
|
|
000000 --
|
1789 |
|
|
000002 -- rti
|
1790 |
|
|
#-----
|
1791 |
|
|
wal 000034 -- vector: 34 (TRAP)
|
1792 |
|
|
bwm 2
|
1793 |
|
|
005020 -- PC:5020
|
1794 |
|
|
000340 -- PS: pri=7
|
1795 |
|
|
#-----
|
1796 |
|
|
wal 005020 -- code (kernel, trap 34):
|
1797 |
|
|
bwm 4
|
1798 |
|
|
011600 -- mov (sp),r0
|
1799 |
|
|
006560 -- mfpi -2(r0)
|
1800 |
|
|
177776
|
1801 |
|
|
000000 -- halt
|
1802 |
|
|
#-----
|
1803 |
|
|
wal 000250 -- vector: 250 (MMU)
|
1804 |
|
|
bwm 2
|
1805 |
|
|
005040 -- PC:5040
|
1806 |
|
|
000340 -- PS: pri=7
|
1807 |
|
|
#-----
|
1808 |
|
|
wal 005040 -- code (kernel, trap 4):
|
1809 |
|
|
bwm 68
|
1810 |
|
|
005337 -- dec @#5256
|
1811 |
|
|
005256
|
1812 |
|
|
001001 -- bne .+2
|
1813 |
|
|
000000 -- halt
|
1814 |
|
|
013700 -- mov ssr0,r0
|
1815 |
|
|
177572
|
1816 |
|
|
042700 -- bic #177741,r0 ; clear all but id+asn fields
|
1817 |
|
|
177741
|
1818 |
|
|
#5060
|
1819 |
|
|
062700 -- add #177600,r0 ; user DR address base
|
1820 |
|
|
177600
|
1821 |
|
|
# 5 23 062710 0 -- add #400,(r0)
|
1822 |
|
|
# 5 23 000400 0
|
1823 |
|
|
105260 -- incb 1(r0) ; odd address IB access fails !!
|
1824 |
|
|
000001
|
1825 |
|
|
010025 -- mov r0,(r5)+
|
1826 |
|
|
012025 -- mov (r0),(r5)+
|
1827 |
|
|
013700 -- mov ssr1,r0
|
1828 |
|
|
177574
|
1829 |
|
|
#5100
|
1830 |
|
|
010025 -- mov r0,(r5)+
|
1831 |
|
|
012701 -- mov #2,r1
|
1832 |
|
|
000002
|
1833 |
|
|
052737 -- bis #004000,psw
|
1834 |
|
|
004000
|
1835 |
|
|
177776
|
1836 |
|
|
005046 -- clr -(sp)
|
1837 |
|
|
106506 -- mfpd sp
|
1838 |
|
|
#5120
|
1839 |
|
|
010546 -- mov r5,-(sp)
|
1840 |
|
|
010446 -- mov r4,-(sp)
|
1841 |
|
|
010346 -- mov r3,-(sp)
|
1842 |
|
|
010246 -- mov r2,-(sp)
|
1843 |
|
|
010146 -- mov r1,-(sp)
|
1844 |
|
|
010046 -- mov r0,-(sp)
|
1845 |
|
|
042737 -- bic #004000,psw
|
1846 |
|
|
004000
|
1847 |
|
|
#5140
|
1848 |
|
|
177776
|
1849 |
|
|
010002 -- L1: mov r0,r2
|
1850 |
|
|
110003 -- movb r0,r3
|
1851 |
|
|
042702 -- bic #177770,r2 ; mask regnum field
|
1852 |
|
|
177770
|
1853 |
|
|
006302 -- asl r2
|
1854 |
|
|
060602 -- add sp,r2 ; address of reg on stack
|
1855 |
|
|
006203 -- asr r3 ; shift delta field down 3 bit
|
1856 |
|
|
#5160
|
1857 |
|
|
006203 -- asr r3
|
1858 |
|
|
006203 -- asr r3
|
1859 |
|
|
160312 -- sub r3,(r2) ; correct register contents
|
1860 |
|
|
000300 -- swap r0
|
1861 |
|
|
077114 -- sob r1,L1 (.-12)
|
1862 |
|
|
052737 -- bis #004000,psw
|
1863 |
|
|
004000
|
1864 |
|
|
177776
|
1865 |
|
|
#5200
|
1866 |
|
|
012600 -- mov (sp)+,r0
|
1867 |
|
|
012601 -- mov (sp)+,r1
|
1868 |
|
|
012602 -- mov (sp)+,r2
|
1869 |
|
|
012603 -- mov (sp)+,r3
|
1870 |
|
|
012604 -- mov (sp)+,r4
|
1871 |
|
|
012605 -- mov (sp)+,r5
|
1872 |
|
|
106606 -- mtpd sp
|
1873 |
|
|
005726 -- tst (sp)+
|
1874 |
|
|
#5220
|
1875 |
|
|
042737 -- bic #004000,psw
|
1876 |
|
|
004000
|
1877 |
|
|
177776
|
1878 |
|
|
013700 -- mov ssr2,r0
|
1879 |
|
|
177576
|
1880 |
|
|
010025 -- mov r0,(r5)+
|
1881 |
|
|
010016 -- mov r0,(sp)
|
1882 |
|
|
042737 -- bic #160000,ssr0 ; clear abort bits
|
1883 |
|
|
#5240
|
1884 |
|
|
160000
|
1885 |
|
|
177572
|
1886 |
|
|
000002 -- rti
|
1887 |
|
|
000000 -- halt
|
1888 |
|
|
#-----
|
1889 |
|
|
wal 005256 -- data (kernel):
|
1890 |
|
|
wmi 000003 -- stop at 3rd call of MMU handler
|
1891 |
|
|
#-----
|
1892 |
|
|
wal 005300 -- code (user):
|
1893 |
|
|
bwm 8
|
1894 |
|
|
012706 -- mov #100,sp
|
1895 |
|
|
000100
|
1896 |
|
|
005000 -- clr r0
|
1897 |
|
|
012701 -- mov #074,r1
|
1898 |
|
|
000074
|
1899 |
|
|
062021 -- add (r0)+,(r1)+ ; r1 = 74
|
1900 |
|
|
000137 -- jmp @#74
|
1901 |
|
|
000074
|
1902 |
|
|
#
|
1903 |
|
|
wal 005374 -- .=5374
|
1904 |
|
|
bwm 4
|
1905 |
|
|
062021 -- add (r0)+,(r1)+ ; r1 = 76
|
1906 |
|
|
062021 -- add (r0)+,(r1)+ ; r1 = 100
|
1907 |
|
|
#5400
|
1908 |
|
|
062021 -- add (r0)+,(r1)+ ; r1 = 102
|
1909 |
|
|
104417 -- trap 17
|
1910 |
|
|
#
|
1911 |
|
|
wal 005500 -- data (user):
|
1912 |
|
|
bwm 4
|
1913 |
|
|
002001 -- mem_ud(0)=02001
|
1914 |
|
|
002002 -- mem_ud(2)=02002
|
1915 |
|
|
002003 -- mem_ud(4)=02003
|
1916 |
|
|
002004 -- mem_ud(6)=02004
|
1917 |
|
|
wal 005574 -- data (user):
|
1918 |
|
|
bwm 4
|
1919 |
|
|
000300 -- mem_ud(074)=0300
|
1920 |
|
|
000300 -- mem_ud(076)=0300
|
1921 |
|
|
000300 -- mem_ud(100)=0300
|
1922 |
|
|
000300 -- mem_ud(102)=0300
|
1923 |
|
|
#
|
1924 |
|
|
C Exec code 22 (MMU ; run user mode code with I/D)
|
1925 |
|
|
wr5 005260 -- r5=5260
|
1926 |
|
|
wsp 001400 -- sp=1400
|
1927 |
|
|
wpc 005000 -- pc=5000
|
1928 |
|
|
cont -- cont @ 5000
|
1929 |
|
|
wtgo
|
1930 |
|
|
rsp d=001372 -- ! sp
|
1931 |
|
|
rpc d=005030 -- ! pc (halt in TRAP handler)
|
1932 |
|
|
wal 001372 -- check stack (1372)
|
1933 |
|
|
brm 3
|
1934 |
|
|
d=104417 -- ! TRAP instruction
|
1935 |
|
|
d=000104 -- ! PC trap
|
1936 |
|
|
d=174000 -- ! PS trap
|
1937 |
|
|
#
|
1938 |
|
|
wal 005256 --
|
1939 |
|
|
brm 9
|
1940 |
|
|
d=000001 -- ! mem(5256) (mmu 3 - trap count)
|
1941 |
|
|
d=177620 -- ! mem(5260) (1st trap: address fixed DR)
|
1942 |
|
|
d=000406 -- ! mem(5262) (1st trap: new content of DR)
|
1943 |
|
|
d=010420 -- ! mem(5264) (1st trap: ssr1: ra=0,2;rb=1,2)
|
1944 |
|
|
d=000076 -- ! mem(5266) (1st trap: ssr2: pc)
|
1945 |
|
|
d=177600 -- ! mem(5270) (2nd trap: address fixed DR)
|
1946 |
|
|
d=000402 -- ! mem(5272) (2nd trap: new content of DR)
|
1947 |
|
|
d=000000 -- ! mem(5274) (2nd trap: ssr1: none)
|
1948 |
|
|
d=000100 -- ! mem(5276) (2nd trap: ssr2: pc)
|
1949 |
|
|
#
|
1950 |
|
|
wal 005574
|
1951 |
|
|
brm 4
|
1952 |
|
|
d=002301 -- ! mem(5574)=02301 was mem_ud(074)
|
1953 |
|
|
d=002302 -- ! mem(5576)=02302 was mem_ud(076)
|
1954 |
|
|
d=002303 -- ! mem(5600)=02303 was mem_ud(100)
|
1955 |
|
|
d=002304 -- ! mem(5602)=02304 was mem_ud(102)
|
1956 |
|
|
#
|
1957 |
|
|
wal 000034 -- vector: 34 -> trap catcher again
|
1958 |
|
|
bwm 2
|
1959 |
|
|
000036 -- PC:36
|
1960 |
|
|
000000 -- PS:0
|
1961 |
|
|
wal 000250 -- vector: 250 -> trap catcher again
|
1962 |
|
|
bwm 2
|
1963 |
|
|
000252 -- PC:252
|
1964 |
|
|
000000 -- PS:0
|
1965 |
|
|
#
|
1966 |
|
|
wps 000000 -- psw: cmode=pmode=0 (kernel)
|
1967 |
|
|
#-----------------------------------------------------------------------------
|
1968 |
|
|
C Setup code 23 [base 5700; use 57-63] (test cmp and conditional branch)
|
1969 |
|
|
#
|
1970 |
|
|
wal 005700 -- code test 1:
|
1971 |
|
|
bwm 5
|
1972 |
|
|
012012 -- mov (r0)+,(r2) ; load PSW from table
|
1973 |
|
|
004737 -- jsr pc,@#6000
|
1974 |
|
|
006000
|
1975 |
|
|
077104 -- sob r1,-4
|
1976 |
|
|
000000 -- halt
|
1977 |
|
|
#
|
1978 |
|
|
wal 005720 -- code test 2:
|
1979 |
|
|
bwm 6
|
1980 |
|
|
000230 -- spl 0
|
1981 |
|
|
005720 -- tst (r0)+ ; verify tst response
|
1982 |
|
|
004737 -- jsr pc,@#6000
|
1983 |
|
|
006000
|
1984 |
|
|
077104 -- sob r1,-4
|
1985 |
|
|
000000 -- halt
|
1986 |
|
|
#
|
1987 |
|
|
wal 005740 -- code test 3:
|
1988 |
|
|
bwm 6
|
1989 |
|
|
000230 -- spl 0
|
1990 |
|
|
022020 -- cmp (r0+),(r0)+ ; verify cmp response
|
1991 |
|
|
004737 -- jsr pc,@#6000
|
1992 |
|
|
006000
|
1993 |
|
|
077104 -- sob r1,-4
|
1994 |
|
|
000000 -- halt
|
1995 |
|
|
#
|
1996 |
|
|
# test 1 test 2 test 3
|
1997 |
|
|
# - C V Z N < = > < = >
|
1998 |
|
|
# code branch condition mask 1 2 3 4 5 1 2 3 1 2 3 4 5 6 7
|
1999 |
|
|
# BNE if Z = 0 000004 y y y y y y y y y y y y
|
2000 |
|
|
# BEQ if Z = 1 000010 y y y
|
2001 |
|
|
# BGE if (N xor V) = 0 000020 y y y y y y y y y
|
2002 |
|
|
# BLT if (N xor V) = 1 000040 y y y y y y
|
2003 |
|
|
# BGT if (Z or (N xor V)) = 0 000100 y y y y y y
|
2004 |
|
|
# BLE if (Z or (N xor V)) = 1 000200 y y y y y y y y y
|
2005 |
|
|
# BPL if N = 0 000400 y y y y y y y y y y
|
2006 |
|
|
# BMI if N = 1 001000 y y y y y
|
2007 |
|
|
# BHI if (C or Z) = 0 002000 y y y y y y y y
|
2008 |
|
|
# BLOS if (C or Z) = 1 004000 y y y y y y y
|
2009 |
|
|
# BVC if V = 0 010000 y y y y y y y y y y y y
|
2010 |
|
|
# BVS if V = 1 020000 y y y
|
2011 |
|
|
# BCC if C = 0 (aka BHIS) 040000 y y y y y y y y y y y
|
2012 |
|
|
# BCS if C = 1 (aka BLO) 100000 y y y y
|
2013 |
|
|
#
|
2014 |
|
|
wal 006000 -- code check:
|
2015 |
|
|
bwm 63
|
2016 |
|
|
011203 -- mov (r2),r3 ; save PSW
|
2017 |
|
|
012704 -- mov #177774,r4 ; set pattern store
|
2018 |
|
|
177774 --
|
2019 |
|
|
010312 -- mov r3,(r2) ; restore PSW
|
2020 |
|
|
001003 -- bne .+3
|
2021 |
|
|
042704 -- bic #000004,r4
|
2022 |
|
|
000004 --
|
2023 |
|
|
010312 -- mov r3,(r2)
|
2024 |
|
|
#6020
|
2025 |
|
|
001403 -- beq .+3
|
2026 |
|
|
042704 -- bic #000010,r4
|
2027 |
|
|
000010 --
|
2028 |
|
|
010312 -- mov r3,(r2)
|
2029 |
|
|
002003 -- bge .+3
|
2030 |
|
|
042704 -- bic #000020,r4
|
2031 |
|
|
000020 --
|
2032 |
|
|
010312 -- mov r3,(r2)
|
2033 |
|
|
#6040
|
2034 |
|
|
002403 -- blt .+3
|
2035 |
|
|
042704 -- bic #000040,r4
|
2036 |
|
|
000040 --
|
2037 |
|
|
010312 -- mov r3,(r2)
|
2038 |
|
|
003003 -- bgt .+3
|
2039 |
|
|
042704 -- bic #000100,r4
|
2040 |
|
|
000100 --
|
2041 |
|
|
010312 -- mov r3,(r2)
|
2042 |
|
|
#6060
|
2043 |
|
|
003403 -- ble .+3
|
2044 |
|
|
042704 -- bic #000200,r4
|
2045 |
|
|
000200 --
|
2046 |
|
|
010312 -- mov r3,(r2)
|
2047 |
|
|
100003 -- bpl .+3
|
2048 |
|
|
042704 -- bic #000400,r4
|
2049 |
|
|
000400 --
|
2050 |
|
|
010312 -- mov r3,(r2)
|
2051 |
|
|
#6100
|
2052 |
|
|
100403 -- bmi .+3
|
2053 |
|
|
042704 -- bic #001000,r4
|
2054 |
|
|
001000 --
|
2055 |
|
|
010312 -- mov r3,(r2)
|
2056 |
|
|
101003 -- bhi .+3
|
2057 |
|
|
042704 -- bic #002000,r4
|
2058 |
|
|
002000 --
|
2059 |
|
|
010312 -- mov r3,(r2)
|
2060 |
|
|
#6120
|
2061 |
|
|
101403 -- blos .+3
|
2062 |
|
|
042704 -- bic #004000,r4
|
2063 |
|
|
004000 --
|
2064 |
|
|
010312 -- mov r3,(r2)
|
2065 |
|
|
102003 -- bvc .+3
|
2066 |
|
|
042704 -- bic #010000,r4
|
2067 |
|
|
010000 --
|
2068 |
|
|
010312 -- mov r3,(r2)
|
2069 |
|
|
#6140
|
2070 |
|
|
102403 -- bvs .+3
|
2071 |
|
|
042704 -- bic #020000,r4
|
2072 |
|
|
020000 --
|
2073 |
|
|
010312 -- mov r3,(r2)
|
2074 |
|
|
103003 -- bcc .+3
|
2075 |
|
|
042704 -- bic #040000,r4
|
2076 |
|
|
040000 --
|
2077 |
|
|
010312 -- mov r3,(r2)
|
2078 |
|
|
#6160
|
2079 |
|
|
103403 -- bcs .+3
|
2080 |
|
|
042704 -- bic #100000,r4
|
2081 |
|
|
100000 --
|
2082 |
|
|
010312 -- mov r3,(r2)
|
2083 |
|
|
010325 -- mov r3,(r5)+
|
2084 |
|
|
010425 -- mov r4,(r5)+
|
2085 |
|
|
000207 -- rts pc
|
2086 |
|
|
#
|
2087 |
|
|
wal 006200 -- data test 1:
|
2088 |
|
|
bwm 5
|
2089 |
|
|
000000 -- PSW - no cc
|
2090 |
|
|
000001 -- PSW - C=1
|
2091 |
|
|
000002 -- PSW - V=1
|
2092 |
|
|
000004 -- PSW - Z=1
|
2093 |
|
|
000010 -- PSW - N=1
|
2094 |
|
|
#
|
2095 |
|
|
wal 006220 -- data test 2:
|
2096 |
|
|
bwm 3
|
2097 |
|
|
177777 -- tst -1
|
2098 |
|
|
000000 -- tst 0
|
2099 |
|
|
000001 -- tst 1
|
2100 |
|
|
#
|
2101 |
|
|
wal 006230 -- data test 3:
|
2102 |
|
|
bwm 14
|
2103 |
|
|
000001 -- cmp 1,2
|
2104 |
|
|
000002
|
2105 |
|
|
000001 -- cmp 1,1
|
2106 |
|
|
000001
|
2107 |
|
|
#6240
|
2108 |
|
|
000002 -- cmp 2,1
|
2109 |
|
|
000001
|
2110 |
|
|
177777 -- cmp -1,2
|
2111 |
|
|
000002
|
2112 |
|
|
000002 -- cmp 2,-1
|
2113 |
|
|
177777
|
2114 |
|
|
100000 -- cmp 100000,077777
|
2115 |
|
|
077777
|
2116 |
|
|
#6260
|
2117 |
|
|
077777 -- cmp 077777,100000
|
2118 |
|
|
100000
|
2119 |
|
|
#
|
2120 |
|
|
C Exec code 23 (test cmp and conditional branch)
|
2121 |
|
|
C Exec test 23.1 (explict cc setting)
|
2122 |
|
|
#
|
2123 |
|
|
wr0 006200 -- r0=6200 (input data)
|
2124 |
|
|
wr1 000005 -- r1=5
|
2125 |
|
|
wr2 177776 -- r2=177776 (PS address)
|
2126 |
|
|
wr5 006300 -- r5=6300 (output data)
|
2127 |
|
|
wsp 001400 -- sp=1400
|
2128 |
|
|
stapc 005700 -- start @ 5700
|
2129 |
|
|
wtgo
|
2130 |
|
|
rr0 d=006212 -- ! r0
|
2131 |
|
|
rr1 d=000000 -- ! r1
|
2132 |
|
|
rr5 d=006324 -- ! r5
|
2133 |
|
|
rsp d=001400 -- ! sp
|
2134 |
|
|
rpc d=005712 -- ! pc
|
2135 |
|
|
wal 006300 -- use BCC/BCS naming below
|
2136 |
|
|
brm 10
|
2137 |
|
|
d=000000 -- ! mem(6300) 1 PS: none
|
2138 |
|
|
d=052524 -- ! mem(6302) 1 BNE,BGE,BGT,BPL,BHI,BVC,BCC
|
2139 |
|
|
d=000001 -- ! mem(6304) 2 PS: C=1
|
2140 |
|
|
d=114524 -- ! mem(6306) 2 BNE,BGE,BGT,BPL,BLOS,BVC,BCS
|
2141 |
|
|
d=000002 -- ! mem(6310) 3 PS: V=1
|
2142 |
|
|
d=062644 -- ! mem(6312) 3 BNE,BLT,BLE,BPL,BHI,BVS,BCC
|
2143 |
|
|
d=000004 -- ! mem(6314) 4 PS: Z=1
|
2144 |
|
|
d=054630 -- ! mem(6316) 4 BEQ,BGE,BLE,BPL,BLOS,BVC,BCC
|
2145 |
|
|
d=000010 -- ! mem(6320) 5 PS: N=1
|
2146 |
|
|
d=053244 -- ! mem(6322) 5 BNE,BLT,BLE,BMI,BHI,BVC,BCC
|
2147 |
|
|
#
|
2148 |
|
|
C Exec test 23.2 (tst testing)
|
2149 |
|
|
#
|
2150 |
|
|
wr0 006220 -- r0=6220 (input data)
|
2151 |
|
|
wr1 000003 -- r1=3
|
2152 |
|
|
wr2 177776 -- r2=177776 (PS address)
|
2153 |
|
|
wr5 006330 -- sp=6330 (output data)
|
2154 |
|
|
wsp 001400 -- sp=1400
|
2155 |
|
|
stapc 005720 -- start @ 5720
|
2156 |
|
|
wtgo
|
2157 |
|
|
rr0 d=006226 -- ! r0
|
2158 |
|
|
rr1 d=000000 -- ! r1
|
2159 |
|
|
rr5 d=006344 -- ! r5
|
2160 |
|
|
rsp d=001400 -- ! sp
|
2161 |
|
|
rpc d=005734 -- ! pc
|
2162 |
|
|
wal 006330 -- use BHIS(BCC)/BLO(BLO) naming below
|
2163 |
|
|
brm 6
|
2164 |
|
|
d=000010 -- ! mem(6330) 1 PS: tst -1: N=1
|
2165 |
|
|
d=053244 -- ! mem(6332) 1 BNE,BLT,BLE,BMI,BHI,BVC,BHIS
|
2166 |
|
|
d=000004 -- ! mem(6334) 2 PS: tst 0: Z=1
|
2167 |
|
|
d=054630 -- ! mem(6336) 2 BEQ,BGE,BLE,BPL,BLOS,BVC,BHIS
|
2168 |
|
|
d=000000 -- ! mem(6340) 3 PS: tst 1: all 0
|
2169 |
|
|
d=052524 -- ! mem(6342) 3 BNE,BGE,BGT,BPL,BHI,BVC,BHIS
|
2170 |
|
|
#
|
2171 |
|
|
C Exec test 23.3 (cmp testing)
|
2172 |
|
|
#
|
2173 |
|
|
wr0 006230 -- r0=6230 (input data)
|
2174 |
|
|
wr1 000007 -- r1=7
|
2175 |
|
|
wr2 177776 -- r2=177776 (PS address)
|
2176 |
|
|
wr5 006344 -- sp=6344 (output data)
|
2177 |
|
|
wsp 001400 -- sp=1400
|
2178 |
|
|
stapc 005740 -- start @ 5740
|
2179 |
|
|
wtgo
|
2180 |
|
|
rr0 d=006264 -- ! r0
|
2181 |
|
|
rr1 d=000000 -- ! r1
|
2182 |
|
|
rr5 d=006400 -- ! r5
|
2183 |
|
|
rsp d=001400 -- ! sp
|
2184 |
|
|
rpc d=005754 -- ! pc
|
2185 |
|
|
wal 006344 -- cmp= S-D !
|
2186 |
|
|
brm 14
|
2187 |
|
|
d=000011 -- ! mem(6344) 1 PS: cmp 1,2: N=1,C=1 ok
|
2188 |
|
|
d=115244 -- ! mem(6346) 1 BNE,BLT,BLE,BMI,BLOS,BVC,BLO
|
2189 |
|
|
d=000004 -- ! mem(6350) 2 PS: cmp 1,1: Z=1 ok
|
2190 |
|
|
d=054630 -- ! mem(6352) 2 BEQ,BGE,BLE,BPL,BLOS,BVC,BHIS
|
2191 |
|
|
d=000000 -- ! mem(6354) 3 PS: cmp 2,1: none ok
|
2192 |
|
|
d=052524 -- ! mem(6356) 3 BNE,BGE,BGT,BPL,BHI,BVC,BHIS
|
2193 |
|
|
d=000010 -- ! mem(6360) 4 PS: cmp -1,2: N=1
|
2194 |
|
|
d=053244 -- ! mem(6362) 4 BNE,BLT,BLE,BMI,BHI,BVC,BHIS ok
|
2195 |
|
|
d=000001 -- ! mem(6364) 5 PS: cmp 2,-1: C=1
|
2196 |
|
|
d=114524 -- ! mem(6366) 5 BNE,BGE,BGT,BPL,BLOS,BVC,BLO ok
|
2197 |
|
|
d=000002 -- ! mem(6370) 6 PS: cmp 10..,07..: V=1
|
2198 |
|
|
d=062644 -- ! mem(6372) 6 BNE,BLT,BLE,BPL,BHI,BVS,BHIS ok
|
2199 |
|
|
d=000013 -- ! mem(6374) 7 PS: cmp 07..,10..: N=1,V=1,C=1
|
2200 |
|
|
d=125124 -- ! mem(6376) 7 BNE,BGE,BGT,BMI,BLOS,BVS,BLO ok
|
2201 |
|
|
#
|
2202 |
|
|
#-----------------------------------------------------------------------------
|
2203 |
|
|
C Setup code 24 [base 6400] (test MARK instruction)
|
2204 |
|
|
#
|
2205 |
|
|
wal 006400 -- code (main):
|
2206 |
|
|
bwm 13
|
2207 |
|
|
010546 -- mov r5,-(sp) ; push old r5 on stack
|
2208 |
|
|
012746 -- mov #101,-(sp) ; push 1st parameter
|
2209 |
|
|
000101
|
2210 |
|
|
012746 -- mov #102,-(sp) ; push 2nd parameter
|
2211 |
|
|
000102
|
2212 |
|
|
012746 -- mov #103,-(sp) ; push 3rd parameter
|
2213 |
|
|
000103
|
2214 |
|
|
012746 -- mov #mark3,-(sp) ; push MARK 3
|
2215 |
|
|
#6420
|
2216 |
|
|
006403
|
2217 |
|
|
010605 -- mov sp,r5 ; address of MARK N
|
2218 |
|
|
004737 -- jsr pc,@#6440 ; call procedure
|
2219 |
|
|
006440
|
2220 |
|
|
000000 -- halt
|
2221 |
|
|
#
|
2222 |
|
|
# stack of procedure when called:
|
2223 |
|
|
# addr content
|
2224 |
|
|
# 576 12(sp) 10(r5) old r5
|
2225 |
|
|
# 574 10(sp) 6(r5) param1
|
2226 |
|
|
# 572 6(sp) 4(r5) param2
|
2227 |
|
|
# 570 4(sp) 2(r5) param3
|
2228 |
|
|
# 566 2(sp) (r5) mark 3
|
2229 |
|
|
# 564 (sp) return pc
|
2230 |
|
|
#
|
2231 |
|
|
wal 006440 -- code (procedure):
|
2232 |
|
|
bwm 7
|
2233 |
|
|
016520 -- mov 6(r5),(r0)+ ; get 1st param
|
2234 |
|
|
000006
|
2235 |
|
|
016520 -- mov 4(r5),(r0)+ ; get 2nd param
|
2236 |
|
|
000004
|
2237 |
|
|
016520 -- mov 2(r5),(r0)+ ; get 3rd param
|
2238 |
|
|
000002
|
2239 |
|
|
000205 -- rts r5
|
2240 |
|
|
#
|
2241 |
|
|
C Exec code 24 (test MARK instruction)
|
2242 |
|
|
#
|
2243 |
|
|
wr0 006470 -- r0=6470
|
2244 |
|
|
wr5 123456 -- r5=123456
|
2245 |
|
|
wsp 001400 -- sp=1400
|
2246 |
|
|
stapc 006400 -- start @ 6400
|
2247 |
|
|
wtgo
|
2248 |
|
|
rr0 d=006476 -- ! r0=6476 (3 words written)
|
2249 |
|
|
rr5 d=123456 -- ! r5 (restored)
|
2250 |
|
|
rsp d=001400 -- ! sp
|
2251 |
|
|
rpc d=006432 -- ! pc
|
2252 |
|
|
wal 001364 -- check stack
|
2253 |
|
|
brm 6
|
2254 |
|
|
d=006430 -- ! mem(1364)
|
2255 |
|
|
d=006403 -- ! mem(1366)
|
2256 |
|
|
d=000103 -- ! mem(1370)
|
2257 |
|
|
d=000102 -- ! mem(1372)
|
2258 |
|
|
d=000101 -- ! mem(1374)
|
2259 |
|
|
d=123456 -- ! mem(1376)
|
2260 |
|
|
wal 006470 -- check stored values
|
2261 |
|
|
brm 3
|
2262 |
|
|
d=000101 -- ! mem(6470) (1st param)
|
2263 |
|
|
d=000102 -- ! mem(6472) (2nd param)
|
2264 |
|
|
d=000103 -- ! mem(6474) (3rd param)
|
2265 |
|
|
#
|
2266 |
|
|
# probably first and last time MARK is used. It's a bastard anyway.
|
2267 |
|
|
#
|
2268 |
|
|
#-----------------------------------------------------------------------------
|
2269 |
|
|
C Setup code 25 [base 6500; use 65-66] (basic byte instruction and cc test)
|
2270 |
|
|
#
|
2271 |
|
|
wal 006500 -- code:
|
2272 |
|
|
bwm 22
|
2273 |
|
|
110124 -- movb r1,(r4)+ (#123, #333)
|
2274 |
|
|
120124 -- cmpb r1,(r4)+ (#123, #333)
|
2275 |
|
|
120224 -- cmpb r2,(r4)+ (#321, #111)
|
2276 |
|
|
120124 -- cmpb r1,(r4)+ (#123, #123)
|
2277 |
|
|
105024 -- clrb (r4)+ (#333)
|
2278 |
|
|
130124 -- bitb r1,(r4)+ (#123, #11)
|
2279 |
|
|
130124 -- bitb r1,(r4)+ (#123, #44)
|
2280 |
|
|
140124 -- bicb r1,(r4)+ (#123, #333)
|
2281 |
|
|
#6520
|
2282 |
|
|
150124 -- bisb r1,(r4)+ (#123, #111)
|
2283 |
|
|
105124 -- comb (r4)+ (#321)
|
2284 |
|
|
105224 -- incb (r4)+ (#321)
|
2285 |
|
|
105324 -- decb (r4)+ (#321)
|
2286 |
|
|
105424 -- negb (r4)+ (#321)
|
2287 |
|
|
105724 -- tstb (r4)+ (#321)
|
2288 |
|
|
106024 -- rorb (r4)+ (#201) Cin=0; Cout=1
|
2289 |
|
|
106024 -- rorb (r4)+ (#021) Cin=1; Cout=1
|
2290 |
|
|
#6540
|
2291 |
|
|
106124 -- rolb (r4)+ (#210) Cin=1; Cout=1
|
2292 |
|
|
106224 -- asrb (r4)+ (#020)
|
2293 |
|
|
106224 -- asrb (r4)+ (#220)
|
2294 |
|
|
106324 -- aslb (r4)+ (#020)
|
2295 |
|
|
106324 -- aslb (r4)+ (#220)
|
2296 |
|
|
000000 -- halt
|
2297 |
|
|
#
|
2298 |
|
|
wal 000014 -- vector: 14
|
2299 |
|
|
bwm 2
|
2300 |
|
|
006560 -- PC:6560
|
2301 |
|
|
000000 -- PS:0
|
2302 |
|
|
#
|
2303 |
|
|
wal 006560 -- code: (trap 14):
|
2304 |
|
|
bwm 3
|
2305 |
|
|
016625 -- mov 2(sp),(r5)+
|
2306 |
|
|
000002
|
2307 |
|
|
000006 -- rtt
|
2308 |
|
|
#
|
2309 |
|
|
wal 006600 -- data 1:
|
2310 |
|
|
bwm 11
|
2311 |
|
|
155733 -- (#333,#333)
|
2312 |
|
|
051511 -- (#123,#111)
|
2313 |
|
|
044333 -- (#11 ,#333)
|
2314 |
|
|
155444 -- (#333,#44)
|
2315 |
|
|
150511 -- (#321,#111)
|
2316 |
|
|
150721 -- (#321,#321)
|
2317 |
|
|
150721 -- (#321,#321)
|
2318 |
|
|
010601 -- (#021,#201)
|
2319 |
|
|
#6620
|
2320 |
|
|
010210 -- (#020,#210)
|
2321 |
|
|
010220 -- (#020,#220)
|
2322 |
|
|
000220 -- (....,#220)
|
2323 |
|
|
#
|
2324 |
|
|
C Exec code 25 (basic byte instruction and cc test)
|
2325 |
|
|
#
|
2326 |
|
|
wr1 000123 -- r1=123
|
2327 |
|
|
wr2 000321 -- r2=321
|
2328 |
|
|
wr4 006600 -- r4=6600
|
2329 |
|
|
wr5 006626 -- r5=6626
|
2330 |
|
|
wsp 001374 -- sp=1374
|
2331 |
|
|
wal 001374 -- setup stack with rtt return frame setting T flag
|
2332 |
|
|
bwm 2
|
2333 |
|
|
006500 -- start address (code 25 @ 6500)
|
2334 |
|
|
000020 -- set T flag in PSW
|
2335 |
|
|
stapc 006564 -- start @ 6564 -> rtt -> 6500 from stack
|
2336 |
|
|
wtgo
|
2337 |
|
|
rr1 d=000123 -- ! r1=123
|
2338 |
|
|
rr2 d=000321 -- ! r2=321
|
2339 |
|
|
rr4 d=006625 -- ! r4=6625
|
2340 |
|
|
rr5 d=006700 -- ! r5=6700
|
2341 |
|
|
rsp d=001400 -- ! sp=1400
|
2342 |
|
|
rpc d=006554 -- ! pc=6554
|
2343 |
|
|
wal 006600
|
2344 |
|
|
brm 11
|
2345 |
|
|
d=155523 -- ! mem(6600)=123; movb r1,(r4)+ (#123, #333)
|
2346 |
|
|
# ! mem(6601)=333; cmpb r1,(r4)+ (#123, #333)
|
2347 |
|
|
d=051511 -- ! mem(6602)=111; cmpb r1,(r4)+ (#321, #111)
|
2348 |
|
|
# ! mem(6603)=123; cmpb r1,(r4)+ (#123, #123)
|
2349 |
|
|
d=044000 -- ! mem(6604)=000; clrb (r4)+ (#333)
|
2350 |
|
|
# ! mem(6605)=011; bitb r1,(r4)+ (#123, #11)
|
2351 |
|
|
d=104044 -- ! mem(6606)=044; bitb r1,(r4)+ (#123, #44)
|
2352 |
|
|
# ! mem(6607)=210; bicb r1,(r4)+ (#123, #333)
|
2353 |
|
|
d=027133 -- ! mem(6610)=133; bisb r1,(r4)+ (#123, #111)
|
2354 |
|
|
# ! mem(6611)=056; comb (r4)+ (#321)
|
2355 |
|
|
d=150322 -- ! mem(6612)=322; incb (r4)+ (#321)
|
2356 |
|
|
# ! mem(6613)=320; decb (r4)+ (#321)
|
2357 |
|
|
d=150457 -- ! mem(6614)=057; negb (r4)+ (#321)
|
2358 |
|
|
# ! mem(6615)=321; tstb (r4)+ (#321)
|
2359 |
|
|
d=104100 -- ! mem(6616)=100; rorb (r4)+ (#201) Cout=1
|
2360 |
|
|
# ! mem(6617)=210; rorb (r4)+ (#021) Cout=1
|
2361 |
|
|
d=004021 -- ! mem(6620)=021; rolb (r4)+ (#210) Cout=1
|
2362 |
|
|
# ! mem(6621)=010; asrb (r4)+ (#020)
|
2363 |
|
|
d=020310 -- ! mem(6622)=310; asrb (r4)+ (#220)
|
2364 |
|
|
# ! mem(6623)=040; aslb (r4)+ (#020)
|
2365 |
|
|
d=000040 -- ! mem(6624)=040; aslb (r4)+ (#220)
|
2366 |
|
|
#
|
2367 |
|
|
wal 006626 -- NZVC
|
2368 |
|
|
brm 21
|
2369 |
|
|
d=000020 -- ! mem(6626)=0000; movb r1,(r4)+ (#123, #333)
|
2370 |
|
|
d=000021 -- ! mem(6630)=000C; cmpb r1,(r4)+ (#123, #333)
|
2371 |
|
|
d=000030 -- ! mem(6632)=N000; cmpb r1,(r4)+ (#321, #111)
|
2372 |
|
|
d=000024 -- ! mem(6634)=0Z00; cmpb r1,(r4)+ (#123, #123)
|
2373 |
|
|
d=000024 -- ! mem(6636)=0Z00; clrb (r4)+ (#333)
|
2374 |
|
|
d=000020 -- ! mem(6640)=0000; bitb r1,(r4)+ (#123, #11)
|
2375 |
|
|
d=000024 -- ! mem(6642)=0Z00; bitb r1,(r4)+ (#123, #44)
|
2376 |
|
|
d=000030 -- ! mem(6644)=N000; bicb r1,(r4)+ (#123, #333)
|
2377 |
|
|
d=000020 -- ! mem(6646)=0000; bisb r1,(r4)+ (#123, #111)
|
2378 |
|
|
d=000021 -- ! mem(6650)=000C; comb (r4)+ (#321)
|
2379 |
|
|
d=000031 -- ! mem(6652)=N00C; incb (r4)+ (#321) keep C!
|
2380 |
|
|
d=000031 -- ! mem(6654)=N00C; decb (r4)+ (#321) keep C!
|
2381 |
|
|
d=000021 -- ! mem(6656)=000C; negb (r4)+ (#321)
|
2382 |
|
|
d=000030 -- ! mem(6660)=N000; tstb (r4)+ (#321)
|
2383 |
|
|
d=000023 -- ! mem(6662)=00VC; rorb (r4)+ (#201)
|
2384 |
|
|
d=000031 -- ! mem(6664)=N00C; rorb (r4)+ (#021)
|
2385 |
|
|
d=000023 -- ! mem(6666)=00VC; rolb (r4)+ (#210)
|
2386 |
|
|
d=000020 -- ! mem(6670)=0000; asrb (r4)+ (#020)
|
2387 |
|
|
d=000032 -- ! mem(6672)=N0V0; asrb (r4)+ (#220)
|
2388 |
|
|
d=000020 -- ! mem(6674)=0000; aslb (r4)+ (#020)
|
2389 |
|
|
d=000023 -- ! mem(6676)=00VC; aslb (r4)+ (#220)
|
2390 |
|
|
#
|
2391 |
|
|
rst -- console reset (to clear T flag)
|
2392 |
|
|
wal 000014 -- vector: 14 -> trap catcher again
|
2393 |
|
|
bwm 2
|
2394 |
|
|
000016 -- PC:16
|
2395 |
|
|
000000 -- PS:0
|
2396 |
|
|
#-----------------------------------------------------------------------------
|
2397 |
|
|
C Setup code 26 [base 6700; use 67-70] (address modes torture tests)
|
2398 |
|
|
#
|
2399 |
|
|
wal 006700 -- code test 1:
|
2400 |
|
|
bwm 5
|
2401 |
|
|
012020 -- mov (r0)+,(r0)+
|
2402 |
|
|
062020 -- add (r0)+,(r0)+
|
2403 |
|
|
014141 -- mov -(r1),-(r1)
|
2404 |
|
|
064141 -- add -(r1),-(r1)
|
2405 |
|
|
#6710
|
2406 |
|
|
000000 -- halt
|
2407 |
|
|
#-----
|
2408 |
|
|
wal 006720 -- code test 2:
|
2409 |
|
|
bwm 8
|
2410 |
|
|
016767 -- mov a(pc),b(pc)
|
2411 |
|
|
000014 -- here pc=6724, target@6740 --> index=14
|
2412 |
|
|
000014 -- here pc=6726, target@6742 --> index=14
|
2413 |
|
|
066767 -- add c(pc),d(pc)
|
2414 |
|
|
#6730
|
2415 |
|
|
000012 -- here pc=6732, target@6744 --> index=12
|
2416 |
|
|
000012 -- here pc=6734, target@6746 --> index=12
|
2417 |
|
|
000000 -- halt
|
2418 |
|
|
000000 -- halt
|
2419 |
|
|
#
|
2420 |
|
|
wal 006740 -- data (pc relative) for test 2:
|
2421 |
|
|
bwm 4
|
2422 |
|
|
006740 -- target for mov a(pc)
|
2423 |
|
|
006742 -- target for ,b(pc)
|
2424 |
|
|
000011 -- target for add c(pc)
|
2425 |
|
|
006746 -- target for ,d(pc)
|
2426 |
|
|
#-----
|
2427 |
|
|
wal 006750 -- code test 3:
|
2428 |
|
|
bwm 12
|
2429 |
|
|
012727 -- mov #1,#0
|
2430 |
|
|
000001
|
2431 |
|
|
000000
|
2432 |
|
|
062727 -- add #1,#2
|
2433 |
|
|
#6760
|
2434 |
|
|
000001
|
2435 |
|
|
000002
|
2436 |
|
|
016767 -- mov -14(pc),2(pc)
|
2437 |
|
|
177764 -- pc here: 6770: read dst of mov #1,#0 (@6754)
|
2438 |
|
|
000002 -- pc here: 6772: write src of add #0,r0 (@6774)
|
2439 |
|
|
062700 -- add #0,r0
|
2440 |
|
|
000000
|
2441 |
|
|
000000 -- halt
|
2442 |
|
|
#-----
|
2443 |
|
|
wal 007000 -- code test 4:
|
2444 |
|
|
bwm 8
|
2445 |
|
|
005200 -- inc r0
|
2446 |
|
|
010001 -- mov r0,r1
|
2447 |
|
|
010702 -- mov pc,r2
|
2448 |
|
|
005007 -- clr pc
|
2449 |
|
|
000000 -- halt
|
2450 |
|
|
000000 -- halt
|
2451 |
|
|
005203 -- L1: inc r3
|
2452 |
|
|
000000 -- halt
|
2453 |
|
|
#-----
|
2454 |
|
|
wal 000000 -- code test 4 (handler at address=0):
|
2455 |
|
|
bwm 2
|
2456 |
|
|
000137 -- jmp @#L1
|
2457 |
|
|
007014
|
2458 |
|
|
#-----
|
2459 |
|
|
wal 007020 -- code test 5:
|
2460 |
|
|
bwm 11
|
2461 |
|
|
012707 -- mov #L2,pc
|
2462 |
|
|
007032
|
2463 |
|
|
000000 -- halt
|
2464 |
|
|
000000 -- halt
|
2465 |
|
|
000000 -- halt
|
2466 |
|
|
062707 -- L2: add #2,pc
|
2467 |
|
|
000002
|
2468 |
|
|
005201 -- inc r1
|
2469 |
|
|
#7040
|
2470 |
|
|
005201 -- inc r1
|
2471 |
|
|
005201 -- inc r1
|
2472 |
|
|
000000 -- halt
|
2473 |
|
|
#-----
|
2474 |
|
|
wal 007060 -- data for test 1 (r0)+ part:
|
2475 |
|
|
bwm 4
|
2476 |
|
|
000111
|
2477 |
|
|
000222
|
2478 |
|
|
000333
|
2479 |
|
|
000444
|
2480 |
|
|
wal 007070 -- data for test 1 -(r1) part:
|
2481 |
|
|
bwm 4
|
2482 |
|
|
000111
|
2483 |
|
|
000222
|
2484 |
|
|
000333
|
2485 |
|
|
000444
|
2486 |
|
|
C Exec code 26 (address modes torture tests)
|
2487 |
|
|
C Exec test 26.1 (test src-dst update hazards with (r0)+,(r0)+ ect):
|
2488 |
|
|
#
|
2489 |
|
|
wr0 007060 -- r0=7060 (input data for (r0)+...)
|
2490 |
|
|
wr1 007100 -- r1=7100 (input data for -(r1)...)
|
2491 |
|
|
wsp 001400 -- sp=1400
|
2492 |
|
|
stapc 006700 -- start @ 6700
|
2493 |
|
|
wtgo
|
2494 |
|
|
rr0 d=007070 -- ! r0
|
2495 |
|
|
rr1 d=007070 -- ! r1
|
2496 |
|
|
rpc d=006712 -- ! pc
|
2497 |
|
|
wal 007060 --
|
2498 |
|
|
brm 4
|
2499 |
|
|
d=000111 -- ! mem(7060)
|
2500 |
|
|
d=000111 -- ! mem(7062)
|
2501 |
|
|
d=000333 -- ! mem(7064)
|
2502 |
|
|
d=000777 -- ! mem(7066)
|
2503 |
|
|
wal 007070 --
|
2504 |
|
|
brm 4
|
2505 |
|
|
d=000333 -- ! mem(7070)
|
2506 |
|
|
d=000222 -- ! mem(7072)
|
2507 |
|
|
d=000444 -- ! mem(7074)
|
2508 |
|
|
d=000444 -- ! mem(7076)
|
2509 |
|
|
C Exec test 26.2 (test indexed mode with pc (mode 67)):
|
2510 |
|
|
#
|
2511 |
|
|
wsp 001400 -- sp=1400
|
2512 |
|
|
stapc 006720 -- start @ 6720
|
2513 |
|
|
wtgo
|
2514 |
|
|
rpc d=006736 -- ! pc
|
2515 |
|
|
wal 006740 --
|
2516 |
|
|
brm 4
|
2517 |
|
|
d=006740 -- ! mem(6740)
|
2518 |
|
|
d=006740 -- ! mem(6742)
|
2519 |
|
|
d=000011 -- ! mem(6744)
|
2520 |
|
|
d=006757 -- ! mem(6746)
|
2521 |
|
|
C Exec test 26.3 (test (pc)+ as dst):
|
2522 |
|
|
#
|
2523 |
|
|
wr0 000111 -- r0=0111
|
2524 |
|
|
wsp 001400 -- sp=1400
|
2525 |
|
|
stapc 006750 -- start @ 6750
|
2526 |
|
|
wtgo
|
2527 |
|
|
rr0 d=000112 -- ! r0
|
2528 |
|
|
rpc d=007000 -- ! pc
|
2529 |
|
|
wal 006752 --
|
2530 |
|
|
brm 2
|
2531 |
|
|
d=000001 -- ! mem(6752) src mov #1,#0
|
2532 |
|
|
d=000001 -- ! mem(6754) dst mov #1,#0
|
2533 |
|
|
wal 006760 --
|
2534 |
|
|
brm 2
|
2535 |
|
|
d=000001 -- ! mem(6760) src add #1,#2
|
2536 |
|
|
d=000003 -- ! mem(6762) dst add #1,#2
|
2537 |
|
|
wal 006774 -- !
|
2538 |
|
|
rmi d=000001 -- ! mem(6774) dst mov -12(pc),2(pc)
|
2539 |
|
|
C Exec test 26.4 (test pc as dst in clr):
|
2540 |
|
|
#
|
2541 |
|
|
wr0 000100 -- r0=0100
|
2542 |
|
|
wr1 000110 -- r1=0110
|
2543 |
|
|
wr2 000120 -- r2=0120
|
2544 |
|
|
wr3 000130 -- r3=0130
|
2545 |
|
|
wsp 001400 -- sp=1400
|
2546 |
|
|
stapc 007000 -- start @ 7000
|
2547 |
|
|
wtgo
|
2548 |
|
|
rr0 d=000101 -- ! r0
|
2549 |
|
|
rr1 d=000101 -- ! r1
|
2550 |
|
|
rr2 d=007006 -- ! r2 (pc after mov pc,r2)
|
2551 |
|
|
rr3 d=000131 -- ! r3
|
2552 |
|
|
rpc d=007020 -- ! pc
|
2553 |
|
|
# cleanup 'vector 0':
|
2554 |
|
|
wal 000000
|
2555 |
|
|
bwm 2
|
2556 |
|
|
000000
|
2557 |
|
|
000000
|
2558 |
|
|
C Exec test 26.5 (test pc as dst in mov and add):
|
2559 |
|
|
#
|
2560 |
|
|
wr1 000000 -- r1=0
|
2561 |
|
|
wsp 001400 -- sp=1400
|
2562 |
|
|
stapc 007020 -- start @ 7020
|
2563 |
|
|
wtgo
|
2564 |
|
|
rr1 d=000002 -- ! r1
|
2565 |
|
|
rpc d=007046 -- ! pc
|
2566 |
|
|
#-----------------------------------------------------------------------------
|
2567 |
|
|
C Setup code 27 [base 7100; use 71-101] (test ASH/ASHC instruction)
|
2568 |
|
|
#
|
2569 |
|
|
wal 007100 -- code test 1 (ash)
|
2570 |
|
|
bwm 7
|
2571 |
|
|
000230 -- spl 0
|
2572 |
|
|
012004 -- L1: mov (r0)+,r4 -- load low
|
2573 |
|
|
072420 -- ash (r0)+,r4 -- shift
|
2574 |
|
|
011321 -- mov (r3),(r1)+ -- store psw
|
2575 |
|
|
010421 -- mov r4,(r1)+ -- store low
|
2576 |
|
|
077205 -- sob r2,L1 (.-5)
|
2577 |
|
|
000000 -- halt
|
2578 |
|
|
#-----
|
2579 |
|
|
wal 007120 -- code test 2 (ashc even)
|
2580 |
|
|
bwm 9
|
2581 |
|
|
000230 -- spl 0
|
2582 |
|
|
012004 -- L1: mov (r0)+,r4 -- load high
|
2583 |
|
|
012005 -- mov (r0)+,r5 -- load low
|
2584 |
|
|
073420 -- ashc (r0)+,r4 -- shift
|
2585 |
|
|
011321 -- mov (r3),(r1)+ -- store psw
|
2586 |
|
|
010421 -- mov r4,(r1)+ -- store high
|
2587 |
|
|
010521 -- mov r5,(r1)+ -- store low
|
2588 |
|
|
077207 -- sob r2,L1 (.-7)
|
2589 |
|
|
#7140
|
2590 |
|
|
000000 -- halt
|
2591 |
|
|
#-----
|
2592 |
|
|
wal 007150 -- code test 3 (ashc odd)
|
2593 |
|
|
bwm 7
|
2594 |
|
|
000230 -- spl 0
|
2595 |
|
|
012005 -- L1: mov (r0)+,r5 -- load low
|
2596 |
|
|
073520 -- ashc (r0)+,r5 -- shift
|
2597 |
|
|
011321 -- mov (r3),(r1)+ -- store psw
|
2598 |
|
|
#7160
|
2599 |
|
|
010521 -- mov r5,(r1)+ -- store low
|
2600 |
|
|
077205 -- sob r2,L1 (.-5)
|
2601 |
|
|
000000 -- halt
|
2602 |
|
|
#-----
|
2603 |
|
|
wal 007200 -- data 1:
|
2604 |
|
|
bwm 24
|
2605 |
|
|
000200 -- (000200, +1)
|
2606 |
|
|
000001 --
|
2607 |
|
|
000200 -- (000200, -1)
|
2608 |
|
|
177777 --
|
2609 |
|
|
000200 -- (000200, +7)
|
2610 |
|
|
000007 --
|
2611 |
|
|
000200 -- (000200, +8)
|
2612 |
|
|
000010 --
|
2613 |
|
|
#7220
|
2614 |
|
|
000200 -- (000200, +9)
|
2615 |
|
|
000011 --
|
2616 |
|
|
000200 -- (000200, -7)
|
2617 |
|
|
177771 --
|
2618 |
|
|
100000 -- (100000, 0)
|
2619 |
|
|
000000 --
|
2620 |
|
|
000000 -- (000000, 0)
|
2621 |
|
|
000000 --
|
2622 |
|
|
#7240
|
2623 |
|
|
000200 -- (000200, -8)
|
2624 |
|
|
177770 --
|
2625 |
|
|
000200 -- (000200, 0)
|
2626 |
|
|
000000 --
|
2627 |
|
|
100000 -- (100000, -6)
|
2628 |
|
|
177772 --
|
2629 |
|
|
040000 -- (040000, +1)
|
2630 |
|
|
000001 --
|
2631 |
|
|
#-----
|
2632 |
|
|
wal 007300 -- data 2:
|
2633 |
|
|
bwm 30
|
2634 |
|
|
000020 -- (000020,000200, +1)
|
2635 |
|
|
000200 --
|
2636 |
|
|
000001 --
|
2637 |
|
|
000020 -- (000020,000200, -1)
|
2638 |
|
|
000200 --
|
2639 |
|
|
177777 --
|
2640 |
|
|
000020 -- (000020,000200, +7)
|
2641 |
|
|
000200 --
|
2642 |
|
|
#7320
|
2643 |
|
|
000007 --
|
2644 |
|
|
000020 -- (000020,000200, +8)
|
2645 |
|
|
000200 --
|
2646 |
|
|
000010 --
|
2647 |
|
|
000020 -- (000020,000200, +9)
|
2648 |
|
|
000200 --
|
2649 |
|
|
000011 --
|
2650 |
|
|
000000 -- (000000,000200, +23)
|
2651 |
|
|
#7340
|
2652 |
|
|
000200 --
|
2653 |
|
|
000027 --
|
2654 |
|
|
000000 -- (000000,000200, +24)
|
2655 |
|
|
000200 --
|
2656 |
|
|
000030 --
|
2657 |
|
|
000000 -- (000000,000200, +25)
|
2658 |
|
|
000200 --
|
2659 |
|
|
000031 --
|
2660 |
|
|
#7360
|
2661 |
|
|
000020 -- (000020,000200, -5)
|
2662 |
|
|
000200 --
|
2663 |
|
|
177773 --
|
2664 |
|
|
000020 -- (000020,000200, -8)
|
2665 |
|
|
000200 --
|
2666 |
|
|
177770 --
|
2667 |
|
|
#-----
|
2668 |
|
|
wal 007440 -- data 3:
|
2669 |
|
|
bwm 6
|
2670 |
|
|
000200 -- (000200, +1)
|
2671 |
|
|
000001 --
|
2672 |
|
|
000200 -- (000200, -1)
|
2673 |
|
|
177777 --
|
2674 |
|
|
000201 -- (000201, -1)
|
2675 |
|
|
177777 --
|
2676 |
|
|
#
|
2677 |
|
|
C Exec code 27 (test ASH/ASHC instruction)
|
2678 |
|
|
C Exec test 27.1 (test ash)
|
2679 |
|
|
#
|
2680 |
|
|
wr0 007200 -- r0=7200 (input data)
|
2681 |
|
|
wr1 007500 -- r1=7500 (output data)
|
2682 |
|
|
wr2 000014 -- r2=14 (test count)
|
2683 |
|
|
wr3 177776 -- r3=177776 (#PSW)
|
2684 |
|
|
wsp 001400 -- sp=1400
|
2685 |
|
|
stapc 007100 -- start @ 7100
|
2686 |
|
|
wtgo
|
2687 |
|
|
rr0 d=007260 -- ! r0
|
2688 |
|
|
rr1 d=007560 -- ! r1
|
2689 |
|
|
rpc d=007116 -- ! pc
|
2690 |
|
|
wal 007500 --
|
2691 |
|
|
brm 24
|
2692 |
|
|
d=000000 -- ! mem(7500) ash +1, 000200 -> nzvc=0
|
2693 |
|
|
d=000400 -- ! mem(7502)
|
2694 |
|
|
d=000000 -- ! mem(7504) ash -1, 000200 -> nzvc=0
|
2695 |
|
|
d=000100 -- ! mem(7506)
|
2696 |
|
|
d=000000 -- ! mem(7510) ash +7, 000200 -> nzvc=0
|
2697 |
|
|
d=040000 -- ! mem(7512)
|
2698 |
|
|
d=000012 -- ! mem(7514) ash +8, 000200 -> n1,z0,v1,c0
|
2699 |
|
|
d=100000 -- ! mem(7516)
|
2700 |
|
|
d=000007 -- ! mem(7520) ash +9, 000200 -> n0,z1,v1,c1
|
2701 |
|
|
d=000000 -- ! mem(7522)
|
2702 |
|
|
d=000000 -- ! mem(7524) ash -7, 000200 -> nzvc=0
|
2703 |
|
|
d=000001 -- ! mem(7526)
|
2704 |
|
|
d=000010 -- ! mem(7530) ash 0, 100000 -> n1,z0,v0,c0
|
2705 |
|
|
d=100000 -- ! mem(7532)
|
2706 |
|
|
d=000004 -- ! mem(7534) ash 0, 000000 -> n0,z1,v0,c0
|
2707 |
|
|
d=000000 -- ! mem(7536)
|
2708 |
|
|
d=000005 -- ! mem(7540) ash -8, 000200 -> n1,z1,v0,c1
|
2709 |
|
|
d=000000 -- ! mem(7542)
|
2710 |
|
|
d=000000 -- ! mem(7544) ash 0, 000200 -> n0,z0,v0,c0
|
2711 |
|
|
d=000200 -- ! mem(7546)
|
2712 |
|
|
d=000010 -- ! mem(7550) ash -6, 100000 -> n1,z0,v0,c0
|
2713 |
|
|
d=177000 -- ! mem(7552)
|
2714 |
|
|
d=000012 -- ! mem(7554) ash +1, 040000 -> n1,z0,v1,c0
|
2715 |
|
|
d=100000 -- ! mem(7556)
|
2716 |
|
|
#----
|
2717 |
|
|
C Exec test 27.2 (test ashc even)
|
2718 |
|
|
#
|
2719 |
|
|
wr0 007300 -- r0=7300 (input data)
|
2720 |
|
|
wr1 007600 -- r1=7600 (output data)
|
2721 |
|
|
wr2 000012 -- r2=12 (test count)
|
2722 |
|
|
wr3 177776 -- r3=177776 (#PSW)
|
2723 |
|
|
wsp 001400 -- sp=1400
|
2724 |
|
|
stapc 007120 -- start @ 7120
|
2725 |
|
|
wtgo
|
2726 |
|
|
rr0 d=007374 -- ! r0
|
2727 |
|
|
rr1 d=007674 -- ! r1
|
2728 |
|
|
rpc d=007142 -- ! pc
|
2729 |
|
|
wal 007600 --
|
2730 |
|
|
brm 30
|
2731 |
|
|
d=000000 -- ! mem(7600) ashc +1, 000020,000200 -> nzvc=0
|
2732 |
|
|
d=000040 -- ! mem(7602)
|
2733 |
|
|
d=000400 -- ! mem(7604)
|
2734 |
|
|
d=000000 -- ! mem(7606) ashc -1, 000020,000200 -> nzvc=0
|
2735 |
|
|
d=000010 -- ! mem(7610)
|
2736 |
|
|
d=000100 -- ! mem(7612)
|
2737 |
|
|
d=000000 -- ! mem(7614) ashc +7, 000020,000200 -> nzvc=0
|
2738 |
|
|
d=004000 -- ! mem(7616)
|
2739 |
|
|
d=040000 -- ! mem(7620)
|
2740 |
|
|
d=000000 -- ! mem(7622) ashc +8, 000020,000200 -> nzvc=0
|
2741 |
|
|
d=010000 -- ! mem(7624)
|
2742 |
|
|
d=100000 -- ! mem(7626)
|
2743 |
|
|
d=000000 -- ! mem(7630) ashc +9, 000020,000200 -> nzvc=0
|
2744 |
|
|
d=020001 -- ! mem(7632)
|
2745 |
|
|
d=000000 -- ! mem(7634)
|
2746 |
|
|
d=000000 -- ! mem(7636) ashc +23, 000000,000200 -> nzvc=0
|
2747 |
|
|
d=040000 -- ! mem(7640)
|
2748 |
|
|
d=000000 -- ! mem(7642)
|
2749 |
|
|
d=000012 -- ! mem(7644) ashc +24, 000000,000200 -> n1z0v1c0
|
2750 |
|
|
d=100000 -- ! mem(7646)
|
2751 |
|
|
d=000000 -- ! mem(7650)
|
2752 |
|
|
d=000007 -- ! mem(7652) ashc +25, 000000,000200 -> n0z1v1c1
|
2753 |
|
|
d=000000 -- ! mem(7654)
|
2754 |
|
|
d=000000 -- ! mem(7656)
|
2755 |
|
|
d=000000 -- ! mem(7660) ashc -5, 000020,000200 -> nzvc=0
|
2756 |
|
|
d=000000 -- ! mem(7662)
|
2757 |
|
|
d=100004 -- ! mem(7664)
|
2758 |
|
|
d=000001 -- ! mem(7666) ashc -8, 000020,000200 -> n0z0v0c1
|
2759 |
|
|
d=000000 -- ! mem(7670)
|
2760 |
|
|
d=010000 -- ! mem(7672)
|
2761 |
|
|
#----
|
2762 |
|
|
C Exec test 27.3 (test ashc odd)
|
2763 |
|
|
#
|
2764 |
|
|
wr0 007440 -- r0=7440 (input data)
|
2765 |
|
|
wr1 007740 -- r1=7740 (output data)
|
2766 |
|
|
wr2 000003 -- r2=3 (test count)
|
2767 |
|
|
wr3 177776 -- r3=177776 (#PSW)
|
2768 |
|
|
wsp 001400 -- sp=1400
|
2769 |
|
|
stapc 007150 -- start @ 7150
|
2770 |
|
|
wtgo
|
2771 |
|
|
rr0 d=007454 -- ! r0
|
2772 |
|
|
rr1 d=007754 -- ! r1
|
2773 |
|
|
rpc d=007166 -- ! pc
|
2774 |
|
|
wal 007740 --
|
2775 |
|
|
brm 6
|
2776 |
|
|
d=000000 -- ! mem(7740) ashc +1, 000200 -> nzvc=0
|
2777 |
|
|
d=000400 -- ! mem(7742)
|
2778 |
|
|
d=000000 -- ! mem(7744) ashc -1, 000200 -> nzvc=0
|
2779 |
|
|
d=000100 -- ! mem(7746)
|
2780 |
|
|
d=000001 -- ! mem(7750) ashc -1, 000201 -> n0z0v0c1
|
2781 |
|
|
d=100100 -- ! mem(7752)
|
2782 |
|
|
#-----------------------------------------------------------------------------
|
2783 |
|
|
C Setup code 30 [base 10200; use 102-103] (test MUL instruction)
|
2784 |
|
|
#
|
2785 |
|
|
wal 010200 -- code test 1 (mul even)
|
2786 |
|
|
bwm 8
|
2787 |
|
|
000230 -- spl 0
|
2788 |
|
|
012004 -- L1: mov (r0)+,r4 -- load p1
|
2789 |
|
|
070420 -- mul (r0)+,r4 -- mul
|
2790 |
|
|
011321 -- mov (r3),(r1)+ -- store psw
|
2791 |
|
|
010421 -- mov r4,(r1)+ -- store p_high
|
2792 |
|
|
010521 -- mov r5,(r1)+ -- store p_low
|
2793 |
|
|
077206 -- sob r2,L1 (.-6)
|
2794 |
|
|
000000 -- halt
|
2795 |
|
|
#-----
|
2796 |
|
|
wal 010220 -- code test 2 (mul odd)
|
2797 |
|
|
bwm 7
|
2798 |
|
|
000230 -- spl 0
|
2799 |
|
|
012005 -- L1: mov (r0)+,r5 -- load p1
|
2800 |
|
|
070520 -- mul (r0)+,r5 -- mul
|
2801 |
|
|
010521 -- mov r5,(r1)+ -- store p_low
|
2802 |
|
|
060403 -- add r4,r3 -- check r4
|
2803 |
|
|
077205 -- sob r2,L1 (.-5)
|
2804 |
|
|
000000 -- halt
|
2805 |
|
|
#
|
2806 |
|
|
# 31022 074456 * 9562 022532 -> 296632364 010656,040054
|
2807 |
|
|
# 18494 044076 * -24041 121027 -> -444614254 162577,134622
|
2808 |
|
|
# -12549 147373 * 2397 004535 -> -30079953 177065,002057
|
2809 |
|
|
# -20493 127763 * -23858 121316 -> 488921994 016444,055612
|
2810 |
|
|
#
|
2811 |
|
|
# 105 000151 * 198 000306 -> 20790 000000,050466
|
2812 |
|
|
# 233 000351 * -94 177642 -> -21902 177777,125162
|
2813 |
|
|
# 186 000272 * -205 177463 -> -38130 177777,065416
|
2814 |
|
|
#
|
2815 |
|
|
wal 010240 -- data 1:
|
2816 |
|
|
bwm 16
|
2817 |
|
|
074456 --
|
2818 |
|
|
022532 --
|
2819 |
|
|
044076 --
|
2820 |
|
|
121027 --
|
2821 |
|
|
147373 --
|
2822 |
|
|
004535 --
|
2823 |
|
|
127763 --
|
2824 |
|
|
121316 --
|
2825 |
|
|
#10260
|
2826 |
|
|
000151 --
|
2827 |
|
|
000306 --
|
2828 |
|
|
000351 --
|
2829 |
|
|
177642 --
|
2830 |
|
|
000272 --
|
2831 |
|
|
177463 --
|
2832 |
|
|
000000 --
|
2833 |
|
|
000272 --
|
2834 |
|
|
#
|
2835 |
|
|
C Exec code 30 (test MUL instruction)
|
2836 |
|
|
C Exec test 30.1 (test mul even)
|
2837 |
|
|
#
|
2838 |
|
|
wr0 010240 -- r0=10240 (input data)
|
2839 |
|
|
wr1 010300 -- r1=10300 (output data)
|
2840 |
|
|
wr2 000010 -- r2=10 (test count)
|
2841 |
|
|
wr3 177776 -- r3=177776 (#PSW)
|
2842 |
|
|
wsp 001400 -- sp=1400
|
2843 |
|
|
stapc 010200 -- start @ 10200
|
2844 |
|
|
wtgo
|
2845 |
|
|
rr0 d=010300 -- ! r0
|
2846 |
|
|
rr1 d=010360 -- ! r1
|
2847 |
|
|
rpc d=010220 -- ! pc
|
2848 |
|
|
wal 010300 --
|
2849 |
|
|
brm 24
|
2850 |
|
|
d=000001 -- ! mem(10300) mul 074456,022532 -> n0z0v0c1
|
2851 |
|
|
d=010656 -- ! mem(10302)
|
2852 |
|
|
d=040054 -- ! mem(10304)
|
2853 |
|
|
d=000011 -- ! mem(10306) mul 044076,121027 -> n1z0v0c1
|
2854 |
|
|
d=162577 -- ! mem(10310)
|
2855 |
|
|
d=134622 -- ! mem(10312)
|
2856 |
|
|
d=000011 -- ! mem(10314) mul 147373,004535 -> n1z0v0c1
|
2857 |
|
|
d=177065 -- ! mem(10316)
|
2858 |
|
|
d=002057 -- ! mem(10320)
|
2859 |
|
|
d=000001 -- ! mem(10322) mul 127763,121316 -> n0z0v0c1
|
2860 |
|
|
d=016444 -- ! mem(10324)
|
2861 |
|
|
d=055612 -- ! mem(10326)
|
2862 |
|
|
d=000000 -- ! mem(10330) mul 000151,000306 -> n0z0v0c0
|
2863 |
|
|
d=000000 -- ! mem(10332)
|
2864 |
|
|
d=050466 -- ! mem(10334)
|
2865 |
|
|
d=000010 -- ! mem(10336) mul 000351,177642 -> n1z0v0c0
|
2866 |
|
|
d=177777 -- ! mem(10340)
|
2867 |
|
|
d=125162 -- ! mem(10342)
|
2868 |
|
|
d=000011 -- ! mem(10344) mul 000272,177463 -> n1z0v0c1
|
2869 |
|
|
d=177777 -- ! mem(10346)
|
2870 |
|
|
d=065416 -- ! mem(10350)
|
2871 |
|
|
d=000004 -- ! mem(10352) mul 000000,000272 -> n0z1v0c0
|
2872 |
|
|
d=000000 -- ! mem(10354)
|
2873 |
|
|
d=000000 -- ! mem(10356)
|
2874 |
|
|
#----
|
2875 |
|
|
C Exec test 30.2 (test mul odd)
|
2876 |
|
|
#
|
2877 |
|
|
wr0 010240 -- r0=10240 (input data)
|
2878 |
|
|
wr1 010360 -- r1=10300 (output data)
|
2879 |
|
|
wr2 000010 -- r2=10 (test count)
|
2880 |
|
|
wr3 000000 -- r3=0
|
2881 |
|
|
wr4 000000 -- r4=0
|
2882 |
|
|
wsp 001400 -- sp=1400
|
2883 |
|
|
stapc 010220 -- start @ 10220
|
2884 |
|
|
wtgo
|
2885 |
|
|
rr0 d=010300 -- ! r0
|
2886 |
|
|
rr1 d=010400 -- ! r1
|
2887 |
|
|
rr3 d=000000 -- ! r3
|
2888 |
|
|
rpc d=010236 -- ! pc
|
2889 |
|
|
wal 010360 --
|
2890 |
|
|
brm 8
|
2891 |
|
|
d=040054 -- ! mem(10360)
|
2892 |
|
|
d=134622 -- ! mem(10362)
|
2893 |
|
|
d=002057 -- ! mem(10364)
|
2894 |
|
|
d=055612 -- ! mem(10366)
|
2895 |
|
|
d=050466 -- ! mem(10370)
|
2896 |
|
|
d=125162 -- ! mem(10372)
|
2897 |
|
|
d=065416 -- ! mem(10374)
|
2898 |
|
|
d=000000 -- ! mem(10376)
|
2899 |
|
|
#
|
2900 |
|
|
#-----------------------------------------------------------------------------
|
2901 |
|
|
C Setup code 31 [base 10400; use 104-110] (test DIV instruction, also ADC,SXT)
|
2902 |
|
|
# Note: test 2 uses sbc too, but if div/div work correctly we have always
|
2903 |
|
|
# C=0 for sbc, so sbc isn't tested. adc has C=0 or C=1 though.
|
2904 |
|
|
#
|
2905 |
|
|
wal 010400 -- code test 1
|
2906 |
|
|
bwm 8
|
2907 |
|
|
012004 -- L1: mov (r0)+,r4 -- load dd high
|
2908 |
|
|
012005 -- mov (r0)+,r5 -- load dd low
|
2909 |
|
|
071420 -- div (r0)+,r4 -- div
|
2910 |
|
|
011321 -- mov (r3),(r1)+ -- store psw
|
2911 |
|
|
010421 -- mov r4,(r1)+ -- store q
|
2912 |
|
|
010521 -- mov r5,(r1)+ -- store r
|
2913 |
|
|
077207 -- sob r2,L1 (.-7)
|
2914 |
|
|
000000 -- halt
|
2915 |
|
|
#-----
|
2916 |
|
|
wal 010420 -- code test 2
|
2917 |
|
|
bwm 24
|
2918 |
|
|
012146 -- L1: mov (r1)+,-(sp) -- save psw on stack
|
2919 |
|
|
016002 -- mov 4(r0),r2 -- load divisor
|
2920 |
|
|
000004
|
2921 |
|
|
070221 -- mul (r1)+,r2 -- multiply with quotient
|
2922 |
|
|
061103 -- add (r1),r3 -- add reminder
|
2923 |
|
|
005502 -- adc r2
|
2924 |
|
|
005721 -- tst (r1)+
|
2925 |
|
|
006704 -- sxt r4
|
2926 |
|
|
#10440
|
2927 |
|
|
060402 -- add r4,r2
|
2928 |
|
|
166003 -- sub 2(r0),r3 -- subtract divident
|
2929 |
|
|
000002
|
2930 |
|
|
005602 -- sbc r2
|
2931 |
|
|
161002 -- sub (r0),r2
|
2932 |
|
|
001002 -- bne L2 (.+2) -- error if !=0
|
2933 |
|
|
005703 -- tst r3
|
2934 |
|
|
001404 -- beq L3 (.+4) -- error if !=0
|
2935 |
|
|
#10460
|
2936 |
|
|
032726 -- L2: bit #3,(sp)+ -- check V,C bits
|
2937 |
|
|
000003
|
2938 |
|
|
001001 -- bne L3 (.+1) -- if V or C =1, ignore
|
2939 |
|
|
000000 -- halt
|
2940 |
|
|
062700 -- L3: add #6,r0 --
|
2941 |
|
|
000006 --
|
2942 |
|
|
077527 -- sob r5,L1 (.-23)
|
2943 |
|
|
000000 -- halt
|
2944 |
|
|
# r q
|
2945 |
|
|
# 6249 014151 * 9158 021706 + 4989 011575 -> 57233331 001551,047663 y n
|
2946 |
|
|
# 5194 012112 * -23807 121401 + -3990 170152 -> -123657548 174241,021264 n y
|
2947 |
|
|
# -19943 131031 * 27112 064750 + -16037 140533 -> -540710653 157705,064403 y n
|
2948 |
|
|
# -20493 127763 * -23858 121316 + 10744 024770 -> 488932738 016444,102602 y y
|
2949 |
|
|
#
|
2950 |
|
|
# -12549 147373 * 2397 004535 + -11187 152115 -> -30091140 177064,154174 n n
|
2951 |
|
|
# 22620 054134 * -9272 155710 + -19907 131075 -> -209752547 171577,067035 y y
|
2952 |
|
|
# 10723 024743 * 7931 017373 + 9824 023140 -> 85053937 002421,150761 n n
|
2953 |
|
|
# -3548 171044 * -15677 141303 + 3019 005713 -> 55625015 001520,142467 n y
|
2954 |
|
|
#
|
2955 |
|
|
## 1 000001 * -32767 100001 + 0 000000 -> -32767 177777,100001 V=0
|
2956 |
|
|
## -1 177777 * 32767 077777 + 0 000000 -> -32767 177777,100001 V=0
|
2957 |
|
|
# 1 000001 * -32768 100000 + 0 000000 -> -32768 177777,100000 V=1
|
2958 |
|
|
# -1 177777 * ...... ...... + 0 000000 -> -32768 177777,100000 V=1
|
2959 |
|
|
#
|
2960 |
|
|
# 32767 077777 * 32767 077777 + 32766 077776 -> 1073709055 037777,077777 V=0
|
2961 |
|
|
# 32767 077777 * ............ + ............ -> 1073709056 037777,100000 V=1
|
2962 |
|
|
# 32767 077777 * -32767 100001 + -32766 100002 ->-1073709055 140000,100001 V=0
|
2963 |
|
|
# 32767 077777 * ............ + ............ ->-1073709056 140000,100000 V=1
|
2964 |
|
|
#
|
2965 |
|
|
# 32767 077777 * ............ + ............ -> 1073741824 040000,000000 V=1
|
2966 |
|
|
##32767 077777 * ............ + ............ ->-2147483648 100000,000000 V=1
|
2967 |
|
|
#
|
2968 |
|
|
#
|
2969 |
|
|
wal 010500 -- data 1:
|
2970 |
|
|
bwm 63
|
2971 |
|
|
000000 -- (000000,000042, 000005) 34/ 5 -> q: 6 r: 4
|
2972 |
|
|
000042 --
|
2973 |
|
|
000005 --
|
2974 |
|
|
000000 -- (000000,000042, 177773) 34/-5 -> q:-6 r: 4
|
2975 |
|
|
000042 --
|
2976 |
|
|
177773 --
|
2977 |
|
|
177777 -- (177777,177736, 000005) -34/ 5 -> q:-6 r:-4
|
2978 |
|
|
177736 --
|
2979 |
|
|
#010520
|
2980 |
|
|
000005 --
|
2981 |
|
|
177777 -- (177777,177736, 177773) -34/-5 -> q: 6 r:-4
|
2982 |
|
|
177736 --
|
2983 |
|
|
177773 --
|
2984 |
|
|
001551 -- (001551,047663, 014151) 57233331 / 6249
|
2985 |
|
|
047663 -- -> q: 9158 r: 4989
|
2986 |
|
|
014151 --
|
2987 |
|
|
174241 -- (174241,021264, 012112) -123657548 / 5194
|
2988 |
|
|
#010540
|
2989 |
|
|
021264 -- -> q: -23807 r: -3990
|
2990 |
|
|
012112 --
|
2991 |
|
|
157705 -- (157705,064403, 131031) -540710653 / -19943
|
2992 |
|
|
064403 -- -> q: 27112 r: -16037
|
2993 |
|
|
131031 --
|
2994 |
|
|
016444 -- (016444,102602, 127763) 488932738 / -20493
|
2995 |
|
|
102602 -- -> q: -23858 r: 10744
|
2996 |
|
|
127763 --
|
2997 |
|
|
#010560
|
2998 |
|
|
177064 -- (177064,154174, 147373) -30091140 / -12549
|
2999 |
|
|
154174 -- -> q: 2397 r: -11187
|
3000 |
|
|
147373 --
|
3001 |
|
|
171577 -- (171577,067035, 054134) -209752547 / 22620
|
3002 |
|
|
067035 -- -> q: -9272 r: -19907
|
3003 |
|
|
054134 --
|
3004 |
|
|
002421 -- (002421,150761, 024743) 85053937 / 10723
|
3005 |
|
|
150761 -- -> q: 7931 r: 9824
|
3006 |
|
|
#010600
|
3007 |
|
|
024743 --
|
3008 |
|
|
001520 -- (001520,142467, 171044) 55625015 / -3548
|
3009 |
|
|
142467 -- -> q: -15677 r: 3019
|
3010 |
|
|
171044 --
|
3011 |
|
|
001520 -- (001520,142467,000000) 55625015 / 0
|
3012 |
|
|
142467 --
|
3013 |
|
|
000000 --
|
3014 |
|
|
000000 -- (000000,000000,021706) 0 / 9158
|
3015 |
|
|
#010620
|
3016 |
|
|
000000 --
|
3017 |
|
|
021706 --
|
3018 |
|
|
177777 -- (177777,100000,000001) -32768 / 1
|
3019 |
|
|
100000 --
|
3020 |
|
|
000001 --
|
3021 |
|
|
177777 -- (177777,100000,177777) -32768 / -1
|
3022 |
|
|
100000 --
|
3023 |
|
|
177777 --
|
3024 |
|
|
#010640
|
3025 |
|
|
037777 -- (037777,077777,077777) 1073709055 / 32767
|
3026 |
|
|
077777 --
|
3027 |
|
|
077777 --
|
3028 |
|
|
037777 -- (037777,100000,077777) 1073709056 / 32767
|
3029 |
|
|
100000 --
|
3030 |
|
|
077777 --
|
3031 |
|
|
140000 -- (140000,100001,077777) -1073709055 / 32767
|
3032 |
|
|
100001 --
|
3033 |
|
|
#010660
|
3034 |
|
|
077777 --
|
3035 |
|
|
140000 -- (140000,100000,077777) -1073709056 / 32767
|
3036 |
|
|
100000 --
|
3037 |
|
|
077777 --
|
3038 |
|
|
040000 -- (040000,000000,077777) 1073741824 / 32767
|
3039 |
|
|
000000 --
|
3040 |
|
|
077777 --
|
3041 |
|
|
#
|
3042 |
|
|
C Exec code 31 (test DIV instruction, also ADC,SXT)
|
3043 |
|
|
C Exec test 31.1 (test div)
|
3044 |
|
|
#
|
3045 |
|
|
wr0 010500 -- r0=10500 (input data)
|
3046 |
|
|
wr1 010700 -- r1=10700 (output data)
|
3047 |
|
|
wr2 000025 -- r2=25 (test count)
|
3048 |
|
|
wr3 177776 -- r3=177776 (#PSW)
|
3049 |
|
|
wsp 001400 -- sp=1400
|
3050 |
|
|
rst -- console reset ; do reset; cont to start with
|
3051 |
|
|
wps 000000 -- clear psw ; psw cc code dump below
|
3052 |
|
|
wpc 010400 -- pc=10400
|
3053 |
|
|
cont -- cont @ 10400
|
3054 |
|
|
wtgo
|
3055 |
|
|
rr0 d=010676 -- ! r0
|
3056 |
|
|
rr1 d=011076 -- ! r1
|
3057 |
|
|
rpc d=010420 -- ! pc
|
3058 |
|
|
wal 010700 --
|
3059 |
|
|
brm 63
|
3060 |
|
|
d=000000 -- ! mem(10700) div 000000, 000042,000005 -> n0z0v0c0
|
3061 |
|
|
d=000006 -- ! mem(10702) 34/ 5 -> 6,4
|
3062 |
|
|
d=000004 -- ! mem(10704)
|
3063 |
|
|
d=000010 -- ! mem(10706) div 000000,000042, 177773 -> n1z0v0c0
|
3064 |
|
|
d=177772 -- ! mem(10710) 34/-5 -> -6,4
|
3065 |
|
|
d=000004 -- ! mem(10712)
|
3066 |
|
|
d=000010 -- ! mem(10714) div 177777,177736, 000005 -> n1z0v0c0
|
3067 |
|
|
d=177772 -- ! mem(10716) -34/ 5 -> -6,-4
|
3068 |
|
|
d=177774 -- ! mem(10720)
|
3069 |
|
|
d=000000 -- ! mem(10722) div 177777,177736, 177773 -> n0z0v0c0
|
3070 |
|
|
d=000006 -- ! mem(10724) -34/-5 -> 6,-4
|
3071 |
|
|
d=177774 -- ! mem(10726)
|
3072 |
|
|
d=000000 -- ! mem(10730) div 001551,047663, 014151 -> n0z0v0c0
|
3073 |
|
|
d=021706 -- ! mem(10732) 57233331/6249 -> 9158,4989
|
3074 |
|
|
d=011575 -- ! mem(10734)
|
3075 |
|
|
d=000010 -- ! mem(10736) div 174241,021264, 012112 -> n1z0v0c0
|
3076 |
|
|
d=121401 -- ! mem(10740) -123657548/5194 -> -23807,-3990
|
3077 |
|
|
d=170152 -- ! mem(10742)
|
3078 |
|
|
d=000000 -- ! mem(10744) div 157705,064403, 131031 -> n0z0v0c0
|
3079 |
|
|
d=064750 -- ! mem(10746) -540710653/-19943 -> 27112,-16037
|
3080 |
|
|
d=140533 -- ! mem(10750)
|
3081 |
|
|
d=000010 -- ! mem(10752) div 016444,102602, 127763 -> n1z0v0c0
|
3082 |
|
|
d=121316 -- ! mem(10754) 488932738/-20493 -> -23858, 10744
|
3083 |
|
|
d=024770 -- ! mem(10756)
|
3084 |
|
|
d=000000 -- ! mem(10760) div 177064,154174, 147373 -> n0z0v0c0
|
3085 |
|
|
d=004535 -- ! mem(10762) -30091140/-12549 -> 2397,-11187
|
3086 |
|
|
d=152115 -- ! mem(10764)
|
3087 |
|
|
d=000010 -- ! mem(10766) div 171577,067035, 054134 -> n1z0v0c0
|
3088 |
|
|
d=155710 -- ! mem(10770) -209752547/22620 -> -9272,-19907
|
3089 |
|
|
d=131075 -- ! mem(10772)
|
3090 |
|
|
d=000000 -- ! mem(10774) div 002421,150761, 024743 -> n0z0v0c0
|
3091 |
|
|
d=017373 -- ! mem(10776) 85053937/10723 -> 7931,9824
|
3092 |
|
|
d=023140 -- ! mem(11000)
|
3093 |
|
|
d=000010 -- ! mem(11002) div 001520,142467, 171044 -> n1z0v0c0
|
3094 |
|
|
d=141303 -- ! mem(11004) 55625015/-3548 -> -15677,3019
|
3095 |
|
|
d=005713 -- ! mem(11006)
|
3096 |
|
|
d=000007 -- ! mem(11010) div 001520,142467,000000 -> n0z1v1c1
|
3097 |
|
|
d=001520 -- ! mem(11012) 55625015/0 -> V=1, keep regs
|
3098 |
|
|
d=142467 -- ! mem(11014)
|
3099 |
|
|
d=000004 -- ! mem(11016) div 000000,000000,021706 -> n0z1v1c0
|
3100 |
|
|
d=000000 -- ! mem(11020) 0/9158 -> 0,0
|
3101 |
|
|
d=000000 -- ! mem(11022)
|
3102 |
|
|
d=000012 -- ! mem(11024) div 177777,100000,000001->n1z0v1c0 [[s:10]]
|
3103 |
|
|
d=177777 -- ! mem(11026) -32768/1 -> overflow [[s:100000]]
|
3104 |
|
|
d=100000 -- ! mem(11030) [[s:000000]]
|
3105 |
|
|
d=000002 -- ! mem(11032) div 177777,100000,177777 -> n0z0v1c0 ?? 2
|
3106 |
|
|
d=177777 -- ! mem(11034) -32768/-1 -> overflow
|
3107 |
|
|
d=100000 -- ! mem(11036)
|
3108 |
|
|
d=000000 -- ! mem(11040) div 037777,077777,077777 -> n0z0v0c0
|
3109 |
|
|
d=077777 -- ! mem(11042) 1073709055/32767 -> 32767,32766
|
3110 |
|
|
d=077776 -- ! mem(11044)
|
3111 |
|
|
d=000002 -- ! mem(11046) div 037777,100000,077777 -> n0z0v1c0
|
3112 |
|
|
d=037777 -- ! mem(11050) 1073709056/32767 -> overflow
|
3113 |
|
|
d=100000 -- ! mem(11052)
|
3114 |
|
|
d=000010 -- ! mem(11054) div 140000,100001,077777 -> n1z0v0c0
|
3115 |
|
|
d=100001 -- ! mem(11056) -1073709055/32767 -> -32767,-32766
|
3116 |
|
|
d=100002 -- ! mem(11060)
|
3117 |
|
|
d=000012 -- ! mem(11062) div 140000,100000,077777->n1z0v1c0 [[s:10]]
|
3118 |
|
|
d=140000 -- ! mem(11064) -1073709056/32767 -> overflow [[s:100000]]
|
3119 |
|
|
d=100000 -- ! mem(11066) [[s:000000]]
|
3120 |
|
|
d=000002 -- ! mem(11070) div 040000,000000,077777 -> n0z0v1c0
|
3121 |
|
|
d=040000 -- ! mem(11072) 1073741824/32767 -> overflow
|
3122 |
|
|
d=000000 -- ! mem(11074)
|
3123 |
|
|
#
|
3124 |
|
|
# simh notes:
|
3125 |
|
|
# 1. a quotient of 100000 leads to an overflow (V=1) on the W11
|
3126 |
|
|
# simh will not indicate overflow and returns q=100000
|
3127 |
|
|
#
|
3128 |
|
|
#----
|
3129 |
|
|
C Exec test 31.2 (test mul after div)
|
3130 |
|
|
#
|
3131 |
|
|
wr0 010500 -- r0=10500 (input data from DIV)
|
3132 |
|
|
wr1 010700 -- r1=10700 (output data from DIV)
|
3133 |
|
|
wr5 000016 -- r5=16 (test count)
|
3134 |
|
|
wsp 001400 -- sp=1400
|
3135 |
|
|
stapc 010420 -- start @ 10420
|
3136 |
|
|
wtgo
|
3137 |
|
|
rr0 d=010624 -- ! r0
|
3138 |
|
|
rr1 d=011024 -- ! r1
|
3139 |
|
|
rr2 d=000000 -- ! r2
|
3140 |
|
|
rr3 d=000000 -- ! r3
|
3141 |
|
|
rr5 d=000000 -- ! r5
|
3142 |
|
|
rpc d=010500 -- ! pc
|
3143 |
|
|
#-----------------------------------------------------------------------------
|
3144 |
|
|
C Setup code 32 [base 11100; use 111-112] (PIRQ test)
|
3145 |
|
|
# The code will exercise all 7 pirq interrupt levels:
|
3146 |
|
|
# set 1+3 -> handle 3, set 7 -> handle 7, set 6+4 -> handle 6
|
3147 |
|
|
# -> handle 4, set 5+2 -> handle 5 -> handle 2 > handle 1
|
3148 |
|
|
#
|
3149 |
|
|
wal 011100 -- code:
|
3150 |
|
|
bwm 14
|
3151 |
|
|
000237 -- spl 7
|
3152 |
|
|
011425 -- mov (r4),(r5)+ ; save PSW
|
3153 |
|
|
012713 -- mov #1000,(r3) ; set PIRQ 1
|
3154 |
|
|
001000
|
3155 |
|
|
011325 -- mov (r3),(r5)+ ; save PIRQ
|
3156 |
|
|
112763 -- movb #12,1(r3) ; set PIRQ 1+3
|
3157 |
|
|
000012
|
3158 |
|
|
000001
|
3159 |
|
|
#11120
|
3160 |
|
|
011325 -- mov (r3),(r5)+ ; save PIRQ
|
3161 |
|
|
000232 -- spl 2 ; now pri=2
|
3162 |
|
|
000240 -- nop ; allow interrupt to happen
|
3163 |
|
|
000230 -- spl 0 ; now pri=0
|
3164 |
|
|
#11130
|
3165 |
|
|
000240 -- nop ; allow interrupt to happen
|
3166 |
|
|
000000 -- halt
|
3167 |
|
|
#-----
|
3168 |
|
|
wal 000240 -- vector: 240
|
3169 |
|
|
bwm 2
|
3170 |
|
|
011134 -- PC:11134
|
3171 |
|
|
000340 -- PS:pri=7
|
3172 |
|
|
#-----
|
3173 |
|
|
wal 011134 -- code: (vector 240)
|
3174 |
|
|
bwm 18
|
3175 |
|
|
011300 -- mov (r3),r0 ; get pirq
|
3176 |
|
|
010625 -- mov sp,(r5)+ ; save sp
|
3177 |
|
|
#11140
|
3178 |
|
|
010025 -- mov r0,(r5)+ ; save pirq
|
3179 |
|
|
110014 -- movb r0,(r4) ; PSW=PIRQ (sets priority)
|
3180 |
|
|
042700 -- bic #177761,r0 ; mask out index bits
|
3181 |
|
|
177761
|
3182 |
|
|
010001 -- mov r0,r1 ; r0 is word index (pri*2)
|
3183 |
|
|
006201 -- asr r1 ; r1 is byte index (pri*1)
|
3184 |
|
|
012702 -- mov #400,r2
|
3185 |
|
|
000400
|
3186 |
|
|
#11160
|
3187 |
|
|
072201 -- ash r1,r2 ; r2 = 1<<(pri)
|
3188 |
|
|
040213 -- bic r2,(r3) ; clear current level in pirq
|
3189 |
|
|
010246 -- mov r2,-(sp) ; save pirq level mask
|
3190 |
|
|
056013 -- bis 11200(r0),(r3) ; trigger new pirq's
|
3191 |
|
|
011200
|
3192 |
|
|
000240 -- noop
|
3193 |
|
|
012625 -- mov (sp)+,(r5)+ ; save pirq level mask
|
3194 |
|
|
000002 -- rti
|
3195 |
|
|
#11200
|
3196 |
|
|
#-----
|
3197 |
|
|
wal 011200 -- data:
|
3198 |
|
|
bwm 8
|
3199 |
|
|
000000 -- mem(11200)=0 ; new pirq @ level 0
|
3200 |
|
|
000000 -- mem(11202)=0 ; new pirq @ level 1
|
3201 |
|
|
000000 -- mem(11204)=0 ; new pirq @ level 2
|
3202 |
|
|
100000 -- mem(11206)=100000 ; new pirq @ level 3 -> 7
|
3203 |
|
|
022000 -- mem(11210)=022000 ; new pirq @ level 4 -> 5+2
|
3204 |
|
|
000000 -- mem(11212)=0 ; new pirq @ level 5
|
3205 |
|
|
000000 -- mem(11214)=0 ; new pirq @ level 6
|
3206 |
|
|
050000 -- mem(11216)=050000 ; new pirq @ level 7 -> 6+4
|
3207 |
|
|
#
|
3208 |
|
|
C Exec code 32 (PIRQ test)
|
3209 |
|
|
#
|
3210 |
|
|
wr3 177772 -- r3=177772 (#PIRQ)
|
3211 |
|
|
wr4 177776 -- r4=177776 (#PSW)
|
3212 |
|
|
wr5 011220 -- r1=11220 (output data)
|
3213 |
|
|
wsp 001400 -- sp=1400
|
3214 |
|
|
stapc 011100 -- start @ 11100
|
3215 |
|
|
wtgo
|
3216 |
|
|
rr5 d=011300 -- ! r5
|
3217 |
|
|
rsp d=001400 -- ! sp
|
3218 |
|
|
rpc d=011134 -- ! pc
|
3219 |
|
|
rps d=000000 -- ! PSW
|
3220 |
|
|
wal 177772 --
|
3221 |
|
|
rmi d=000000 -- ! PIRQ
|
3222 |
|
|
wal 011220 --
|
3223 |
|
|
brm 24
|
3224 |
|
|
d=000340 -- ! mem(11220) PSW after SPL 7
|
3225 |
|
|
d=001042 -- ! mem(11222) PIRQ when 1 set
|
3226 |
|
|
d=005146 -- ! mem(11224) PIRQ when 1+3 set
|
3227 |
|
|
d=001374 -- ! mem(11226) -> PI:3 SP
|
3228 |
|
|
d=005146 -- ! mem(11230) PIRQ (3+1 pending)
|
3229 |
|
|
d=001366 -- ! mem(11232) -> PI:7 SP
|
3230 |
|
|
d=101356 -- ! mem(11234) PIRQ (7+1 pending)
|
3231 |
|
|
d=100000 -- ! mem(11236) <- PI:7 mask
|
3232 |
|
|
d=001366 -- ! mem(11240) -> PI:6 SP
|
3233 |
|
|
d=051314 -- ! mem(11242) PIRQ (6+4+1 pending)
|
3234 |
|
|
d=040000 -- ! mem(11244) <- PI:6 mask
|
3235 |
|
|
d=001366 -- ! mem(11246) -> PI:4 SP
|
3236 |
|
|
d=011210 -- ! mem(11250) PIRQ (4+1 pending)
|
3237 |
|
|
d=001360 -- ! mem(11252) -> PI:5 SP
|
3238 |
|
|
d=023252 -- ! mem(11254) PIRQ (5+2+1 pending)
|
3239 |
|
|
d=020000 -- ! mem(11256) <- PI:5 mask
|
3240 |
|
|
d=010000 -- ! mem(11260) <- PI:4 mask
|
3241 |
|
|
d=004000 -- ! mem(11262) <- PI:3 mask
|
3242 |
|
|
d=001374 -- ! mem(11264) -> PI:2 SP
|
3243 |
|
|
d=003104 -- ! mem(11266) PIRQ
|
3244 |
|
|
d=002000 -- ! mem(11270) <- PI:2 mask
|
3245 |
|
|
d=001374 -- ! mem(11272) -> PI:1 SP
|
3246 |
|
|
d=001042 -- ! mem(11274) PIRQ
|
3247 |
|
|
d=001000 -- ! mem(11276) <- PI:1 mask
|
3248 |
|
|
#
|
3249 |
|
|
wal 000240 -- vector: 240 -> trap catcher again
|
3250 |
|
|
bwm 2
|
3251 |
|
|
000242 -- PC:242
|
3252 |
|
|
000000 -- PS:0
|
3253 |
|
|
#-----------------------------------------------------------------------------
|
3254 |
|
|
C Setup code 33 [base 11200; use 112-113] (adc(b) and sbc(b) test)
|
3255 |
|
|
#
|
3256 |
|
|
wal 011200 -- code test 1: (adc)
|
3257 |
|
|
bwm 5
|
3258 |
|
|
006020 -- L1: ror (r0)+
|
3259 |
|
|
005520 -- adc (r0)+
|
3260 |
|
|
006120 -- rol (r0)+
|
3261 |
|
|
077104 -- sob r1,L1 (.-4)
|
3262 |
|
|
000000 -- halt
|
3263 |
|
|
#-----
|
3264 |
|
|
wal 011220 -- code test 2: (sbc)
|
3265 |
|
|
bwm 5
|
3266 |
|
|
006020 -- L1: ror (r0)+
|
3267 |
|
|
005620 -- sbc (r0)+
|
3268 |
|
|
006120 -- rol (r0)+
|
3269 |
|
|
077104 -- sob r1,L1 (.-4)
|
3270 |
|
|
000000 -- halt
|
3271 |
|
|
#-----
|
3272 |
|
|
wal 011240 -- code test 3: (adcb)
|
3273 |
|
|
bwm 5
|
3274 |
|
|
006020 -- L1: ror (r0)+
|
3275 |
|
|
105520 -- adcb (r0)+
|
3276 |
|
|
106120 -- rolb (r0)+
|
3277 |
|
|
077104 -- sob r1,L1 (.-4)
|
3278 |
|
|
000000 -- halt
|
3279 |
|
|
#-----
|
3280 |
|
|
wal 011260 -- code test 4: (sbcb)
|
3281 |
|
|
bwm 5
|
3282 |
|
|
006020 -- L1: ror (r0)+
|
3283 |
|
|
105620 -- sbcb (r0)+
|
3284 |
|
|
106120 -- rolb (r0)+
|
3285 |
|
|
077104 -- sob r1,L1 (.-4)
|
3286 |
|
|
000000 -- halt
|
3287 |
|
|
#-----
|
3288 |
|
|
wal 011300 -- data test 1: (adc)
|
3289 |
|
|
bwm 9
|
3290 |
|
|
000000 -- 177776 + 0 -> 177776 + 0
|
3291 |
|
|
177776
|
3292 |
|
|
000000
|
3293 |
|
|
000001 -- 177776 + 1 -> 177777 + 0
|
3294 |
|
|
177776
|
3295 |
|
|
000000
|
3296 |
|
|
000001 -- 177777 + 1 -> 000000 + 1
|
3297 |
|
|
177777
|
3298 |
|
|
000000
|
3299 |
|
|
#-----
|
3300 |
|
|
wal 011324 -- data test 2: (sbc)
|
3301 |
|
|
bwm 9
|
3302 |
|
|
000000 -- 000002 - 0 -> 000002 - 0
|
3303 |
|
|
000002
|
3304 |
|
|
000000
|
3305 |
|
|
000001 -- 000002 - 1 -> 000001 - 0
|
3306 |
|
|
000002
|
3307 |
|
|
000000
|
3308 |
|
|
000001 -- 000000 - 1 -> 177777 - 1
|
3309 |
|
|
000000
|
3310 |
|
|
000000
|
3311 |
|
|
#-----
|
3312 |
|
|
wal 011350 -- data test 3: (adcb)
|
3313 |
|
|
bwm 6
|
3314 |
|
|
000000 -- 376 + 0 -> 376 + 0
|
3315 |
|
|
000376
|
3316 |
|
|
000001 -- 376 + 1 -> 377 + 0
|
3317 |
|
|
000376
|
3318 |
|
|
000001 -- 377 + 1 -> 000 + 1
|
3319 |
|
|
000377
|
3320 |
|
|
#-----
|
3321 |
|
|
wal 011364 -- data test 4: (sbcb)
|
3322 |
|
|
bwm 6
|
3323 |
|
|
000000 -- 002 - 0 -> 002 - 0
|
3324 |
|
|
000002
|
3325 |
|
|
000001 -- 002 - 1 -> 001 - 0
|
3326 |
|
|
000002
|
3327 |
|
|
000001 -- 000 - 1 -> 337 - 1
|
3328 |
|
|
000000
|
3329 |
|
|
#
|
3330 |
|
|
C Exec code 33 (adc and sbc test)
|
3331 |
|
|
C Exec test 33.1 (adc)
|
3332 |
|
|
#
|
3333 |
|
|
wr0 011300 -- r0=11300
|
3334 |
|
|
wr1 000003 -- r1=3
|
3335 |
|
|
wsp 001400 -- sp=1400
|
3336 |
|
|
stapc 011200 -- start @ 11200
|
3337 |
|
|
wtgo
|
3338 |
|
|
rr0 d=011322 -- ! r0=11322
|
3339 |
|
|
rpc d=011212 -- ! pc
|
3340 |
|
|
wal 011300
|
3341 |
|
|
brm 9
|
3342 |
|
|
d=000000 -- ! mem(11300)=000000 -- 177776 + 0 -> 177776 + 0
|
3343 |
|
|
d=177776 -- ! mem(11302)=000000
|
3344 |
|
|
d=000000 -- ! mem(11304)=000000
|
3345 |
|
|
d=000000 -- ! mem(11306)=000000 -- 177776 + 1 -> 177777 + 0
|
3346 |
|
|
d=177777 -- ! mem(11310)=000000
|
3347 |
|
|
d=000000 -- ! mem(11312)=000000
|
3348 |
|
|
d=000000 -- ! mem(11314)=000000 -- 177777 + 1 -> 000000 + 1
|
3349 |
|
|
d=000000 -- ! mem(11316)=000000
|
3350 |
|
|
d=000001 -- ! mem(11320)=000000
|
3351 |
|
|
#----
|
3352 |
|
|
C Exec test 33.2 (sbc)
|
3353 |
|
|
#
|
3354 |
|
|
wr0 011324 -- r0=11324
|
3355 |
|
|
wr1 000003 -- r1=3
|
3356 |
|
|
wsp 001400 -- sp=1400
|
3357 |
|
|
stapc 011220 -- start @ 11220
|
3358 |
|
|
wtgo
|
3359 |
|
|
rr0 d=011346 -- ! r0=11346
|
3360 |
|
|
rpc d=011232 -- ! pc
|
3361 |
|
|
wal 011324
|
3362 |
|
|
brm 9
|
3363 |
|
|
d=000000 -- ! mem(11324)=000000 -- 000002 - 0 -> 000002 - 0
|
3364 |
|
|
d=000002 -- ! mem(11326)=000000
|
3365 |
|
|
d=000000 -- ! mem(11330)=000000
|
3366 |
|
|
d=000000 -- ! mem(11332)=000000 -- 000002 - 1 -> 000001 - 0
|
3367 |
|
|
d=000001 -- ! mem(11334)=000000
|
3368 |
|
|
d=000000 -- ! mem(11336)=000000
|
3369 |
|
|
d=000000 -- ! mem(11340)=000000 -- 000000 - 1 -> 177777 - 1
|
3370 |
|
|
d=177777 -- ! mem(11342)=000000
|
3371 |
|
|
d=000001 -- ! mem(11344)=000000
|
3372 |
|
|
#----
|
3373 |
|
|
C Exec test 33.3 (adcb)
|
3374 |
|
|
#
|
3375 |
|
|
wr0 011350 -- r0=11350
|
3376 |
|
|
wr1 000003 -- r1=3
|
3377 |
|
|
wsp 001400 -- sp=1400
|
3378 |
|
|
stapc 011240 -- start @ 11240
|
3379 |
|
|
wtgo
|
3380 |
|
|
rr0 d=011364 -- ! r0=11364
|
3381 |
|
|
rpc d=011252 -- ! pc
|
3382 |
|
|
wal 011350
|
3383 |
|
|
brm 6
|
3384 |
|
|
d=000000 -- ! mem(11350)=000000 -- 376 + 0 -> 376 + 0
|
3385 |
|
|
d=000376 -- ! mem(11352)=000000
|
3386 |
|
|
d=000000 -- ! mem(11354)=000000 -- 376 + 1 -> 377 + 0
|
3387 |
|
|
d=000377 -- ! mem(11356)=000000
|
3388 |
|
|
d=000000 -- ! mem(11360)=000000 -- 377 + 1 -> 000 + 1
|
3389 |
|
|
d=000400 -- ! mem(11362)=000000
|
3390 |
|
|
#----
|
3391 |
|
|
C Exec test 33.4 (sbcb)
|
3392 |
|
|
#
|
3393 |
|
|
wr0 011364 -- r0=11364
|
3394 |
|
|
wr1 000003 -- r1=3
|
3395 |
|
|
wsp 001400 -- sp=1400
|
3396 |
|
|
stapc 011260 -- start @ 11260
|
3397 |
|
|
wtgo
|
3398 |
|
|
rr0 d=011400 -- ! r0=11400
|
3399 |
|
|
rpc d=011272 -- ! pc
|
3400 |
|
|
wal 011364
|
3401 |
|
|
brm 6
|
3402 |
|
|
d=000000 -- ! mem(11364)=000000 -- 002 - 0 -> 002 - 0
|
3403 |
|
|
d=000002 -- ! mem(11366)=000000
|
3404 |
|
|
d=000000 -- ! mem(11370)=000000 -- 002 - 1 -> 001 - 0
|
3405 |
|
|
d=000001 -- ! mem(11372)=000000
|
3406 |
|
|
d=000000 -- ! mem(11374)=000000 -- 000 - 1 -> 337 - 1
|
3407 |
|
|
d=000777 -- ! mem(11377)=000000
|
3408 |
|
|
#-----------------------------------------------------------------------------
|
3409 |
|
|
C Setup code 34 [base 11400; use 114-115] (11/34 self test code)
|
3410 |
|
|
# code adapted from M9312 23-248F1 console PROM, the 11/04-34 Diagnostic PROM
|
3411 |
|
|
#
|
3412 |
|
|
wal 011400 -- code:
|
3413 |
|
|
bwm 51
|
3414 |
|
|
005000 -- clr r0 ; r0=000000 c=0
|
3415 |
|
|
005200 -- inc r0 ; r0=000001 c=0
|
3416 |
|
|
005100 -- com r0 ; r0=177776 c=1
|
3417 |
|
|
006200 -- asr r0 ; r0=177777 c=0
|
3418 |
|
|
006300 -- asl r0 ; r0=177776 c=1
|
3419 |
|
|
006000 -- ror r0 ; r0=177777 c=0
|
3420 |
|
|
005700 -- tst r0 ; r0=177777 c=0 ?impact unclear?
|
3421 |
|
|
005400 -- neg r0 ; r0=000001 c=1
|
3422 |
|
|
#11420
|
3423 |
|
|
005300 -- dec r0 ; r0=000000 c=1
|
3424 |
|
|
005600 -- sbc r0 ; r0=177777 c=1
|
3425 |
|
|
006100 -- rol r0 ; r0=177777 c=1
|
3426 |
|
|
005500 -- adc r0 ; r0=000000 c=1
|
3427 |
|
|
000300 -- swab r0 ; r0=000000 c=0
|
3428 |
|
|
001401 -- beq .+1 ;
|
3429 |
|
|
000000 -- halt ;
|
3430 |
|
|
012702 -- mov #data0,r2 ; r2=011560
|
3431 |
|
|
#11440
|
3432 |
|
|
011560
|
3433 |
|
|
011203 -- mov (r2),r3 ; r2=011560 r3=011560
|
3434 |
|
|
022203 -- cmp (r2)+,r3 ; r2=011562 r3=011560
|
3435 |
|
|
001401 -- beq .+1 ;
|
3436 |
|
|
000000 -- halt ;
|
3437 |
|
|
063203 -- add @(r2)+,r3 ; r2=011564 r3=<2*11560>
|
3438 |
|
|
165203 -- sub @-(r2),r3 ; r2=011562 r3=011560
|
3439 |
|
|
044203 -- bic -(r2),r3 ; r2=011560 r3=000000
|
3440 |
|
|
#11460
|
3441 |
|
|
056203 -- bis 12(r2),r3 ; r2=011560 r3=011566
|
3442 |
|
|
000012
|
3443 |
|
|
037203 -- bis @12(r2),r3 ; r2=011560 r3=011566
|
3444 |
|
|
000012
|
3445 |
|
|
001001 -- bne .+1 ;
|
3446 |
|
|
000000 -- halt ;
|
3447 |
|
|
010701 -- mov pc,r1 ; r1=011476
|
3448 |
|
|
000121 -- jmp (r1)+ ; jump 1.self 2. next; r1=011500
|
3449 |
|
|
#11500
|
3450 |
|
|
012701 -- mov #L2,r1 ; r1=011510
|
3451 |
|
|
011510
|
3452 |
|
|
000131 -- jmp @(r1)+ ; r1=011512 pc=011506
|
3453 |
|
|
000111 -- L1:jmp (r1) ; r1=011512 pc=011512
|
3454 |
|
|
011506 -- L2:.word L1
|
3455 |
|
|
105737 -- tstb data1 ;
|
3456 |
|
|
011564
|
3457 |
|
|
001401 -- beq .+1 ;
|
3458 |
|
|
#11520
|
3459 |
|
|
000000 -- halt ;
|
3460 |
|
|
010204 -- mov r2,r4 ; keep r2 for later check
|
3461 |
|
|
022424 -- cmp (r4)+,(r4)+ ; r4=011564
|
3462 |
|
|
105724 -- tstb (r4)+ ; r4=011565 (r4)+=000
|
3463 |
|
|
001401 -- beq .+1 ;
|
3464 |
|
|
000000 -- halt ;
|
3465 |
|
|
105714 -- tstb (r4) ; r4=011565 (r4)=200
|
3466 |
|
|
100402 -- bmi .+2 ;
|
3467 |
|
|
#11540
|
3468 |
|
|
000000 -- halt ;
|
3469 |
|
|
000000 -- halt ;
|
3470 |
|
|
000000 -- halt ;
|
3471 |
|
|
#-----
|
3472 |
|
|
wal 011560 -- data:
|
3473 |
|
|
bwm 8
|
3474 |
|
|
011560 -- data0: .word data0
|
3475 |
|
|
011560 -- .word data0
|
3476 |
|
|
100000 -- data1: .byte 000,200
|
3477 |
|
|
177777 -- data2: .word 177777
|
3478 |
|
|
011566 -- .word data2
|
3479 |
|
|
011566 -- .word data2
|
3480 |
|
|
000700 -- .word mem+0
|
3481 |
|
|
000701 -- .word mem+1
|
3482 |
|
|
#
|
3483 |
|
|
C Exec code 34 (11/34 self test code)
|
3484 |
|
|
# D RE RQ FU DAT
|
3485 |
|
|
stapc 011400 -- start @ 11400
|
3486 |
|
|
wtgo
|
3487 |
|
|
rr0 d=000000 -- ! r0
|
3488 |
|
|
rr1 d=011512 -- ! r1
|
3489 |
|
|
rr2 d=011560 -- ! r2
|
3490 |
|
|
rr3 d=011566 -- ! r3
|
3491 |
|
|
rr4 d=011565 -- ! r4
|
3492 |
|
|
rpc d=011546 -- ! pc
|
3493 |
|
|
#-----------------------------------------------------------------------------
|
3494 |
|
|
C Setup code 35 [base 11600; use 116-121] (11/70 self test code)
|
3495 |
|
|
# code adapted from M9312 23-616F1 console PROM, the 11/60-70 Diagnostic PROM
|
3496 |
|
|
#
|
3497 |
|
|
wal 011600 -- code:
|
3498 |
|
|
bwm 117
|
3499 |
|
|
005006 -- clr sp ; sp=000000
|
3500 |
|
|
100404 -- bmi L3 ;
|
3501 |
|
|
102403 -- bvs L3 ;
|
3502 |
|
|
101002 -- bhi L3 ;
|
3503 |
|
|
002401 -- blt L3 ;
|
3504 |
|
|
101401 -- blos L4 ;
|
3505 |
|
|
000000 -- L3: halt ;
|
3506 |
|
|
005306 -- L3: dec sp ; sp=177777
|
3507 |
|
|
#11620
|
3508 |
|
|
100003 -- bpl L5 ;
|
3509 |
|
|
001402 -- beq L5 ;
|
3510 |
|
|
002001 -- bge L5 ;
|
3511 |
|
|
003401 -- ble L6 ;
|
3512 |
|
|
000000 -- L5: halt ;
|
3513 |
|
|
006006 -- L6: ror sp ; sp=077777
|
3514 |
|
|
102002 -- bvc L7 ;
|
3515 |
|
|
103001 -- bcc L7 ;
|
3516 |
|
|
#11640
|
3517 |
|
|
001001 -- bne L8 ;
|
3518 |
|
|
000000 -- L7: halt ;
|
3519 |
|
|
012706 -- L8: mov #125252,sp ; sp=125252
|
3520 |
|
|
125252
|
3521 |
|
|
010600 -- mov sp,r0 ;
|
3522 |
|
|
010001 -- mov r0,r1 ;
|
3523 |
|
|
010102 -- mov r1,r2 ;
|
3524 |
|
|
010203 -- mov r2,r3 ;
|
3525 |
|
|
#11660
|
3526 |
|
|
010304 -- mov r3,r4 ;
|
3527 |
|
|
010405 -- mov r4,r5 ;
|
3528 |
|
|
160501 -- sub r5,r1 ; r1=00000
|
3529 |
|
|
002401 -- blt L9a ;
|
3530 |
|
|
001401 -- beq L9 ;
|
3531 |
|
|
000000 -- L9a: halt ;
|
3532 |
|
|
006102 -- L9: rol r2 ; r2=052524 c=1
|
3533 |
|
|
103001 -- bcc L10 ;
|
3534 |
|
|
#11700
|
3535 |
|
|
002401 -- blt L11 ;
|
3536 |
|
|
000000 -- L10: halt ;
|
3537 |
|
|
060203 -- L11: add r2,r3 ; r3=177776 (125252+052524)
|
3538 |
|
|
005203 -- inc r3 ; r3=177777
|
3539 |
|
|
005103 -- com r3 ; r3=000000
|
3540 |
|
|
060301 -- add r3,r1 ; r1=000000 c=0
|
3541 |
|
|
103401 -- bcs L12 ;
|
3542 |
|
|
003401 -- ble L13 ;
|
3543 |
|
|
#11720
|
3544 |
|
|
000000 -- L12: halt ;
|
3545 |
|
|
006004 -- L13: ror r4 ; r4=052525
|
3546 |
|
|
050403 -- bis r4,r3 ; r3=052525 (r3 was 0)
|
3547 |
|
|
060503 -- add r5,r3 ; r3=177777 c=0 (125252+052525)
|
3548 |
|
|
005203 -- inc r3 ; r3=000000 c=0 (kept)
|
3549 |
|
|
103402 -- bcs L14 ;
|
3550 |
|
|
005301 -- dec r1 ; r1=177777
|
3551 |
|
|
002401 -- blt L15 ;
|
3552 |
|
|
#11740
|
3553 |
|
|
000000 -- L14: halt ;
|
3554 |
|
|
005100 -- L15: com r0 ; r0=052525
|
3555 |
|
|
101401 -- blos L16 ;
|
3556 |
|
|
000000 -- halt ;
|
3557 |
|
|
040001 -- L16: bic r0,r1 ; r1=125252
|
3558 |
|
|
060101 -- L16: add r1,r1 ; r1=052524 c=1
|
3559 |
|
|
003001 -- bgt L17 ;
|
3560 |
|
|
003401 -- ble L18 ;
|
3561 |
|
|
#11760
|
3562 |
|
|
000000 -- L17: halt ;
|
3563 |
|
|
000301 -- L18: swab r1 ; r1=052125
|
3564 |
|
|
020127 -- cmp r1,#052125 ;
|
3565 |
|
|
052125
|
3566 |
|
|
001004 -- bne L19 ;
|
3567 |
|
|
030405 -- bit r4,r5 ;
|
3568 |
|
|
003002 -- bgt L19 ;
|
3569 |
|
|
005105 -- com r5 ; r5=052525
|
3570 |
|
|
#12000
|
3571 |
|
|
001001 -- bne L20 ;
|
3572 |
|
|
000000 -- L19: halt ;
|
3573 |
|
|
112700 -- L20: movb #177401,r0 ;
|
3574 |
|
|
177401
|
3575 |
|
|
100001 -- bpl L21 ;
|
3576 |
|
|
000000 -- L22: halt ;
|
3577 |
|
|
077002 -- L21: sob r0,L22 ;
|
3578 |
|
|
000261 -- sec ; c=1
|
3579 |
|
|
#12020
|
3580 |
|
|
006100 -- rol r0 ; r0=000001
|
3581 |
|
|
006100 -- rol r0 ; r0=000002
|
3582 |
|
|
006100 -- rol r0 ; r0=000004
|
3583 |
|
|
010001 -- mov r0,r1 ; r1=000004
|
3584 |
|
|
005401 -- neg r1 ; r1=177774
|
3585 |
|
|
005201 -- L23: inc r1 ;
|
3586 |
|
|
077002 -- sob r0,L23 ;
|
3587 |
|
|
005700 -- tst r0 ; here r0=r1=0
|
3588 |
|
|
#12040
|
3589 |
|
|
001002 -- bne L24 ;
|
3590 |
|
|
005701 -- tst r1 ;
|
3591 |
|
|
001401 -- beq L25 ;
|
3592 |
|
|
000000 -- L24: halt ;
|
3593 |
|
|
012706 -- L25: mov #776,sp ;
|
3594 |
|
|
000776 --
|
3595 |
|
|
004767 -- jsr pc,L26 ;
|
3596 |
|
|
000002
|
3597 |
|
|
#12060
|
3598 |
|
|
000000 -- N2: halt ;
|
3599 |
|
|
022716 -- L26: cmp #N2,(sp) ;
|
3600 |
|
|
012060
|
3601 |
|
|
001401 -- beq L27 ;
|
3602 |
|
|
000000 -- halt ;
|
3603 |
|
|
012716 -- L27: mov #N3,(sp) ;
|
3604 |
|
|
012102
|
3605 |
|
|
000207 -- rts pc ;
|
3606 |
|
|
#12100
|
3607 |
|
|
000000 -- halt ;
|
3608 |
|
|
005046 -- N3: clr -(sp) ;
|
3609 |
|
|
012746 -- mov #N4,-(sp) ;
|
3610 |
|
|
012114
|
3611 |
|
|
000002 -- rti ;
|
3612 |
|
|
000000 -- halt ;
|
3613 |
|
|
000137 -- N4: jmp @#N5 ;
|
3614 |
|
|
012122
|
3615 |
|
|
#12120
|
3616 |
|
|
000000 -- halt ;
|
3617 |
|
|
012705 -- N5: mov #160000,r5 ; r5=160000
|
3618 |
|
|
160000
|
3619 |
|
|
005037 -- clr @#6 ;
|
3620 |
|
|
000006
|
3621 |
|
|
012737 -- mov #N6,@#4 ;
|
3622 |
|
|
012150
|
3623 |
|
|
000004
|
3624 |
|
|
#12140
|
3625 |
|
|
012706 -- mov #776,sp ; sp=776
|
3626 |
|
|
000776
|
3627 |
|
|
005715 -- tst (r5) ; will fail, first word of I/O page
|
3628 |
|
|
000000 -- halt ;
|
3629 |
|
|
000000 -- N6: halt ;
|
3630 |
|
|
#
|
3631 |
|
|
C Exec code 35 (11/70 self test code)
|
3632 |
|
|
# D RE RQ FU DAT
|
3633 |
|
|
stapc 011600 -- start @ 11600
|
3634 |
|
|
wtgo
|
3635 |
|
|
rpc d=012152 -- ! pc
|
3636 |
|
|
wal 000004 -- vector: 4 -> trap catcher again
|
3637 |
|
|
bwm 2
|
3638 |
|
|
000006 -- PC:6
|
3639 |
|
|
000000 -- PS:0
|
3640 |
|
|
#-----------------------------------------------------------------------------
|
3641 |
|
|
# Up to here code and data (both input and result) occupied 'fresh' memory.
|
3642 |
|
|
# Easy to debug, but inconvenient when test should be extended later.
|
3643 |
|
|
# From here on, only code will always occupy fresh memory.
|
3644 |
|
|
# Data will be put into the upper part of the 16 kbyte memory:
|
3645 |
|
|
# test vector: 036000 (512 byte area)
|
3646 |
|
|
# result data: 037000 (512 byte area)
|
3647 |
|
|
#-----------------------------------------------------------------------------
|
3648 |
|
|
C Setup code 36 [base 12200] (systematic CMP test)
|
3649 |
|
|
#
|
3650 |
|
|
wal 012200 -- code:
|
3651 |
|
|
bwm 7
|
3652 |
|
|
000230 -- spl 0
|
3653 |
|
|
012400 -- L1: mov (r4)+,r0
|
3654 |
|
|
012401 -- mov (r4)+,r1
|
3655 |
|
|
020001 -- cmp r0,r1
|
3656 |
|
|
011225 -- mov (r2),(r5)+
|
3657 |
|
|
077305 -- sob r3,L1
|
3658 |
|
|
000000 -- halt
|
3659 |
|
|
#
|
3660 |
|
|
C Exec code 36 (systematic CMP test)
|
3661 |
|
|
C Exec test 36.1: data adapted from cmp.s11 code of Begemot p11-2.10c
|
3662 |
|
|
#
|
3663 |
|
|
wal 036000 -- setup test vector:
|
3664 |
|
|
bwm 22
|
3665 |
|
|
000000 -- 000000, 000000 --> nzvc=0100
|
3666 |
|
|
000000 --
|
3667 |
|
|
000001 -- 000001, 000001 --> nzvc=0100
|
3668 |
|
|
000001 --
|
3669 |
|
|
177777 -- 177777, 177777 --> nzvc=0100
|
3670 |
|
|
177777 --
|
3671 |
|
|
000000 -- 000000, 000001 --> nzvc=1001
|
3672 |
|
|
000001 --
|
3673 |
|
|
000000 -- 000000, 177777 --> nzvc=0001
|
3674 |
|
|
177777 --
|
3675 |
|
|
000001 -- 000001, 000000 --> nzvc=0000
|
3676 |
|
|
000000 --
|
3677 |
|
|
177777 -- 177777, 000000 --> nzvc=1000
|
3678 |
|
|
000000 --
|
3679 |
|
|
000001 -- 000001, 177777 --> nzvc=0001
|
3680 |
|
|
177777 --
|
3681 |
|
|
177777 -- 177777, 000001 --> nzvc=1000
|
3682 |
|
|
000001 --
|
3683 |
|
|
077777 -- 077777, 100000 --> nzvc=1011
|
3684 |
|
|
100000 --
|
3685 |
|
|
100000 -- 100000, 077777 --> nzvc=0010
|
3686 |
|
|
077777 --
|
3687 |
|
|
#----
|
3688 |
|
|
wr2 177776 -- r2=177776 -> psw
|
3689 |
|
|
wr3 000013 -- r3=13 -> test count
|
3690 |
|
|
wr4 036000 -- r4=36000 -> input area
|
3691 |
|
|
wr5 037000 -- r5=37000 -> output area
|
3692 |
|
|
wsp 001400 -- sp=1400
|
3693 |
|
|
stapc 012200 -- start @ 12200
|
3694 |
|
|
wtgo
|
3695 |
|
|
rpc d=012216 -- ! pc
|
3696 |
|
|
rr3 d=000000 -- ! r3=0
|
3697 |
|
|
rr4 d=036054 -- ! r4=12354
|
3698 |
|
|
rr5 d=037026 -- ! r5=12426
|
3699 |
|
|
wal 037000 --
|
3700 |
|
|
brm 11
|
3701 |
|
|
d=000004 -- 000000, 000000 --> nzvc=0100
|
3702 |
|
|
d=000004 -- 000001, 000001 --> nzvc=0100
|
3703 |
|
|
d=000004 -- 177777, 177777 --> nzvc=0100
|
3704 |
|
|
d=000011 -- 000000, 000001 --> nzvc=1001
|
3705 |
|
|
d=000001 -- 000000, 177777 --> nzvc=0001
|
3706 |
|
|
d=000000 -- 000001, 000000 --> nzvc=0000
|
3707 |
|
|
d=000010 -- 177777, 000000 --> nzvc=1000
|
3708 |
|
|
d=000001 -- 000001, 177777 --> nzvc=0001
|
3709 |
|
|
d=000010 -- 177777, 000001 --> nzvc=1000
|
3710 |
|
|
d=000013 -- 077777, 100000 --> nzvc=1011
|
3711 |
|
|
d=000002 -- 100000, 077777 --> nzvc=0010
|
3712 |
|
|
#-----------------------------------------------------------------------------
|
3713 |
|
|
C Setup code 37 [base 12300] (systematic DIV test)
|
3714 |
|
|
#
|
3715 |
|
|
wal 012300 -- code:
|
3716 |
|
|
bwm 9
|
3717 |
|
|
000230 -- spl 0
|
3718 |
|
|
012400 -- L1: mov (r4)+,r0
|
3719 |
|
|
012401 -- mov (r4)+,r1
|
3720 |
|
|
071024 -- div (r4)+,r0
|
3721 |
|
|
011225 -- mov (r2),(r5)+
|
3722 |
|
|
010025 -- mov r0,(r5)+
|
3723 |
|
|
010125 -- mov r1,(r5)+
|
3724 |
|
|
077307 -- sob r3,L1
|
3725 |
|
|
#12520
|
3726 |
|
|
000000 -- halt
|
3727 |
|
|
#
|
3728 |
|
|
C Exec code 37 (systematic DIV test)
|
3729 |
|
|
C Exec test 37.1: data adapted from div.s11 code of Begemot p11-2.10c
|
3730 |
|
|
#
|
3731 |
|
|
wal 036000 -- setup test vector:
|
3732 |
|
|
bwm 57
|
3733 |
|
|
000000 -- 0, 4, 0, 7, 0, 4# 4/ 0 -> 0111 0 4
|
3734 |
|
|
000004 --
|
3735 |
|
|
000000 --
|
3736 |
|
|
000000 -- 0, 4, 2, 0, 2, 0# 4/ 2 -> 0000 2 0
|
3737 |
|
|
000004 --
|
3738 |
|
|
000002 --
|
3739 |
|
|
000000 -- 0, 6, 2, 0, 3, 0# 6/ 2 -> 0000 3 0
|
3740 |
|
|
000006 --
|
3741 |
|
|
000002 --
|
3742 |
|
|
000000 -- 0, 4, -2, 10, -2, 0# 4/-2 ->1000 -2 0
|
3743 |
|
|
000004 --
|
3744 |
|
|
177776 --
|
3745 |
|
|
#36030
|
3746 |
|
|
000002 -- 2, 0, 1, 2, 2, 0# 0x20000 / 1
|
3747 |
|
|
000000 --
|
3748 |
|
|
000001 --
|
3749 |
|
|
000002 -- 2, 0, -2, 12, 2, 0# 0x20000 / -2
|
3750 |
|
|
000000 --
|
3751 |
|
|
177776 --
|
3752 |
|
|
100000 -- 100000, 0, 1, 12,100000, 0# 0x80000000 / 1
|
3753 |
|
|
000000 --
|
3754 |
|
|
000001 --
|
3755 |
|
|
177776 -- 177776,177777, -1, 2,177776,177777# -0x10001 / -1
|
3756 |
|
|
177777 --
|
3757 |
|
|
177777 --
|
3758 |
|
|
#36060
|
3759 |
|
|
177777 -- 177777,177773, 2, 10, -2, -1# -5 / 2
|
3760 |
|
|
177773 --
|
3761 |
|
|
000002 --
|
3762 |
|
|
177777 -- 177777,177773, -2, 0, 2, -1# -5 / -2
|
3763 |
|
|
177773 --
|
3764 |
|
|
177776 --
|
3765 |
|
|
177776 -- 177776, 0, 40000, 10, -10, 0# -0x20000/0x4000
|
3766 |
|
|
000000 --
|
3767 |
|
|
040000 --
|
3768 |
|
|
000100 -- 100, 200,177601, 12, 100, 200# 0x400080 / -0x7f
|
3769 |
|
|
000200 --
|
3770 |
|
|
177601 --
|
3771 |
|
|
#36110
|
3772 |
|
|
000000 -- 0, 1, 0, 7, 0, 1 # zero divide
|
3773 |
|
|
000001 --
|
3774 |
|
|
000000 --
|
3775 |
|
|
177777 -- -1, -1, 0, 7, -1, -1 # zero divide
|
3776 |
|
|
177777 --
|
3777 |
|
|
000000 --
|
3778 |
|
|
000000 -- 0, 0, 0, 7, 0, 0 # zero divide
|
3779 |
|
|
000000 --
|
3780 |
|
|
000000 --
|
3781 |
|
|
000001 -- 1, 1, 1, 2, 1, 1 # overflow
|
3782 |
|
|
000001 --
|
3783 |
|
|
000001 --
|
3784 |
|
|
#36140
|
3785 |
|
|
000001 -- 1, 1, -1, 012, 1, 1 # overflow
|
3786 |
|
|
000001 --
|
3787 |
|
|
177777 --
|
3788 |
|
|
177777 -- -1, -1, 1, 010, -1, 0 # wfjm corrected, not overflow
|
3789 |
|
|
177777 --
|
3790 |
|
|
000001 --
|
3791 |
|
|
177777 -- -1, -1, -1, 0, 1, 0 # wfjm corrected, not overflow
|
3792 |
|
|
177777 --
|
3793 |
|
|
177777 --
|
3794 |
|
|
#----
|
3795 |
|
|
wr2 177776 -- r2=177776 -> psw
|
3796 |
|
|
wr3 000023 -- r3=23 -> test count
|
3797 |
|
|
wr4 036000 -- r4=36000 -> input area
|
3798 |
|
|
wr5 037000 -- r5=37000 -> output area
|
3799 |
|
|
wsp 001400 -- sp=1400
|
3800 |
|
|
stapc 012300 -- start @ 12300
|
3801 |
|
|
wtgo
|
3802 |
|
|
rpc d=012322 -- ! pc
|
3803 |
|
|
rr3 d=000000 -- ! r3=0
|
3804 |
|
|
rr4 d=036162 -- ! r4=36162
|
3805 |
|
|
rr5 d=037162 -- ! r5=37162
|
3806 |
|
|
wal 037000 --
|
3807 |
|
|
brm 57
|
3808 |
|
|
d=000007 --! 0, 4, 0, 7, 0, 4# 4/ 0 -> 0111 0 4
|
3809 |
|
|
d=000000 --!
|
3810 |
|
|
d=000004 --!
|
3811 |
|
|
d=000000 --! 0, 4, 2, 0, 2, 0# 4/ 2 -> 0000 2 0
|
3812 |
|
|
d=000002 --!
|
3813 |
|
|
d=000000 --!
|
3814 |
|
|
d=000000 --! 0, 6, 2, 0, 3, 0# 6/ 2 -> 0000 3 0
|
3815 |
|
|
d=000003 --!
|
3816 |
|
|
d=000000 --!
|
3817 |
|
|
d=000010 --! 0, 4, -2, 10, -2, 0# 4/-2 ->1000 -2 0
|
3818 |
|
|
d=177776 --!
|
3819 |
|
|
d=000000 --!
|
3820 |
|
|
#37030
|
3821 |
|
|
d=000002 --! 2, 0, 1, 2, 2, 0# 0x20000 / 1
|
3822 |
|
|
d=000002 --!
|
3823 |
|
|
d=000000 --!
|
3824 |
|
|
d=000012 --! 2, 0, -2, 12, 2, 0# 0x20000 / -2
|
3825 |
|
|
d=000002 --!
|
3826 |
|
|
d=000000 --!
|
3827 |
|
|
d=000012 --!100000, 0, 1, 12,100000, 0# 0x80000000 / 1
|
3828 |
|
|
d=100000 --!
|
3829 |
|
|
d=000000 --!
|
3830 |
|
|
d=000002 --!177776,177777, -1, 2,177776,177777# -0x10001 / -1
|
3831 |
|
|
d=177776 --!
|
3832 |
|
|
d=177777 --!
|
3833 |
|
|
#37060
|
3834 |
|
|
d=000010 --!177777,177773, 2, 10, -2, -1# -5 / 2
|
3835 |
|
|
d=177776 --!
|
3836 |
|
|
d=177777 --!
|
3837 |
|
|
d=000000 --!177777,177773, -2, 0, 2, -1# -5 / -2
|
3838 |
|
|
d=000002 --!
|
3839 |
|
|
d=177777 --!
|
3840 |
|
|
d=000010 --!177776, 0, 40000, 10, -10, 0# -0x20000/0x4000
|
3841 |
|
|
d=177770 --!
|
3842 |
|
|
d=000000 --!
|
3843 |
|
|
d=000012 --! 100, 200,177601, 12, 100, 200# 0x400080 / -0x7f
|
3844 |
|
|
d=000100 --!
|
3845 |
|
|
d=000200 --!
|
3846 |
|
|
#37110
|
3847 |
|
|
d=000007 --! 0, 1, 0, 7, 0, 1 # zero divide
|
3848 |
|
|
d=000000 --!
|
3849 |
|
|
d=000001 --!
|
3850 |
|
|
d=000007 --! -1, -1, 0, 7, -1, -1 # zero divide
|
3851 |
|
|
d=177777 --!
|
3852 |
|
|
d=177777 --!
|
3853 |
|
|
d=000007 --! 0, 0, 0, 7, 0, 0 # zero divide
|
3854 |
|
|
d=000000 --!
|
3855 |
|
|
d=000000 --!
|
3856 |
|
|
d=000002 --! 1, 1, 1, 2, 1, 1 # overflow
|
3857 |
|
|
d=000001 --!
|
3858 |
|
|
d=000001 --!
|
3859 |
|
|
#13740
|
3860 |
|
|
d=000012 --! 1, 1, -1, 012, 1, 1 # overflow
|
3861 |
|
|
d=000001 --!
|
3862 |
|
|
d=000001 --!
|
3863 |
|
|
d=000010 --! -1, -1, 1, 010, -1, 0 # wfjm corrected, not overflow
|
3864 |
|
|
d=177777 --!
|
3865 |
|
|
d=000000 --!
|
3866 |
|
|
d=000000 --! -1, -1, -1, 0, 1, 0 # wfjm corrected, not overflow
|
3867 |
|
|
d=000001 --!
|
3868 |
|
|
d=000000 --!
|
3869 |
|
|
#--------
|
3870 |
|
|
C Exec test 37.2: data adapted from KDJ11.MAC, test 213, p. 139-141
|
3871 |
|
|
# D RE RQ FU DAT
|
3872 |
|
|
wal 036000 -- setup test vector:
|
3873 |
|
|
bwm 51
|
3874 |
|
|
177777 -- 177777,177777,177777, 0, 1, 0#
|
3875 |
|
|
177777 --
|
3876 |
|
|
177777 --
|
3877 |
|
|
000000 -- 0,177777,177777,12, 0,177777#
|
3878 |
|
|
177777 --
|
3879 |
|
|
177777 --
|
3880 |
|
|
177777 -- 177777, 0,177777, 2,177777, 0#
|
3881 |
|
|
000000 --
|
3882 |
|
|
177777 --
|
3883 |
|
|
000000 -- 0, 7642, 7643, 4, 0, 7642#
|
3884 |
|
|
007642 --
|
3885 |
|
|
007643 --
|
3886 |
|
|
000000 -- 0, 137,177543, 4, 0, 137#
|
3887 |
|
|
000137 --
|
3888 |
|
|
177543 --
|
3889 |
|
|
000000 -- 0, 7643, 7643, 0, 1, 0#
|
3890 |
|
|
007643 --
|
3891 |
|
|
007643 --
|
3892 |
|
|
100000 -- 100000, 4376, 10021,12,100000, 4376#
|
3893 |
|
|
004376 --
|
3894 |
|
|
010021 --
|
3895 |
|
|
177700 -- 177700,170033, 10021,10,176024,171307#
|
3896 |
|
|
170033 --
|
3897 |
|
|
010021 --
|
3898 |
|
|
177700 -- 177700,170033,167757, 0, 1754,171307#
|
3899 |
|
|
170033 --
|
3900 |
|
|
167757 --
|
3901 |
|
|
000000 -- 0,177777, 1, 2, 0,177777#
|
3902 |
|
|
177777 --
|
3903 |
|
|
000001 --
|
3904 |
|
|
177777 -- 177777, 45716, 1,12,177777, 45716#
|
3905 |
|
|
045716 --
|
3906 |
|
|
000001 --
|
3907 |
|
|
000000 -- 0, 2,177770, 4, 0, 2#
|
3908 |
|
|
000002 --
|
3909 |
|
|
177770 --
|
3910 |
|
|
177777 -- 177777,177776, 10, 4, 0,177776#
|
3911 |
|
|
177776 --
|
3912 |
|
|
000010 --
|
3913 |
|
|
000001 -- 1,177777, 1, 2, 1,177777#
|
3914 |
|
|
177777 --
|
3915 |
|
|
000001 --
|
3916 |
|
|
000001 -- 1, 0, 2, 2, 1, 0#
|
3917 |
|
|
000000 --
|
3918 |
|
|
000002 --
|
3919 |
|
|
000001 -- 1, 0, 3, 0, 52525, 1#
|
3920 |
|
|
000000 --
|
3921 |
|
|
000003 --
|
3922 |
|
|
000023 -- 23, 16054, 16537, 0, 246, 10222#
|
3923 |
|
|
016054 --
|
3924 |
|
|
016537 --
|
3925 |
|
|
#----
|
3926 |
|
|
wr2 177776 -- r2=177776 -> psw
|
3927 |
|
|
wr3 000021 -- r3=21 (17.) -> test count
|
3928 |
|
|
wr4 036000 -- r4=36000 -> input area
|
3929 |
|
|
wr5 037000 -- r5=37000 -> output area
|
3930 |
|
|
wsp 001400 -- sp=1400
|
3931 |
|
|
stapc 012300 -- start @ 12300
|
3932 |
|
|
wtgo
|
3933 |
|
|
rpc d=012322 -- ! pc
|
3934 |
|
|
rr3 d=000000 -- ! r3=0
|
3935 |
|
|
rr4 d=036146 -- ! r4=36146
|
3936 |
|
|
rr5 d=037146 -- ! r5=37146
|
3937 |
|
|
wal 037000 --
|
3938 |
|
|
brm 51
|
3939 |
|
|
d=000000 --!177777,177777,177777, 0, 1, 0#
|
3940 |
|
|
d=000001 --!
|
3941 |
|
|
d=000000 --!
|
3942 |
|
|
d=000012 --! 0,177777,177777,12, 0,177777#
|
3943 |
|
|
d=000000 --!
|
3944 |
|
|
d=177777 --!
|
3945 |
|
|
d=000002 --!177777, 0,177777, 2,177777, 0#
|
3946 |
|
|
d=177777 --!
|
3947 |
|
|
d=000000 --!
|
3948 |
|
|
d=000004 --! 0, 7642, 7643, 4, 0, 7642#
|
3949 |
|
|
d=000000 --!
|
3950 |
|
|
d=007642 --!
|
3951 |
|
|
d=000004 --! 0, 137,177543, 4, 0, 137#
|
3952 |
|
|
d=000000 --!
|
3953 |
|
|
d=000137 --!
|
3954 |
|
|
d=000000 --! 0, 7643, 7643, 0, 1, 0#
|
3955 |
|
|
d=000001 --!
|
3956 |
|
|
d=000000 --!
|
3957 |
|
|
d=000012 --!100000, 4376, 10021,12,100000, 4376#
|
3958 |
|
|
d=100000 --!
|
3959 |
|
|
d=004376 --!
|
3960 |
|
|
d=000010 --!177700,170033, 10021,10,176024,171307#
|
3961 |
|
|
d=176024 --!
|
3962 |
|
|
d=171307 --!
|
3963 |
|
|
d=000000 --!177700,170033,167757, 0, 1754,171307#
|
3964 |
|
|
d=001754 --!
|
3965 |
|
|
d=171307 --!
|
3966 |
|
|
d=000002 --! 0,177777, 1, 2, 0,177777#
|
3967 |
|
|
d=000000 --!
|
3968 |
|
|
d=177777 --!
|
3969 |
|
|
d=000012 --!177777, 45716, 1,12,177777, 45716#
|
3970 |
|
|
d=177777 --!
|
3971 |
|
|
d=045716 --!
|
3972 |
|
|
d=000004 --! 0, 2,177770, 4, 0, 2#
|
3973 |
|
|
d=000000 --!
|
3974 |
|
|
d=000002 --!
|
3975 |
|
|
d=000004 --!177777,177776, 10, 4, 0,177776#
|
3976 |
|
|
d=000000 --!
|
3977 |
|
|
d=177776 --!
|
3978 |
|
|
d=000002 --! 1,177777, 1, 2, 1,177777#
|
3979 |
|
|
d=000001 --!
|
3980 |
|
|
d=177777 --!
|
3981 |
|
|
d=000002 --! 1, 0, 2, 2, 1, 0#
|
3982 |
|
|
d=000001 --!
|
3983 |
|
|
d=000000 --!
|
3984 |
|
|
d=000000 --! 1, 0, 3, 0, 52525, 1#
|
3985 |
|
|
d=052525 --!
|
3986 |
|
|
d=000001 --!
|
3987 |
|
|
d=000000 --! 23, 16054, 16537, 0, 246, 10222#
|
3988 |
|
|
d=000246 --!
|
3989 |
|
|
d=010222 --!
|
3990 |
|
|
#-----------------------------------------------------------------------------
|
3991 |
|
|
C Setup code 40 [base 12400] (systematic ASH test)
|
3992 |
|
|
#
|
3993 |
|
|
wal 012400 -- code:
|
3994 |
|
|
bwm 15
|
3995 |
|
|
000230 -- spl 0
|
3996 |
|
|
016400 -- L1: mov 2(r4),r0
|
3997 |
|
|
000002
|
3998 |
|
|
011412 -- mov (r4),(r2)
|
3999 |
|
|
072064 -- ash 4(r4),r0
|
4000 |
|
|
000004
|
4001 |
|
|
011265 -- mov (r2),2(r5)
|
4002 |
|
|
000002
|
4003 |
|
|
#12420
|
4004 |
|
|
010015 -- mov r0,(r5)
|
4005 |
|
|
062704 -- add #6,r4
|
4006 |
|
|
000006
|
4007 |
|
|
062705 -- add #4,r5
|
4008 |
|
|
000004
|
4009 |
|
|
077315 -- sob r3,L1
|
4010 |
|
|
000000 -- halt
|
4011 |
|
|
#
|
4012 |
|
|
C Exec code 40 (systematic ASH test)
|
4013 |
|
|
C Exec test 40.1: data adapted from ash.s11 code of Begemot p11-2.10c
|
4014 |
|
|
#
|
4015 |
|
|
# The {} comments are original comments from Harti Brandt
|
4016 |
|
|
# Annotations starting with !! indicated mods for W11
|
4017 |
|
|
# Note, that the W11 does not have the microcode bugs of the J11 !
|
4018 |
|
|
#
|
4019 |
|
|
wal 036000 -- setup test vector:
|
4020 |
|
|
# test shift amount 0
|
4021 |
|
|
bwm 150
|
4022 |
|
|
000000 -- 00, 000000, 000000, 000000, 04
|
4023 |
|
|
000000 --
|
4024 |
|
|
000000 --
|
4025 |
|
|
000017 -- 17, 000000, 000000, 000000, 04
|
4026 |
|
|
000000 --
|
4027 |
|
|
000000 --
|
4028 |
|
|
000017 -- 17, 100001, 000000, 100001, 10
|
4029 |
|
|
100001 --
|
4030 |
|
|
000000 --
|
4031 |
|
|
000017 -- 17, 040001, 000000, 040001, 00
|
4032 |
|
|
040001 --
|
4033 |
|
|
000000 --
|
4034 |
|
|
000017 -- 17, 040001, 177700, 040001, 00
|
4035 |
|
|
040001 --
|
4036 |
|
|
177700 --
|
4037 |
|
|
# right shift positive values
|
4038 |
|
|
000000 -- 00, 000000, 000077, 000000, 04
|
4039 |
|
|
000000 --
|
4040 |
|
|
000077 --
|
4041 |
|
|
000017 -- 17, 000000, 000077, 000000, 04
|
4042 |
|
|
000000 --
|
4043 |
|
|
000077 --
|
4044 |
|
|
000000 -- 00, 000002, 000077, 000001, 00
|
4045 |
|
|
000002 --
|
4046 |
|
|
000077 --
|
4047 |
|
|
000000 -- 00, 000001, 000077, 000000, 05
|
4048 |
|
|
000001 --
|
4049 |
|
|
000077 --
|
4050 |
|
|
000000 -- 00, 000003, 000076, 000000, 05
|
4051 |
|
|
000003 --
|
4052 |
|
|
000076 --
|
4053 |
|
|
000000 -- 00, 000001, 000076, 000000, 04
|
4054 |
|
|
000001 --
|
4055 |
|
|
000076 --
|
4056 |
|
|
000000 -- 00, 040000, 000062, 000001, 00
|
4057 |
|
|
040000 --
|
4058 |
|
|
000062 --
|
4059 |
|
|
000000 -- 00, 040000, 000061, 000000, 05
|
4060 |
|
|
040000 --
|
4061 |
|
|
000061 --
|
4062 |
|
|
000000 -- 00, 040000, 000060, 000000, 04
|
4063 |
|
|
040000 --
|
4064 |
|
|
000060 --
|
4065 |
|
|
000000 -- 00, 040000, 000042, 000000, 04
|
4066 |
|
|
040000 --
|
4067 |
|
|
000042 --
|
4068 |
|
|
000000 -- 00, 040000, 000041, 000000, 04
|
4069 |
|
|
040000 --
|
4070 |
|
|
000041 --
|
4071 |
|
|
000000 -- 00, 040000, 000040, 000000, 04
|
4072 |
|
|
040000 --
|
4073 |
|
|
000040 --
|
4074 |
|
|
000000 -- 00, 040000, 100037, 000000, 04
|
4075 |
|
|
040000 --
|
4076 |
|
|
100037 --
|
4077 |
|
|
# right shift negative numbers
|
4078 |
|
|
000000 -- 00, 100002, 000077, 140001, 10
|
4079 |
|
|
100002 --
|
4080 |
|
|
000077 --
|
4081 |
|
|
000000 -- 00, 100002, 000076, 160000, 11
|
4082 |
|
|
100002 --
|
4083 |
|
|
000076 --
|
4084 |
|
|
000000 -- 00, 100002, 000075, 170000, 10
|
4085 |
|
|
100002 --
|
4086 |
|
|
000075 --
|
4087 |
|
|
000000 -- 00, 100002, 000062, 177776, 10
|
4088 |
|
|
100002 --
|
4089 |
|
|
000062 --
|
4090 |
|
|
000000 -- 00, 100002, 000061, 177777, 10
|
4091 |
|
|
100002 --
|
4092 |
|
|
000061 --
|
4093 |
|
|
000000 -- 00, 100002, 000060, 177777, 11
|
4094 |
|
|
100002 --
|
4095 |
|
|
000060 --
|
4096 |
|
|
000000 -- 00, 100002, 000057, 177777, 11
|
4097 |
|
|
100002 --
|
4098 |
|
|
000057 --
|
4099 |
|
|
000000 -- 00, 100002, 000056, 177777, 11
|
4100 |
|
|
100002 --
|
4101 |
|
|
000056 --
|
4102 |
|
|
000000 -- 00, 100002, 000041, 177777, 11
|
4103 |
|
|
100002 --
|
4104 |
|
|
000041 --
|
4105 |
|
|
000000 -- 00, 100002, 000040, 177777, 11
|
4106 |
|
|
100002 --
|
4107 |
|
|
000040 --
|
4108 |
|
|
000000 -- 00, 100002, 040037, 177777, 11
|
4109 |
|
|
100002 --
|
4110 |
|
|
040037 --
|
4111 |
|
|
# left shift positive numbers
|
4112 |
|
|
000000 -- 00, 000000, 000001, 000000, 04
|
4113 |
|
|
000000 --
|
4114 |
|
|
000001 --
|
4115 |
|
|
000017 -- 17, 000000, 000001, 000000, 04
|
4116 |
|
|
000000 --
|
4117 |
|
|
000001 --
|
4118 |
|
|
000000 -- 00, 000001, 000007, 000200, 00
|
4119 |
|
|
000001 --
|
4120 |
|
|
000007 --
|
4121 |
|
|
000000 -- 00, 000001, 000016, 040000, 00
|
4122 |
|
|
000001 --
|
4123 |
|
|
000016 --
|
4124 |
|
|
000000 -- 00, 000001, 000017, 100000, 12
|
4125 |
|
|
000001 --
|
4126 |
|
|
000017 --
|
4127 |
|
|
000000 -- 00, 000001, 000020, 000000, 07
|
4128 |
|
|
000001 --
|
4129 |
|
|
000020 --
|
4130 |
|
|
000000 -- 00, 000001, 000021, 000000, 06
|
4131 |
|
|
000001 --
|
4132 |
|
|
000021 --
|
4133 |
|
|
000000 -- 00, 000001, 000036, 000000, 06
|
4134 |
|
|
000001 --
|
4135 |
|
|
000036 --
|
4136 |
|
|
000000 -- 00, 000001, 000037, 000000, 04 {????}
|
4137 |
|
|
000001 --
|
4138 |
|
|
000037 --
|
4139 |
|
|
000000 -- 00, 000001, 000040, 000000, 04 {right shift!}
|
4140 |
|
|
000001 --
|
4141 |
|
|
000040 --
|
4142 |
|
|
000000 -- 00, 000001, 010037, 000000, 04 {right shift!}
|
4143 |
|
|
000001 --
|
4144 |
|
|
010037 --
|
4145 |
|
|
# left shift negative numbers
|
4146 |
|
|
000000 -- 00, 100001, 000001, 000002, 03
|
4147 |
|
|
100001 --
|
4148 |
|
|
000001 --
|
4149 |
|
|
000000 -- 00, 140001, 000001, 100002, 11
|
4150 |
|
|
140001 --
|
4151 |
|
|
000001 --
|
4152 |
|
|
000000 -- 00, 140001, 000002, 000004, 03
|
4153 |
|
|
140001 --
|
4154 |
|
|
000002 --
|
4155 |
|
|
000000 -- 00, 140001, 000016, 040000, 02
|
4156 |
|
|
140001 --
|
4157 |
|
|
000016 --
|
4158 |
|
|
000000 -- 00, 140001, 000017, 100000, 12
|
4159 |
|
|
140001 --
|
4160 |
|
|
000017 --
|
4161 |
|
|
000000 -- 00, 140001, 000020, 000000, 07
|
4162 |
|
|
140001 --
|
4163 |
|
|
000020 --
|
4164 |
|
|
000000 -- 00, 140001, 000021, 000000, 06
|
4165 |
|
|
140001 --
|
4166 |
|
|
000021 --
|
4167 |
|
|
000000 -- 00, 140002, 000035, 000000, 06
|
4168 |
|
|
140002 --
|
4169 |
|
|
000035 --
|
4170 |
|
|
000000 -- 00, 140002, 000036, 000000, 06
|
4171 |
|
|
140002 --
|
4172 |
|
|
000036 --
|
4173 |
|
|
000000 -- 00, 140002, 000037, 177777, 11 {????}
|
4174 |
|
|
140002 --
|
4175 |
|
|
000037 --
|
4176 |
|
|
#----
|
4177 |
|
|
wr2 177776 -- r2=177776 -> psw
|
4178 |
|
|
wr3 000062 -- r3=62 -> test count
|
4179 |
|
|
wr4 036000 -- r4=36000 -> input area
|
4180 |
|
|
wr5 037000 -- r5=37000 -> output area
|
4181 |
|
|
wsp 001400 -- sp=1400
|
4182 |
|
|
stapc 012400 -- start @ 12400
|
4183 |
|
|
wtgo
|
4184 |
|
|
rpc d=012436 -- ! pc
|
4185 |
|
|
rr3 d=000000 -- ! r3=0
|
4186 |
|
|
rr4 d=036454 -- ! r4=36454
|
4187 |
|
|
rr5 d=037310 -- ! r5=37310
|
4188 |
|
|
wal 037000 --
|
4189 |
|
|
# test shift amount 0
|
4190 |
|
|
brm 100
|
4191 |
|
|
d=000000 -- 00, 000000, 000000, 000000, 04
|
4192 |
|
|
d=000004 --
|
4193 |
|
|
d=000000 -- 17, 000000, 000000, 000000, 04
|
4194 |
|
|
d=000004 --
|
4195 |
|
|
d=100001 -- 17, 100001, 000000, 100001, 10
|
4196 |
|
|
d=000010 --
|
4197 |
|
|
d=040001 -- 17, 040001, 000000, 040001, 00
|
4198 |
|
|
d=000000 --
|
4199 |
|
|
d=040001 -- 17, 040001, 177700, 040001, 00
|
4200 |
|
|
d=000000 --
|
4201 |
|
|
#37024 # right shift positive values
|
4202 |
|
|
d=000000 -- 00, 000000, 000077, 000000, 04
|
4203 |
|
|
d=000004 --
|
4204 |
|
|
d=000000 -- 17, 000000, 000077, 000000, 04
|
4205 |
|
|
d=000004 --
|
4206 |
|
|
d=000001 -- 00, 000002, 000077, 000001, 00
|
4207 |
|
|
d=000000 --
|
4208 |
|
|
#37040
|
4209 |
|
|
d=000000 -- 00, 000001, 000077, 000000, 05
|
4210 |
|
|
d=000005 --
|
4211 |
|
|
d=000000 -- 00, 000003, 000076, 000000, 05
|
4212 |
|
|
d=000005 --
|
4213 |
|
|
d=000000 -- 00, 000001, 000076, 000000, 04
|
4214 |
|
|
d=000004 --
|
4215 |
|
|
d=000001 -- 00, 040000, 000062, 000001, 00
|
4216 |
|
|
d=000000 --
|
4217 |
|
|
#37060
|
4218 |
|
|
d=000000 -- 00, 040000, 000061, 000000, 05
|
4219 |
|
|
d=000005 --
|
4220 |
|
|
d=000000 -- 00, 040000, 000060, 000000, 04
|
4221 |
|
|
d=000004 --
|
4222 |
|
|
d=000000 -- 00, 040000, 000042, 000000, 04
|
4223 |
|
|
d=000004 --
|
4224 |
|
|
d=000000 -- 00, 040000, 000041, 000000, 04
|
4225 |
|
|
d=000004 --
|
4226 |
|
|
#37100
|
4227 |
|
|
d=000000 -- 00, 040000, 000040, 000000, 04
|
4228 |
|
|
d=000004 --
|
4229 |
|
|
d=000000 -- 00, 040000, 100037, 000000, 04
|
4230 |
|
|
d=000006 -- !!04->06
|
4231 |
|
|
#37110 # right shift negative numbers
|
4232 |
|
|
d=140001 -- 00, 100002, 000077, 140001, 10
|
4233 |
|
|
d=000010 --
|
4234 |
|
|
d=160000 -- 00, 100002, 000076, 160000, 11
|
4235 |
|
|
d=000011 --
|
4236 |
|
|
#37120
|
4237 |
|
|
d=170000 -- 00, 100002, 000075, 170000, 10
|
4238 |
|
|
d=000010 --
|
4239 |
|
|
d=177776 -- 00, 100002, 000062, 177776, 10
|
4240 |
|
|
d=000010 --
|
4241 |
|
|
d=177777 -- 00, 100002, 000061, 177777, 10
|
4242 |
|
|
d=000010 --
|
4243 |
|
|
d=177777 -- 00, 100002, 000060, 177777, 11
|
4244 |
|
|
d=000011 --
|
4245 |
|
|
#37140
|
4246 |
|
|
d=177777 -- 00, 100002, 000057, 177777, 11
|
4247 |
|
|
d=000011 --
|
4248 |
|
|
d=177777 -- 00, 100002, 000056, 177777, 11
|
4249 |
|
|
d=000011 --
|
4250 |
|
|
d=177777 -- 00, 100002, 000041, 177777, 11
|
4251 |
|
|
d=000011 --
|
4252 |
|
|
d=177777 -- 00, 100002, 000040, 177777, 11
|
4253 |
|
|
d=000011 -- see Note below [[s:10]]
|
4254 |
|
|
d=000000 -- 00, 100002, 040037, 177777, 11 !!-1->0
|
4255 |
|
|
d=000006 -- !!11->06
|
4256 |
|
|
#37164 # left shift positive numbers
|
4257 |
|
|
d=000000 -- 00, 000000, 000001, 000000, 04
|
4258 |
|
|
d=000004 --
|
4259 |
|
|
d=000000 -- 17, 000000, 000001, 000000, 04
|
4260 |
|
|
d=000004 --
|
4261 |
|
|
d=000200 -- 00, 000001, 000007, 000200, 00
|
4262 |
|
|
d=000000 --
|
4263 |
|
|
#37200
|
4264 |
|
|
d=040000 -- 00, 000001, 000016, 040000, 00
|
4265 |
|
|
d=000000 --
|
4266 |
|
|
d=100000 -- 00, 000001, 000017, 100000, 12
|
4267 |
|
|
d=000012 --
|
4268 |
|
|
d=000000 -- 00, 000001, 000020, 000000, 07
|
4269 |
|
|
d=000007 --
|
4270 |
|
|
d=000000 -- 00, 000001, 000021, 000000, 06
|
4271 |
|
|
d=000006 --
|
4272 |
|
|
#37220
|
4273 |
|
|
d=000000 -- 00, 000001, 000036, 000000, 06
|
4274 |
|
|
d=000006 --
|
4275 |
|
|
d=000000 -- 00, 000001, 000037, 000000, 04 {????}
|
4276 |
|
|
d=000006 -- !!04->06
|
4277 |
|
|
d=000000 -- 00, 000001, 000040, 000000, 04 {right shift!}
|
4278 |
|
|
d=000004 --
|
4279 |
|
|
d=000000 -- 00, 000001, 010037, 000000, 04 {right shift!}
|
4280 |
|
|
d=000006 -- !!04->06
|
4281 |
|
|
#37240 # left shift negative numbers
|
4282 |
|
|
d=000002 -- 00, 100001, 000001, 000002, 03
|
4283 |
|
|
d=000003 --
|
4284 |
|
|
d=100002 -- 00, 140001, 000001, 100002, 11
|
4285 |
|
|
d=000011 --
|
4286 |
|
|
d=000004 -- 00, 140001, 000002, 000004, 03
|
4287 |
|
|
d=000003 --
|
4288 |
|
|
d=040000 -- 00, 140001, 000016, 040000, 02
|
4289 |
|
|
d=000002 --
|
4290 |
|
|
#37260
|
4291 |
|
|
d=100000 -- 00, 140001, 000017, 100000, 12
|
4292 |
|
|
d=000012 --
|
4293 |
|
|
d=000000 -- 00, 140001, 000020, 000000, 07
|
4294 |
|
|
d=000007 --
|
4295 |
|
|
d=000000 -- 00, 140001, 000021, 000000, 06
|
4296 |
|
|
d=000006 --
|
4297 |
|
|
d=000000 -- 00, 140002, 000035, 000000, 06
|
4298 |
|
|
d=000006 --
|
4299 |
|
|
#37300
|
4300 |
|
|
d=000000 -- 00, 140002, 000036, 000000, 06
|
4301 |
|
|
d=000006 --
|
4302 |
|
|
d=000000 -- 00, 140002, 000037, 177777, 11 {????} !!-1->0
|
4303 |
|
|
d=000006 -- !!11->06
|
4304 |
|
|
#
|
4305 |
|
|
# simh notes:
|
4306 |
|
|
# 1. ash dst=100002,src=040 sets C=0 in simh. PSW is: s:10 b:11 W11:11
|
4307 |
|
|
#
|
4308 |
|
|
#-----------------------------------------------------------------------------
|
4309 |
|
|
C Setup code 41 [base 12500] (systematic ASHC even test)
|
4310 |
|
|
#
|
4311 |
|
|
wal 012500 -- code:
|
4312 |
|
|
bwm 19
|
4313 |
|
|
000230 -- spl 0
|
4314 |
|
|
016400 -- L1: mov 2(r4),r0
|
4315 |
|
|
000002
|
4316 |
|
|
016401 -- mov 4(r4),r1
|
4317 |
|
|
000004
|
4318 |
|
|
011412 -- mov (r4),(r2)
|
4319 |
|
|
073064 -- ashc 6(r4),r0
|
4320 |
|
|
000006
|
4321 |
|
|
#12520
|
4322 |
|
|
011265 -- mov (r2),4(r5)
|
4323 |
|
|
000004
|
4324 |
|
|
010015 -- mov r0,(r5)
|
4325 |
|
|
010165 -- mov r1,2(r5)
|
4326 |
|
|
000002
|
4327 |
|
|
062704 -- add #10,r4
|
4328 |
|
|
000010
|
4329 |
|
|
062705 -- add #6,r5
|
4330 |
|
|
#12540
|
4331 |
|
|
000006
|
4332 |
|
|
077321 -- sob r3,L1
|
4333 |
|
|
000000 -- halt
|
4334 |
|
|
#
|
4335 |
|
|
C Exec code 41 (systematic ASHC even test)
|
4336 |
|
|
C Exec test 41.1: data adapted from ashc.s11 code of Begemot p11-2.10c
|
4337 |
|
|
#
|
4338 |
|
|
# The {} comments are original comments from Harti Brandt
|
4339 |
|
|
# Annotations starting with !! indicated mods for W11
|
4340 |
|
|
# Note, that the W11 does not have the microcode bugs of the J11 !
|
4341 |
|
|
#
|
4342 |
|
|
wal 036000 -- setup test vector:
|
4343 |
|
|
# test when no shift at all, cc must be correctly set
|
4344 |
|
|
bwm 188
|
4345 |
|
|
000000 -- 00, 000000, 000000, 000000, 000000, 000000, 04
|
4346 |
|
|
000000 --
|
4347 |
|
|
000000 --
|
4348 |
|
|
000000 --
|
4349 |
|
|
000017 -- 17, 000000, 000000, 000000, 000000, 000000, 04
|
4350 |
|
|
000000 --
|
4351 |
|
|
000000 --
|
4352 |
|
|
000000 --
|
4353 |
|
|
000017 -- 17, 040000, 000001, 000000, 040000, 000001, 00
|
4354 |
|
|
040000 --
|
4355 |
|
|
000001 --
|
4356 |
|
|
000000 --
|
4357 |
|
|
000017 -- 17, 100000, 000001, 000000, 100000, 000001, 10
|
4358 |
|
|
100000 --
|
4359 |
|
|
000001 --
|
4360 |
|
|
000000 --
|
4361 |
|
|
000017 -- 17, 100000, 000001, 177700, 100000, 000001, 10
|
4362 |
|
|
100000 --
|
4363 |
|
|
000001 --
|
4364 |
|
|
177700 --
|
4365 |
|
|
# right shifts of positive numbers
|
4366 |
|
|
000000 -- 00, 000000, 000000, 000077, 000000, 000000, 04
|
4367 |
|
|
000000 --
|
4368 |
|
|
000000 --
|
4369 |
|
|
000077 --
|
4370 |
|
|
000017 -- 17, 000000, 000000, 000077, 000000, 000000, 04
|
4371 |
|
|
000000 --
|
4372 |
|
|
000000 --
|
4373 |
|
|
000077 --
|
4374 |
|
|
000000 -- 00, 040000, 000000, 000077, 020000, 000000, 00
|
4375 |
|
|
040000 --
|
4376 |
|
|
000000 --
|
4377 |
|
|
000077 --
|
4378 |
|
|
000000 -- 00, 040000, 000000, 177777, 020000, 000000, 00
|
4379 |
|
|
040000 --
|
4380 |
|
|
000000 --
|
4381 |
|
|
000077 --
|
4382 |
|
|
000000 -- 00, 040000, 000000, 000060, 000000, 040000, 00
|
4383 |
|
|
040000 --
|
4384 |
|
|
000000 --
|
4385 |
|
|
000060 --
|
4386 |
|
|
000000 -- 00, 040000, 000000, 000042, 000000, 000001, 00
|
4387 |
|
|
040000 --
|
4388 |
|
|
000000 --
|
4389 |
|
|
000042 --
|
4390 |
|
|
000000 -- 00, 040000, 000000, 000041, 000000, 000000, 05
|
4391 |
|
|
040000 --
|
4392 |
|
|
000000 --
|
4393 |
|
|
000041 --
|
4394 |
|
|
000000 -- 00, 040000, 000000, 000040, 000000, 000000, 04
|
4395 |
|
|
040000 --
|
4396 |
|
|
000000 --
|
4397 |
|
|
000040 --
|
4398 |
|
|
000000 -- 00, 040000, 000000, 177737, 000000, 000000, 04
|
4399 |
|
|
040000 --
|
4400 |
|
|
000000 --
|
4401 |
|
|
177737 --
|
4402 |
|
|
000000 -- 00, 000000, 000001, 177737, 000000, 000000, 04
|
4403 |
|
|
000000 --
|
4404 |
|
|
000001 --
|
4405 |
|
|
177737 --
|
4406 |
|
|
# right shifts of negative numbers
|
4407 |
|
|
000000 -- 00, 100000, 000002, 000077, 140000, 000001, 10
|
4408 |
|
|
100000 --
|
4409 |
|
|
000002 --
|
4410 |
|
|
000077 --
|
4411 |
|
|
000000 -- 00, 100020, 000001, 000077, 140010, 000000, 11
|
4412 |
|
|
100020 --
|
4413 |
|
|
000001 --
|
4414 |
|
|
000077 --
|
4415 |
|
|
000000 -- 00, 177777, 177776, 000077, 177777, 177777, 10
|
4416 |
|
|
177777 --
|
4417 |
|
|
177776 --
|
4418 |
|
|
000077 --
|
4419 |
|
|
000000 -- 00, 177777, 177777, 000077, 177777, 177777, 11
|
4420 |
|
|
177777 --
|
4421 |
|
|
177777 --
|
4422 |
|
|
000077 --
|
4423 |
|
|
000000 -- 00, 100000, 100000, 000060, 177777, 100000, 11
|
4424 |
|
|
100000 --
|
4425 |
|
|
100000 --
|
4426 |
|
|
000060 --
|
4427 |
|
|
000000 -- 00, 100000, 000000, 000060, 177777, 100000, 10
|
4428 |
|
|
100000 --
|
4429 |
|
|
000000 --
|
4430 |
|
|
000060 --
|
4431 |
|
|
000000 -- 00, 100000, 000001, 000042, 177777, 177776, 10
|
4432 |
|
|
100000 --
|
4433 |
|
|
000001 --
|
4434 |
|
|
000042 --
|
4435 |
|
|
000000 -- 00, 100000, 000001, 000041, 177777, 177777, 10
|
4436 |
|
|
100000 --
|
4437 |
|
|
000001 --
|
4438 |
|
|
000041 --
|
4439 |
|
|
000000 -- 00, 100000, 000001, 000040, 177777, 177777, 11
|
4440 |
|
|
100000 --
|
4441 |
|
|
000001 --
|
4442 |
|
|
000040 --
|
4443 |
|
|
000000 -- 00, 100000, 000001, 177737, 177777, 177777, 11
|
4444 |
|
|
100000 --
|
4445 |
|
|
000001 --
|
4446 |
|
|
177737 --
|
4447 |
|
|
# left shifts of positive numbers
|
4448 |
|
|
000000 -- 00, 000000, 000000, 000001, 000000, 000000, 04
|
4449 |
|
|
000000 --
|
4450 |
|
|
000000 --
|
4451 |
|
|
000001 --
|
4452 |
|
|
000017 -- 17, 000000, 000000, 000001, 000000, 000000, 04
|
4453 |
|
|
000000 --
|
4454 |
|
|
000000 --
|
4455 |
|
|
000001 --
|
4456 |
|
|
000000 -- 00, 000002, 000001, 000001, 000004, 000002, 00
|
4457 |
|
|
000002 --
|
4458 |
|
|
000001 --
|
4459 |
|
|
000001 --
|
4460 |
|
|
000000 -- 00, 000002, 100000, 000001, 000005, 000000, 00
|
4461 |
|
|
000002 --
|
4462 |
|
|
100000 --
|
4463 |
|
|
000001 --
|
4464 |
|
|
000000 -- 00, 040000, 000000, 000001, 100000, 000000, 12
|
4465 |
|
|
040000 --
|
4466 |
|
|
000000 --
|
4467 |
|
|
000001 --
|
4468 |
|
|
000000 -- 00, 040000, 000000, 000002, 000000, 000000, 07
|
4469 |
|
|
040000 --
|
4470 |
|
|
000000 --
|
4471 |
|
|
000002 --
|
4472 |
|
|
000000 -- 00, 040000, 000000, 000003, 000000, 000000, 06
|
4473 |
|
|
040000 --
|
4474 |
|
|
000000 --
|
4475 |
|
|
000003 --
|
4476 |
|
|
000000 -- 00, 000000, 000001, 177701, 000000, 000002, 00
|
4477 |
|
|
000000 --
|
4478 |
|
|
000001 --
|
4479 |
|
|
177701 --
|
4480 |
|
|
000000 -- 00, 000000, 000001, 177735, 020000, 000000, 00
|
4481 |
|
|
000000 --
|
4482 |
|
|
000001 --
|
4483 |
|
|
177735 --
|
4484 |
|
|
000000 -- 00, 000000, 000001, 177736, 040000, 000000, 00
|
4485 |
|
|
000000 --
|
4486 |
|
|
000001 --
|
4487 |
|
|
177736 --
|
4488 |
|
|
000000 -- 00, 000000, 000001, 000037, 100000, 000000, 12 {left shift!}
|
4489 |
|
|
000000 --
|
4490 |
|
|
000001 --
|
4491 |
|
|
000037 --
|
4492 |
|
|
000000 -- 00, 000000, 000001, 177737, 000000, 000000, 04 {right shift!}
|
4493 |
|
|
000000 --
|
4494 |
|
|
000001 --
|
4495 |
|
|
177737 --
|
4496 |
|
|
000000 -- 00, 000000, 000001, 020037, 000000, 000000, 04 {right shift!}
|
4497 |
|
|
000000 --
|
4498 |
|
|
000001 --
|
4499 |
|
|
020037 --
|
4500 |
|
|
# left shifts of negative numbers
|
4501 |
|
|
000000 -- 00, 177777, 177777, 000001, 177777, 177776, 11
|
4502 |
|
|
177777 --
|
4503 |
|
|
177777 --
|
4504 |
|
|
000001 --
|
4505 |
|
|
000000 -- 00, 177777, 177777, 000002, 177777, 177774, 11
|
4506 |
|
|
177777 --
|
4507 |
|
|
177777 --
|
4508 |
|
|
000002 --
|
4509 |
|
|
000000 -- 00, 177777, 177777, 000036, 140000, 000000, 11
|
4510 |
|
|
177777 --
|
4511 |
|
|
177777 --
|
4512 |
|
|
000036 --
|
4513 |
|
|
000000 -- 00, 177777, 177777, 000037, 100000, 000000, 11
|
4514 |
|
|
177777 --
|
4515 |
|
|
177777 --
|
4516 |
|
|
000037 --
|
4517 |
|
|
000000 -- 00, 177777, 177776, 000037, 000000, 000000, 07
|
4518 |
|
|
177777 --
|
4519 |
|
|
177776 --
|
4520 |
|
|
000037 --
|
4521 |
|
|
000000 -- 00, 177777, 177774, 000037, 000000, 000000, 06
|
4522 |
|
|
177777 --
|
4523 |
|
|
177774 --
|
4524 |
|
|
000037 --
|
4525 |
|
|
000000 -- 00, 177777, 177777, 177701, 177777, 177776, 11
|
4526 |
|
|
177777 --
|
4527 |
|
|
177777 --
|
4528 |
|
|
177701 --
|
4529 |
|
|
000000 -- 00, 177777, 177777, 001037, 177777, 177777, 11 {right shift!}
|
4530 |
|
|
177777 --
|
4531 |
|
|
177777 --
|
4532 |
|
|
001037 --
|
4533 |
|
|
000000 -- 00, 177777, 177777, 001036, 140000, 000000, 11
|
4534 |
|
|
177777 --
|
4535 |
|
|
177777 --
|
4536 |
|
|
001036 --
|
4537 |
|
|
#----
|
4538 |
|
|
wr2 177776 -- r2=177776
|
4539 |
|
|
wr3 000057 -- r3=57 (47.)
|
4540 |
|
|
wr4 036000 -- r4=36000
|
4541 |
|
|
wr5 037000 -- r5=37000
|
4542 |
|
|
wsp 001400 -- sp=1400
|
4543 |
|
|
stapc 012500 -- start @ 12500
|
4544 |
|
|
wtgo
|
4545 |
|
|
rpc d=012546 -- ! pc
|
4546 |
|
|
rr3 d=000000 -- ! r3=0
|
4547 |
|
|
rr4 d=036570 -- ! r4=36570
|
4548 |
|
|
rr5 d=037432 -- ! r5=37432
|
4549 |
|
|
wal 037000 --
|
4550 |
|
|
# test when no shift at all, cc must be correctly set
|
4551 |
|
|
brm 141
|
4552 |
|
|
d=000000 --!00, 000000, 000000, 000000, 000000, 000000, 04
|
4553 |
|
|
d=000000 --!
|
4554 |
|
|
d=000004 --!
|
4555 |
|
|
d=000000 --!17, 000000, 000000, 000000, 000000, 000000, 04
|
4556 |
|
|
d=000000 --!
|
4557 |
|
|
d=000004 --!
|
4558 |
|
|
d=040000 --!17, 040000, 000001, 000000, 040000, 000001, 00
|
4559 |
|
|
d=000001 --!
|
4560 |
|
|
d=000000 --!
|
4561 |
|
|
d=100000 --!17, 100000, 000001, 000000, 100000, 000001, 10
|
4562 |
|
|
d=000001 --!
|
4563 |
|
|
d=000010 --!
|
4564 |
|
|
#37030
|
4565 |
|
|
d=100000 --!17, 100000, 000001, 177700, 100000, 000001, 10
|
4566 |
|
|
d=000001 --!
|
4567 |
|
|
d=000010 --!
|
4568 |
|
|
# right shifts of positive numbers
|
4569 |
|
|
d=000000 --!00, 000000, 000000, 000077, 000000, 000000, 04
|
4570 |
|
|
d=000000 --!
|
4571 |
|
|
d=000004 --!
|
4572 |
|
|
d=000000 --!17, 000000, 000000, 000077, 000000, 000000, 04
|
4573 |
|
|
d=000000 --!
|
4574 |
|
|
d=000004 --!
|
4575 |
|
|
d=020000 --!00, 040000, 000000, 000077, 020000, 000000, 00
|
4576 |
|
|
d=000000 --!
|
4577 |
|
|
d=000000 --!
|
4578 |
|
|
#37060
|
4579 |
|
|
d=020000 --!00, 040000, 000000, 177777, 020000, 000000, 00
|
4580 |
|
|
d=000000 --!
|
4581 |
|
|
d=000000 --!
|
4582 |
|
|
d=000000 --!00, 040000, 000000, 000060, 000000, 040000, 00
|
4583 |
|
|
d=040000 --!
|
4584 |
|
|
d=000000 --!
|
4585 |
|
|
d=000000 --!00, 040000, 000000, 000042, 000000, 000001, 00
|
4586 |
|
|
d=000001 --!
|
4587 |
|
|
d=000000 --!
|
4588 |
|
|
d=000000 --!00, 040000, 000000, 000041, 000000, 000000, 05
|
4589 |
|
|
d=000000 --!
|
4590 |
|
|
d=000005 --!
|
4591 |
|
|
#37110
|
4592 |
|
|
d=000000 --!00, 040000, 000000, 000040, 000000, 000000, 04
|
4593 |
|
|
d=000000 --!
|
4594 |
|
|
d=000004 --!
|
4595 |
|
|
d=000000 --!00, 040000, 000000, 177737, 000000, 000000, 04
|
4596 |
|
|
d=000000 --!
|
4597 |
|
|
d=000006 --! !!04->06
|
4598 |
|
|
d=100000 --!00, 000000, 000001, 177737, 000000, 000000, 04!!->100000
|
4599 |
|
|
d=000000 --!
|
4600 |
|
|
d=000012 --! !!04->12
|
4601 |
|
|
# right shifts of negative numbers
|
4602 |
|
|
d=140000 --!00, 100000, 000002, 000077, 140000, 000001, 10
|
4603 |
|
|
d=000001 --!
|
4604 |
|
|
d=000010 --!
|
4605 |
|
|
#37140
|
4606 |
|
|
d=140010 --!00, 100020, 000001, 000077, 140010, 000000, 11
|
4607 |
|
|
d=000000 --!
|
4608 |
|
|
d=000011 --!
|
4609 |
|
|
d=177777 --!00, 177777, 177776, 000077, 177777, 177777, 10
|
4610 |
|
|
d=177777 --!
|
4611 |
|
|
d=000010 --!
|
4612 |
|
|
d=177777 --!00, 177777, 177777, 000077, 177777, 177777, 11
|
4613 |
|
|
d=177777 --!
|
4614 |
|
|
d=000011 --!
|
4615 |
|
|
d=177777 --!00, 100000, 100000, 000060, 177777, 100000, 11
|
4616 |
|
|
d=100000 --!
|
4617 |
|
|
d=000011 --!
|
4618 |
|
|
#37170
|
4619 |
|
|
d=177777 --!00, 100000, 000000, 000060, 177777, 100000, 10
|
4620 |
|
|
d=100000 --!
|
4621 |
|
|
d=000010 --!
|
4622 |
|
|
d=177777 --!00, 100000, 000001, 000042, 177777, 177776, 10
|
4623 |
|
|
d=177776 --!
|
4624 |
|
|
d=000010 --!
|
4625 |
|
|
d=177777 --!00, 100000, 000001, 000041, 177777, 177777, 10
|
4626 |
|
|
d=177777 --!
|
4627 |
|
|
d=000010 --!
|
4628 |
|
|
d=177777 --!00, 100000, 000001, 000040, 177777, 177777, 11
|
4629 |
|
|
d=177777 --!
|
4630 |
|
|
d=000011 --!
|
4631 |
|
|
#37220
|
4632 |
|
|
d=100000 --!00, 100000, 000001, 177737, 177777, 177777, 11!!->100000
|
4633 |
|
|
d=000000 --! !!->000000
|
4634 |
|
|
d=000012 --! !!11->12
|
4635 |
|
|
# left shifts of positive numbers
|
4636 |
|
|
d=000000 --!00, 000000, 000000, 000001, 000000, 000000, 04
|
4637 |
|
|
d=000000 --!
|
4638 |
|
|
d=000004 --!
|
4639 |
|
|
d=000000 --!17, 000000, 000000, 000001, 000000, 000000, 04
|
4640 |
|
|
d=000000 --!
|
4641 |
|
|
d=000004 --!
|
4642 |
|
|
d=000004 --!00, 000002, 000001, 000001, 000004, 000002, 00
|
4643 |
|
|
d=000002 --!
|
4644 |
|
|
d=000000 --!
|
4645 |
|
|
#37250
|
4646 |
|
|
d=000005 --!00, 000002, 100000, 000001, 000005, 000000, 00
|
4647 |
|
|
d=000000 --!
|
4648 |
|
|
d=000000 --!
|
4649 |
|
|
d=100000 --!00, 040000, 000000, 000001, 100000, 000000, 12
|
4650 |
|
|
d=000000 --!
|
4651 |
|
|
d=000012 --!
|
4652 |
|
|
d=000000 --!00, 040000, 000000, 000002, 000000, 000000, 07
|
4653 |
|
|
d=000000 --!
|
4654 |
|
|
d=000007 --!
|
4655 |
|
|
d=000000 --!00, 040000, 000000, 000003, 000000, 000000, 06
|
4656 |
|
|
d=000000 --!
|
4657 |
|
|
d=000006 --!
|
4658 |
|
|
#37300
|
4659 |
|
|
d=000000 --!00, 000000, 000001, 177701, 000000, 000002, 00
|
4660 |
|
|
d=000002 --!
|
4661 |
|
|
d=000000 --!
|
4662 |
|
|
d=020000 --!00, 000000, 000001, 177735, 020000, 000000, 00
|
4663 |
|
|
d=000000 --!
|
4664 |
|
|
d=000000 --!
|
4665 |
|
|
d=040000 --!00, 000000, 000001, 177736, 040000, 000000, 00
|
4666 |
|
|
d=000000 --!
|
4667 |
|
|
d=000000 --!
|
4668 |
|
|
d=100000 --!00, 000000, 000001, 000037, 100000, 000000, 12 {left shift!}
|
4669 |
|
|
d=000000 --!
|
4670 |
|
|
d=000012 --!
|
4671 |
|
|
#37330
|
4672 |
|
|
d=100000 --!00, 000000, 000001, 177737, 000000, 000000, 04 {right shift!} !!->100000
|
4673 |
|
|
d=000000 --!
|
4674 |
|
|
d=000012 --! !!04->12
|
4675 |
|
|
d=100000 --!00, 000000, 000001, 020037, 000000, 000000, 04 {right shift!} !!->100000
|
4676 |
|
|
d=000000 --!
|
4677 |
|
|
d=000012 --! !!04->12
|
4678 |
|
|
# left shifts of negative numbers
|
4679 |
|
|
d=177777 --!00, 177777, 177777, 000001, 177777, 177776, 11
|
4680 |
|
|
d=177776 --!
|
4681 |
|
|
d=000011 --!
|
4682 |
|
|
d=177777 --!00, 177777, 177777, 000002, 177777, 177774, 11
|
4683 |
|
|
d=177774 --!
|
4684 |
|
|
d=000011 --!
|
4685 |
|
|
#37360
|
4686 |
|
|
d=140000 --!00, 177777, 177777, 000036, 140000, 000000, 11
|
4687 |
|
|
d=000000 --!
|
4688 |
|
|
d=000011 --!
|
4689 |
|
|
d=100000 --!00, 177777, 177777, 000037, 100000, 000000, 11
|
4690 |
|
|
d=000000 --!
|
4691 |
|
|
d=000011 --!
|
4692 |
|
|
d=000000 --!00, 177777, 177776, 000037, 000000, 000000, 07
|
4693 |
|
|
d=000000 --!
|
4694 |
|
|
d=000007 --!
|
4695 |
|
|
d=000000 --!00, 177777, 177774, 000037, 000000, 000000, 06
|
4696 |
|
|
d=000000 --!
|
4697 |
|
|
d=000006 --!
|
4698 |
|
|
#37410
|
4699 |
|
|
d=177777 --!00, 177777, 177777, 177701, 177777, 177776, 11
|
4700 |
|
|
d=177776 --!
|
4701 |
|
|
d=000011 --!
|
4702 |
|
|
d=100000 --!00, 177777, 177777, 001037, 177777, 177777, 11 {right shift!} !!->100000
|
4703 |
|
|
d=000000 --! !!->00000
|
4704 |
|
|
d=000011 --!
|
4705 |
|
|
d=140000 --!00, 177777, 177777, 001036, 140000, 000000, 11
|
4706 |
|
|
d=000000 --!
|
4707 |
|
|
d=000011 --!
|
4708 |
|
|
#-----------------------------------------------------------------------------
|
4709 |
|
|
C Setup code 42 [base 12600] (systematic ASHC odd test)
|
4710 |
|
|
#
|
4711 |
|
|
wal 012600 -- code:
|
4712 |
|
|
bwm 15
|
4713 |
|
|
000230 -- spl 0
|
4714 |
|
|
016401 -- L1: mov 2(r4),r1
|
4715 |
|
|
000002
|
4716 |
|
|
011412 -- mov (r4),(r2)
|
4717 |
|
|
073164 -- ashc 4(r4),r1
|
4718 |
|
|
000004
|
4719 |
|
|
011265 -- mov (r2),2(r5)
|
4720 |
|
|
000002
|
4721 |
|
|
#12620
|
4722 |
|
|
010115 -- mov r1,(r5)
|
4723 |
|
|
062704 -- add #6,r4
|
4724 |
|
|
000006
|
4725 |
|
|
062705 -- add #4,r5
|
4726 |
|
|
000004
|
4727 |
|
|
077315 -- sob r3,L1
|
4728 |
|
|
000000 -- halt
|
4729 |
|
|
#
|
4730 |
|
|
C Exec code 42 (systematic ASHC odd test)
|
4731 |
|
|
C Exec test 42.1: data adapted from ashc.s11 code of Begemot p11-2.10c
|
4732 |
|
|
#
|
4733 |
|
|
# The {} comments are original comments from Harti Brandt
|
4734 |
|
|
# Annotations starting with !! indicated mods for W11
|
4735 |
|
|
# Note, that the W11 does not have the microcode bugs of the J11 !
|
4736 |
|
|
#
|
4737 |
|
|
wal 036000 -- setup test vector:
|
4738 |
|
|
# test shift amount 0
|
4739 |
|
|
bwm 165
|
4740 |
|
|
000000 -- 00, 000000, 000000, 000000, 04
|
4741 |
|
|
000000 --
|
4742 |
|
|
000000 --
|
4743 |
|
|
000017 -- 17, 000000, 000000, 000000, 04
|
4744 |
|
|
000000 --
|
4745 |
|
|
000000 --
|
4746 |
|
|
000017 -- 17, 100001, 000000, 100001, 10
|
4747 |
|
|
100001 --
|
4748 |
|
|
000000 --
|
4749 |
|
|
000017 -- 17, 040001, 000000, 040001, 00
|
4750 |
|
|
040001 --
|
4751 |
|
|
000000 --
|
4752 |
|
|
000017 -- 17, 040001, 177700, 040001, 00
|
4753 |
|
|
040001 --
|
4754 |
|
|
177700 --
|
4755 |
|
|
# right rotate positive values
|
4756 |
|
|
000000 -- 00, 000000, 000077, 000000, 04
|
4757 |
|
|
000000 --
|
4758 |
|
|
000077 --
|
4759 |
|
|
000017 -- 17, 000000, 000077, 000000, 04
|
4760 |
|
|
000000 --
|
4761 |
|
|
000077 --
|
4762 |
|
|
000000 -- 00, 000002, 000077, 000001, 00
|
4763 |
|
|
000002 --
|
4764 |
|
|
000077 --
|
4765 |
|
|
000000 -- 00, 000001, 000077, 100000, 01 {cc is funny!}
|
4766 |
|
|
000001 --
|
4767 |
|
|
000077 --
|
4768 |
|
|
000000 -- 00, 000003, 000076, 140000, 01
|
4769 |
|
|
000003 --
|
4770 |
|
|
000076 --
|
4771 |
|
|
000000 -- 00, 000001, 000076, 040000, 00
|
4772 |
|
|
000001 --
|
4773 |
|
|
000076 --
|
4774 |
|
|
000000 -- 00, 040000, 000060, 040000, 00
|
4775 |
|
|
040000 --
|
4776 |
|
|
000060 --
|
4777 |
|
|
000000 -- 00, 040000, 000043, 000002, 00
|
4778 |
|
|
040000 --
|
4779 |
|
|
000043 --
|
4780 |
|
|
000000 -- 00, 040000, 000042, 000001, 00
|
4781 |
|
|
040000 --
|
4782 |
|
|
000042 --
|
4783 |
|
|
000000 -- 00, 040000, 000041, 000000, 05
|
4784 |
|
|
040000 --
|
4785 |
|
|
000041 --
|
4786 |
|
|
000000 -- 00, 040000, 000040, 000000, 04
|
4787 |
|
|
040000 --
|
4788 |
|
|
000040 --
|
4789 |
|
|
000000 -- 00, 040000, 100037, 000000, 04
|
4790 |
|
|
040000 --
|
4791 |
|
|
100037 --
|
4792 |
|
|
000000 -- 00, 020000, 000043, 000001, 00
|
4793 |
|
|
020000 --
|
4794 |
|
|
000043 --
|
4795 |
|
|
000000 -- 00, 020000, 000042, 000000, 05
|
4796 |
|
|
020000 --
|
4797 |
|
|
000042 --
|
4798 |
|
|
000000 -- 00, 020000, 000041, 000000, 04
|
4799 |
|
|
020000 --
|
4800 |
|
|
000041 --
|
4801 |
|
|
# right rotate negative numbers
|
4802 |
|
|
000000 -- 00, 100002, 000077, 040001, 10
|
4803 |
|
|
100002 --
|
4804 |
|
|
000077 --
|
4805 |
|
|
000000 -- 00, 100002, 000076, 120000, 11
|
4806 |
|
|
100002 --
|
4807 |
|
|
000076 --
|
4808 |
|
|
000000 -- 00, 100002, 000075, 050000, 10
|
4809 |
|
|
100002 --
|
4810 |
|
|
000075 --
|
4811 |
|
|
000000 -- 00, 100002, 000061, 000005, 10
|
4812 |
|
|
100002 --
|
4813 |
|
|
000061 --
|
4814 |
|
|
000000 -- 00, 100002, 000060, 100002, 11
|
4815 |
|
|
100002 --
|
4816 |
|
|
000060 --
|
4817 |
|
|
000000 -- 00, 100002, 000057, 140001, 10
|
4818 |
|
|
100002 --
|
4819 |
|
|
000057 --
|
4820 |
|
|
000000 -- 00, 100002, 000056, 160000, 11
|
4821 |
|
|
100002 --
|
4822 |
|
|
000056 --
|
4823 |
|
|
000000 -- 00, 100002, 000055, 170000, 10
|
4824 |
|
|
100002 --
|
4825 |
|
|
000055 --
|
4826 |
|
|
000000 -- 00, 100002, 000042, 177776, 10
|
4827 |
|
|
100002 --
|
4828 |
|
|
000042 --
|
4829 |
|
|
000000 -- 00, 100002, 000041, 177777, 10
|
4830 |
|
|
100002 --
|
4831 |
|
|
000041 --
|
4832 |
|
|
000000 -- 00, 100002, 000040, 177777, 11
|
4833 |
|
|
100002 --
|
4834 |
|
|
000040 --
|
4835 |
|
|
000000 -- 00, 100002, 040037, 177777, 11
|
4836 |
|
|
100002 --
|
4837 |
|
|
040037 --
|
4838 |
|
|
# left rotate positive numbers
|
4839 |
|
|
000000 -- 00, 000000, 000001, 000000, 04
|
4840 |
|
|
000000 --
|
4841 |
|
|
000001 --
|
4842 |
|
|
000000 -- 17, 000000, 000001, 000000, 04
|
4843 |
|
|
000000 --
|
4844 |
|
|
000001 --
|
4845 |
|
|
000000 -- 00, 000001, 000007, 000200, 00
|
4846 |
|
|
000001 --
|
4847 |
|
|
000007 --
|
4848 |
|
|
000000 -- 00, 000001, 000016, 040000, 00
|
4849 |
|
|
000001 --
|
4850 |
|
|
000016 --
|
4851 |
|
|
000000 -- 00, 000001, 000017, 100000, 12
|
4852 |
|
|
000001 --
|
4853 |
|
|
000017 --
|
4854 |
|
|
000000 -- 00, 000001, 000020, 000000, 03
|
4855 |
|
|
000001 --
|
4856 |
|
|
000020 --
|
4857 |
|
|
000000 -- 00, 000001, 000021, 000000, 02
|
4858 |
|
|
000001 --
|
4859 |
|
|
000021 --
|
4860 |
|
|
000000 -- 00, 000001, 000036, 000000, 02
|
4861 |
|
|
000001 --
|
4862 |
|
|
000036 --
|
4863 |
|
|
000000 -- 00, 000001, 000037, 000000, 12
|
4864 |
|
|
000001 --
|
4865 |
|
|
000037 --
|
4866 |
|
|
000000 -- 00, 000001, 000040, 000000, 04 {right shift!}
|
4867 |
|
|
000001 --
|
4868 |
|
|
000040 --
|
4869 |
|
|
000000 -- 00, 000001, 010037, 000000, 04 {right shift!}
|
4870 |
|
|
000001 --
|
4871 |
|
|
010037 --
|
4872 |
|
|
# left rotate negative numbers
|
4873 |
|
|
000000 -- 00, 100001, 000001, 000002, 03
|
4874 |
|
|
100001 --
|
4875 |
|
|
000001 --
|
4876 |
|
|
000000 -- 00, 140001, 000001, 100002, 11
|
4877 |
|
|
140001 --
|
4878 |
|
|
000001 --
|
4879 |
|
|
000000 -- 00, 140001, 000002, 000004, 03
|
4880 |
|
|
140001 --
|
4881 |
|
|
000002 --
|
4882 |
|
|
000000 -- 00, 140001, 000016, 040000, 02
|
4883 |
|
|
140001 --
|
4884 |
|
|
000016 --
|
4885 |
|
|
000000 -- 00, 140001, 000017, 100000, 12
|
4886 |
|
|
140001 --
|
4887 |
|
|
000017 --
|
4888 |
|
|
000000 -- 00, 140001, 000020, 000000, 13
|
4889 |
|
|
140001 --
|
4890 |
|
|
000020 --
|
4891 |
|
|
000000 -- 00, 140001, 000021, 000000, 13
|
4892 |
|
|
140001 --
|
4893 |
|
|
000021 --
|
4894 |
|
|
000000 -- 00, 140001, 000022, 000000, 03
|
4895 |
|
|
140001 --
|
4896 |
|
|
000022 --
|
4897 |
|
|
000000 -- 00, 140001, 000023, 000000, 02
|
4898 |
|
|
140001 --
|
4899 |
|
|
000023 --
|
4900 |
|
|
000000 -- 00, 140002, 000035, 000000, 02
|
4901 |
|
|
140002 --
|
4902 |
|
|
000035 --
|
4903 |
|
|
000000 -- 00, 140002, 000036, 000000, 12
|
4904 |
|
|
140002 --
|
4905 |
|
|
000036 --
|
4906 |
|
|
000000 -- 00, 140002, 000037, 000000, 07
|
4907 |
|
|
140002 --
|
4908 |
|
|
000037 --
|
4909 |
|
|
#----
|
4910 |
|
|
wr2 177776 -- r2=177776 -> psw
|
4911 |
|
|
wr3 000067 -- r3=67 (55.) -> test count
|
4912 |
|
|
wr4 036000 -- r4=36000 -> input area
|
4913 |
|
|
wr5 037000 -- r5=37000 -> output area
|
4914 |
|
|
wsp 001400 -- sp=1400
|
4915 |
|
|
stapc 012600 -- start @ 12600
|
4916 |
|
|
wtgo
|
4917 |
|
|
rpc d=012636 -- ! pc
|
4918 |
|
|
rr3 d=000000 -- ! r3=0
|
4919 |
|
|
rr4 d=036512 -- ! r4=36512
|
4920 |
|
|
rr5 d=037334 -- ! r5=37334
|
4921 |
|
|
wal 037000 --
|
4922 |
|
|
# test shift amount 0
|
4923 |
|
|
brm 110
|
4924 |
|
|
d=000000 --!00, 000000, 000000, 000000, 04
|
4925 |
|
|
d=000004 --!
|
4926 |
|
|
d=000000 --!17, 000000, 000000, 000000, 04
|
4927 |
|
|
d=000004 --!
|
4928 |
|
|
d=100001 --!17, 100001, 000000, 100001, 10
|
4929 |
|
|
d=000010 --!
|
4930 |
|
|
d=040001 --!17, 040001, 000000, 040001, 00
|
4931 |
|
|
d=000000 --!
|
4932 |
|
|
#37020
|
4933 |
|
|
d=040001 --!17, 040001, 177700, 040001, 00
|
4934 |
|
|
d=000000 --!
|
4935 |
|
|
# right rotate positive values
|
4936 |
|
|
d=000000 --!00, 000000, 000077, 000000, 04
|
4937 |
|
|
d=000004 --!
|
4938 |
|
|
d=000000 --!17, 000000, 000077, 000000, 04
|
4939 |
|
|
d=000004 --!
|
4940 |
|
|
d=000001 --!00, 000002, 000077, 000001, 00
|
4941 |
|
|
d=000000 --!
|
4942 |
|
|
#37040
|
4943 |
|
|
d=100000 --!00, 000001, 000077, 100000, 01 {cc is funny!}
|
4944 |
|
|
d=000001 --!
|
4945 |
|
|
d=140000 --!00, 000003, 000076, 140000, 01
|
4946 |
|
|
d=000001 --!
|
4947 |
|
|
d=040000 --!00, 000001, 000076, 040000, 00
|
4948 |
|
|
d=000000 --!
|
4949 |
|
|
d=040000 --!00, 040000, 000060, 040000, 00
|
4950 |
|
|
d=000000 --!
|
4951 |
|
|
#37060
|
4952 |
|
|
d=000002 --!00, 040000, 000043, 000002, 00
|
4953 |
|
|
d=000000 --!
|
4954 |
|
|
d=000001 --!00, 040000, 000042, 000001, 00
|
4955 |
|
|
d=000000 --!
|
4956 |
|
|
d=000000 --!00, 040000, 000041, 000000, 05
|
4957 |
|
|
d=000005 --!
|
4958 |
|
|
d=000000 --!00, 040000, 000040, 000000, 04
|
4959 |
|
|
d=000004 --!
|
4960 |
|
|
#37100
|
4961 |
|
|
d=000000 --!00, 040000, 100037, 000000, 04
|
4962 |
|
|
d=000006 --! !!04->06
|
4963 |
|
|
d=000001 --!00, 020000, 000043, 000001, 00
|
4964 |
|
|
d=000000 --!
|
4965 |
|
|
d=000000 --!00, 020000, 000042, 000000, 05
|
4966 |
|
|
d=000005 --!
|
4967 |
|
|
d=000000 --!00, 020000, 000041, 000000, 04
|
4968 |
|
|
d=000004 --!
|
4969 |
|
|
#37120 # right rotate negative numbers
|
4970 |
|
|
d=040001 --!00, 100002, 000077, 040001, 10
|
4971 |
|
|
d=000010 --!
|
4972 |
|
|
d=120000 --!00, 100002, 000076, 120000, 11
|
4973 |
|
|
d=000011 --!
|
4974 |
|
|
d=050000 --!00, 100002, 000075, 050000, 10
|
4975 |
|
|
d=000010 --!
|
4976 |
|
|
d=000005 --!00, 100002, 000061, 000005, 10
|
4977 |
|
|
d=000010 --!
|
4978 |
|
|
#37140
|
4979 |
|
|
d=100002 --!00, 100002, 000060, 100002, 11
|
4980 |
|
|
d=000011 --!
|
4981 |
|
|
d=140001 --!00, 100002, 000057, 140001, 10
|
4982 |
|
|
d=000010 --!
|
4983 |
|
|
d=160000 --!00, 100002, 000056, 160000, 11
|
4984 |
|
|
d=000011 --!
|
4985 |
|
|
d=170000 --!00, 100002, 000055, 170000, 10
|
4986 |
|
|
d=000010 --!
|
4987 |
|
|
#37160
|
4988 |
|
|
d=177776 --!00, 100002, 000042, 177776, 10
|
4989 |
|
|
d=000010 --!
|
4990 |
|
|
d=177777 --!00, 100002, 000041, 177777, 10
|
4991 |
|
|
d=000010 --!
|
4992 |
|
|
d=177777 --!00, 100002, 000040, 177777, 11
|
4993 |
|
|
d=000011 --!
|
4994 |
|
|
d=000000 --!00, 100002, 040037, 177777, 11 !!->000000
|
4995 |
|
|
d=000007 --! !!11->07
|
4996 |
|
|
#37200 # left rotate positive numbers
|
4997 |
|
|
d=000000 --!00, 000000, 000001, 000000, 04
|
4998 |
|
|
d=000004 --!
|
4999 |
|
|
d=000000 --!17, 000000, 000001, 000000, 04
|
5000 |
|
|
d=000004 --!
|
5001 |
|
|
d=000200 --!00, 000001, 000007, 000200, 00
|
5002 |
|
|
d=000000 --!
|
5003 |
|
|
d=040000 --!00, 000001, 000016, 040000, 00
|
5004 |
|
|
d=000000 --!
|
5005 |
|
|
#37220
|
5006 |
|
|
d=100000 --!00, 000001, 000017, 100000, 12
|
5007 |
|
|
d=000012 --!
|
5008 |
|
|
d=000000 --!00, 000001, 000020, 000000, 03
|
5009 |
|
|
d=000003 --!
|
5010 |
|
|
d=000000 --!00, 000001, 000021, 000000, 02
|
5011 |
|
|
d=000002 --!
|
5012 |
|
|
d=000000 --!00, 000001, 000036, 000000, 02
|
5013 |
|
|
d=000002 --!
|
5014 |
|
|
#37240
|
5015 |
|
|
d=000000 --!00, 000001, 000037, 000000, 12
|
5016 |
|
|
d=000012 --!
|
5017 |
|
|
d=000000 --!00, 000001, 000040, 000000, 04 {right shift!}
|
5018 |
|
|
d=000004 --!
|
5019 |
|
|
d=000000 --!00, 000001, 010037, 000000, 04 {right shift!}
|
5020 |
|
|
d=000012 --! !!04->12
|
5021 |
|
|
# left rotate negative numbers
|
5022 |
|
|
d=000002 --!00, 100001, 000001, 000002, 03
|
5023 |
|
|
d=000003 --!
|
5024 |
|
|
#37260
|
5025 |
|
|
d=100002 --!00, 140001, 000001, 100002, 11
|
5026 |
|
|
d=000011 --!
|
5027 |
|
|
d=000004 --!00, 140001, 000002, 000004, 03
|
5028 |
|
|
d=000003 --!
|
5029 |
|
|
d=040000 --!00, 140001, 000016, 040000, 02
|
5030 |
|
|
d=000002 --!
|
5031 |
|
|
d=100000 --!00, 140001, 000017, 100000, 12
|
5032 |
|
|
d=000012 --!
|
5033 |
|
|
#37300
|
5034 |
|
|
d=000000 --!00, 140001, 000020, 000000, 13
|
5035 |
|
|
d=000013 --!
|
5036 |
|
|
d=000000 --!00, 140001, 000021, 000000, 13
|
5037 |
|
|
d=000013 --!
|
5038 |
|
|
d=000000 --!00, 140001, 000022, 000000, 03
|
5039 |
|
|
d=000003 --!
|
5040 |
|
|
d=000000 --!00, 140001, 000023, 000000, 02
|
5041 |
|
|
d=000002 --!
|
5042 |
|
|
#37320
|
5043 |
|
|
d=000000 --!00, 140002, 000035, 000000, 02
|
5044 |
|
|
d=000002 --!
|
5045 |
|
|
d=000000 --!00, 140002, 000036, 000000, 12
|
5046 |
|
|
d=000012 --!
|
5047 |
|
|
d=000000 --!00, 140002, 000037, 000000, 07
|
5048 |
|
|
d=000007 --!
|
5049 |
|
|
#-----------------------------------------------------------------------------
|
5050 |
|
|
C Setup code 43 [base 12700] (Begemot MARK instruction test)
|
5051 |
|
|
# test data and code adapted from Mark.s11 code of Begemot p11-2.10c
|
5052 |
|
|
#
|
5053 |
|
|
wal 012700 -- code test 1: (basics)
|
5054 |
|
|
bwm 14
|
5055 |
|
|
012705 -- mov #77077,r5 ; cookie
|
5056 |
|
|
077077
|
5057 |
|
|
010546 -- mov r5,-(sp) ; push r5
|
5058 |
|
|
012746 -- mov #12,-(sp) ; parameter 1
|
5059 |
|
|
000012
|
5060 |
|
|
012746 -- mov #23,-(sp) ; parameter 2
|
5061 |
|
|
000023
|
5062 |
|
|
012746 -- mov #mark+2,-(sp) ; now the mark instruction
|
5063 |
|
|
#12720
|
5064 |
|
|
006402
|
5065 |
|
|
010605 -- mov sp,r5 ; let r5 point to mark instruction
|
5066 |
|
|
004737 -- jsr pc,subr ; call subroutine
|
5067 |
|
|
012770
|
5068 |
|
|
000240 -- noop
|
5069 |
|
|
000000 -- halt
|
5070 |
|
|
#-----
|
5071 |
|
|
wal 012740 -- code test 2: (MARK with max. # of args)
|
5072 |
|
|
bwm 10
|
5073 |
|
|
010546 -- mov r5, -(sp) ; push r5
|
5074 |
|
|
162706 -- sub #2*77, sp ; max number
|
5075 |
|
|
000176
|
5076 |
|
|
012746 -- mov #mark+77, -(sp) ; the mark instruction
|
5077 |
|
|
006477
|
5078 |
|
|
010605 -- mov sp, r5 ; let r5 point to mark instruction
|
5079 |
|
|
004737 -- jsr pc, subr ; call subroutine
|
5080 |
|
|
012770
|
5081 |
|
|
#12760
|
5082 |
|
|
000240 -- noop
|
5083 |
|
|
000000 -- halt
|
5084 |
|
|
#-----
|
5085 |
|
|
wal 012770 -- code (procedure):
|
5086 |
|
|
wmi 000205 -- subr: rts r5
|
5087 |
|
|
#-----
|
5088 |
|
|
C Exec code 43 (Begemot MARK test)
|
5089 |
|
|
C Exec test 43.1 (basics)
|
5090 |
|
|
# D RE RQ FU DAT
|
5091 |
|
|
wsp 001400 -- sp=1400
|
5092 |
|
|
stapc 012700 -- start @ 12700
|
5093 |
|
|
wtgo
|
5094 |
|
|
rpc d=012734 -- ! pc
|
5095 |
|
|
rr5 d=077077 -- ! r5
|
5096 |
|
|
rsp d=001400 -- ! sp
|
5097 |
|
|
wal 001366 --
|
5098 |
|
|
brm 5
|
5099 |
|
|
d=012730 -- ! mem(1366)
|
5100 |
|
|
d=006402 -- ! mem(1370)
|
5101 |
|
|
d=000023 -- ! mem(1372)
|
5102 |
|
|
d=000012 -- ! mem(1374)
|
5103 |
|
|
d=077077 -- ! mem(1376)
|
5104 |
|
|
#----
|
5105 |
|
|
C Exec test 43.2 (MARK with max. # of args)
|
5106 |
|
|
# D RE RQ FU DAT
|
5107 |
|
|
wsp 001400 -- sp=1400
|
5108 |
|
|
stapc 012740 -- start @ 12740
|
5109 |
|
|
wtgo
|
5110 |
|
|
rpc d=012764 -- ! pc
|
5111 |
|
|
rr5 d=077077 -- ! r5
|
5112 |
|
|
rsp d=001400 -- ! sp
|
5113 |
|
|
#-----------------------------------------------------------------------------
|
5114 |
|
|
C Setup code 44 [base 13000] (Implementation variations)
|
5115 |
|
|
# test various PDP11 implementation variations (DCJ11 user guide, table C-1)
|
5116 |
|
|
#
|
5117 |
|
|
wal 013000 -- code: (to be single stepped mostly)
|
5118 |
|
|
bwm 22
|
5119 |
|
|
010424 -- mov r4,(r4)+ ; case 1 and 2
|
5120 |
|
|
010444 -- mov r4,-(r4)
|
5121 |
|
|
010764 -- mov pc,2(r4)
|
5122 |
|
|
000002
|
5123 |
|
|
000124 -- jmp (r4)+
|
5124 |
|
|
000104 -- jmp r4
|
5125 |
|
|
000304 -- swab r4
|
5126 |
|
|
005214 -- inc (r4)
|
5127 |
|
|
#13020
|
5128 |
|
|
000006 -- rtt
|
5129 |
|
|
000000 -- halt
|
5130 |
|
|
000002 -- rti
|
5131 |
|
|
000000 -- halt
|
5132 |
|
|
010011 -- mov r0,(r1)
|
5133 |
|
|
010046 -- mov r0,-(sp)
|
5134 |
|
|
000114 -- jmp (r4)
|
5135 |
|
|
010021 -- mov r0,(r1)+
|
5136 |
|
|
#13040
|
5137 |
|
|
012100 -- mov (r1)+,r0
|
5138 |
|
|
005221 -- inc (r1)+
|
5139 |
|
|
106621 -- mtpd (r1)+
|
5140 |
|
|
106506 -- mfpd sp
|
5141 |
|
|
106606 -- mtpd sp
|
5142 |
|
|
000003 -- bpt
|
5143 |
|
|
#-----
|
5144 |
|
|
wal 013070 -- code: (target for rtt,rti tests)
|
5145 |
|
|
bwm 2
|
5146 |
|
|
000240 -- noop
|
5147 |
|
|
000000 -- halt
|
5148 |
|
|
#-----
|
5149 |
|
|
C Exec code 44 (Implementation variations)
|
5150 |
|
|
C test 44.1: OPR R,(R)+ : incremented before {J11} or after {70} use as source
|
5151 |
|
|
#
|
5152 |
|
|
rst -- console reset
|
5153 |
|
|
wps 000000 -- clear psw
|
5154 |
|
|
wr4 001600 -- r4=1600
|
5155 |
|
|
wsp 001400 -- sp=1400
|
5156 |
|
|
wpc 013000 -- pc=13000
|
5157 |
|
|
step -- step (mov r4,(r4)+)
|
5158 |
|
|
rpc d=013002 -- ! pc=13002
|
5159 |
|
|
rr4 d=001602 -- ! r4=1602
|
5160 |
|
|
wal 001600 -- check target location
|
5161 |
|
|
rmi d=001600 -- ! ; initial content of R expected for 11/70
|
5162 |
|
|
#
|
5163 |
|
|
C test 44.2: OPR R,-(R) : decremented before {J11} or after {70} use as source
|
5164 |
|
|
#
|
5165 |
|
|
wr4 001600 -- r4=1600
|
5166 |
|
|
wsp 001400 -- sp=1400
|
5167 |
|
|
wpc 013002 -- pc=13002
|
5168 |
|
|
step -- step (mov r4,-(r4))
|
5169 |
|
|
rpc d=013004 -- ! pc=13004
|
5170 |
|
|
rr4 d=001576 -- ! r4=1576
|
5171 |
|
|
wal 001600 -- check target location
|
5172 |
|
|
rmi d=001600 -- ! ; initial content of R expected for 11/70
|
5173 |
|
|
#
|
5174 |
|
|
C test 44.3: OPR PC,A(R) : store PC+2 {70} or PC+4 {J11}
|
5175 |
|
|
#
|
5176 |
|
|
wr4 001600 -- r4=1600
|
5177 |
|
|
wsp 001400 -- sp=1400
|
5178 |
|
|
wpc 013004 -- pc=13004
|
5179 |
|
|
step -- step (mov pc,2(r4))
|
5180 |
|
|
rpc d=013010 -- ! pc=13010
|
5181 |
|
|
wal 001602 -- check target location
|
5182 |
|
|
rmi d=013006 -- ! ; PC+2 expected for 11/70
|
5183 |
|
|
#
|
5184 |
|
|
C test 44.4: JMP (R)+ : R used {70;J11} or R+2 used {05,10,15,20}
|
5185 |
|
|
#
|
5186 |
|
|
wr4 013074 -- r4=13074
|
5187 |
|
|
wsp 001400 -- sp=1400
|
5188 |
|
|
wpc 013010 -- pc=13010
|
5189 |
|
|
step -- step (jmp (r4)+)
|
5190 |
|
|
rpc d=013074 -- ! pc=13074 ; R expected for 11/70
|
5191 |
|
|
rr4 d=013076 -- ! r4=13076
|
5192 |
|
|
#
|
5193 |
|
|
C test 44.5: JMP R : traps to 10 {44,45,70;J11} or 4 {all others}
|
5194 |
|
|
C Note: J11 doc is wrong, 11/70 traps 10, not 4, as stated
|
5195 |
|
|
#
|
5196 |
|
|
wal 177766 -- clear CPUERR
|
5197 |
|
|
wm 000000 --
|
5198 |
|
|
wr4 000000 -- r4=0
|
5199 |
|
|
wsp 001400 -- sp=1400
|
5200 |
|
|
wpc 013012 -- pc=13012
|
5201 |
|
|
step -- step (jmp r4) [[s:2]]
|
5202 |
|
|
rpc d=000012 -- ! pc=12 ; trap 10 expected for 11/70 [[s:10]]
|
5203 |
|
|
rsp d=001374 -- ! sp=1374
|
5204 |
|
|
wal 177766 -- check CPUERR
|
5205 |
|
|
rm d=000000 -- ! CPUERR: no bit set
|
5206 |
|
|
wm 000000 -- clear CPUERR
|
5207 |
|
|
#
|
5208 |
|
|
C test 44.6: SWAB does not change V {15,20} or clears V {all others}
|
5209 |
|
|
#
|
5210 |
|
|
wr4 000300 -- r4=3000
|
5211 |
|
|
wsp 001400 -- sp=1400
|
5212 |
|
|
wpc 013014 -- pc=13014
|
5213 |
|
|
wps 000017 -- psw: set all cc flags in psw
|
5214 |
|
|
step -- step (swab r4)
|
5215 |
|
|
rpc d=013016 -- ! pc=13074
|
5216 |
|
|
rr4 d=140000 -- ! r4=140000
|
5217 |
|
|
rps d=000004 -- ! psw: Z=1 ; clear V expected for 11/70
|
5218 |
|
|
#
|
5219 |
|
|
C test 44.7: CPU access to 177700-177717 (regs) timesout {70,J11} or not {05,10}
|
5220 |
|
|
#
|
5221 |
|
|
wr4 177700 -- r4=177700
|
5222 |
|
|
wsp 001400 -- sp=1400
|
5223 |
|
|
wpc 013016 -- pc=13016
|
5224 |
|
|
step -- step (inc (r4)) [[s:2]]
|
5225 |
|
|
rpc d=000006 -- ! pc=6 ; trap 4 expected for 11/70 [[s:10]]
|
5226 |
|
|
rsp d=001374 -- ! sp=1374
|
5227 |
|
|
wal 177766 -- check CPUERR
|
5228 |
|
|
rm d=000020 -- ! CPUERR: (iobto=1)
|
5229 |
|
|
wm 000000 -- clear CPUERR
|
5230 |
|
|
#
|
5231 |
|
|
C test 44.10: If RTT sets T bit, trap occurs after instr. following RTT {70,J11}
|
5232 |
|
|
#
|
5233 |
|
|
wal 001374 -- setup stack with rtt return frame setting T flag
|
5234 |
|
|
bwm 2
|
5235 |
|
|
013070 -- start address (points to: noop, halt)
|
5236 |
|
|
000020 -- set T flag in PSW
|
5237 |
|
|
wsp 001374 -- sp=1374
|
5238 |
|
|
wpc 013020 -- pc=13020
|
5239 |
|
|
cont -- cont (rtt)
|
5240 |
|
|
wtgo
|
5241 |
|
|
rpc d=000020 -- ! pc=20 ; T-trap executed
|
5242 |
|
|
rsp d=001374 -- ! sp=1374
|
5243 |
|
|
wal 001374 -- check stack
|
5244 |
|
|
brm 2
|
5245 |
|
|
d=013072 -- trap address: address after noop expected for 11/70
|
5246 |
|
|
d=000020 -- PSW
|
5247 |
|
|
rst -- console reset (to clear T flag)
|
5248 |
|
|
#
|
5249 |
|
|
C test 44.11: If RTI sets T bit, T trap occurs immediately {70,J11}
|
5250 |
|
|
#
|
5251 |
|
|
wal 001374 -- setup stack with rtt return frame setting T flag
|
5252 |
|
|
bwm 2
|
5253 |
|
|
013070 -- start address (points to: noop, halt)
|
5254 |
|
|
000020 -- set T flag in PSW
|
5255 |
|
|
wsp 001374 -- sp=1374
|
5256 |
|
|
wpc 013024 -- pc=13024
|
5257 |
|
|
cont -- cont (rti)
|
5258 |
|
|
wtgo
|
5259 |
|
|
rpc d=000020 -- ! pc=20 ; T-trap executed
|
5260 |
|
|
rsp d=001374 -- ! sp=1374
|
5261 |
|
|
wal 001374 -- check stack
|
5262 |
|
|
brm 2
|
5263 |
|
|
d=013070 -- trap address: address of noop expected for 11/70
|
5264 |
|
|
d=000020 -- PSW
|
5265 |
|
|
rst -- console reset (to clear T flag)
|
5266 |
|
|
#
|
5267 |
|
|
C test 44.14: Direct access to PSW can {05..20} / cannot {others} set T bit
|
5268 |
|
|
#
|
5269 |
|
|
wr0 000030 -- r0=30 (set T bit, N also)
|
5270 |
|
|
wr1 177776 -- r1=177776 (PSW address)
|
5271 |
|
|
wsp 001400 -- sp=1400
|
5272 |
|
|
wpc 013030 -- pc=13030
|
5273 |
|
|
step -- step (mov r0,(r1))
|
5274 |
|
|
rpc d=013032 -- ! pc=13032
|
5275 |
|
|
rps d=000010 -- ! psw: T bit not set expected for 11/70
|
5276 |
|
|
#
|
5277 |
|
|
C test 44.15: odd address using SP causes HALT {<=20} or emmergency stack {>35}
|
5278 |
|
|
#
|
5279 |
|
|
wsp 001401 -- sp=1401
|
5280 |
|
|
wpc 013032 -- pc=13032
|
5281 |
|
|
step -- step (mov r0,-(sp)) [[s:2]]
|
5282 |
|
|
rpc d=000006 -- ! pc=6 ; trap 4 [[s:13034]]
|
5283 |
|
|
rsp d=000000 -- ! sp=0 ; emergency stack expected for 11/70 [[s:4]]
|
5284 |
|
|
wal 000000 -- check emergency stack
|
5285 |
|
|
brm 2
|
5286 |
|
|
d=013034 -- ! PC of abort [[s:0]]
|
5287 |
|
|
d=000000 -- ! PS of abort (currently gets lost...)
|
5288 |
|
|
rst -- console reset (to clear CPUERR reg)
|
5289 |
|
|
wal 000000 -- clean tainted memory
|
5290 |
|
|
bwm 2
|
5291 |
|
|
000000 --
|
5292 |
|
|
000000 --
|
5293 |
|
|
#
|
5294 |
|
|
# simh notes:
|
5295 |
|
|
# 1. apparently not consistently implemented in simh. SP is set to 4, but
|
5296 |
|
|
# interrupt/trap sequence isn't executed. Effectively, simh halt's.
|
5297 |
|
|
#
|
5298 |
|
|
# for the test 28/29/30x enable MMU and make address 100000 unavailable
|
5299 |
|
|
#
|
5300 |
|
|
wal 172310 -- kernel I space DR segment 4 (base 100000)
|
5301 |
|
|
wmi 077400 -- slf=127; ed=0(up); acf=0 (non resident)
|
5302 |
|
|
#
|
5303 |
|
|
C test 44.28: If PC->bad memory, PC incremented {others} / not inc'ed {35,40}
|
5304 |
|
|
#
|
5305 |
|
|
wal 177572 -- SSR0
|
5306 |
|
|
wmi 000001 -- set enable bit
|
5307 |
|
|
wr4 100000 -- r4=100000
|
5308 |
|
|
wsp 001400 -- sp=1400
|
5309 |
|
|
wpc 013034 -- pc=13034
|
5310 |
|
|
cont -- cont (jmp (r4))
|
5311 |
|
|
wtgo
|
5312 |
|
|
rpc d=000254 -- ! pc=254 ; trap 240 ; Note: halt is executed, was cont !
|
5313 |
|
|
rsp d=001374 -- ! sp=1374
|
5314 |
|
|
wal 001374 -- check stack
|
5315 |
|
|
brm 2
|
5316 |
|
|
d=100002 -- trap address: PC inc'ed expected for 11/70 [[s:100000]]
|
5317 |
|
|
d=000340 -- PSW
|
5318 |
|
|
rst -- console reset (to clear CPUERR reg)
|
5319 |
|
|
#
|
5320 |
|
|
# simh notes:
|
5321 |
|
|
# 1. simh reads instruction, later increments PC. Thus PC not inc'ed in simh.
|
5322 |
|
|
#
|
5323 |
|
|
C test 44.29/30a: If R->bad in mode 2, R inc'ed {others} / or not {4,34,44}
|
5324 |
|
|
C test for dstw chain (mov r0,(r1)+)
|
5325 |
|
|
#
|
5326 |
|
|
wal 177572 -- SSR0
|
5327 |
|
|
wmi 000001 -- set enable bit
|
5328 |
|
|
wr1 100000 -- r1=100000
|
5329 |
|
|
wsp 001400 -- sp=1400
|
5330 |
|
|
wpc 013036 -- pc=13036
|
5331 |
|
|
step -- step (mov r0,(r1)+) [[s:2]]
|
5332 |
|
|
rpc d=000252 -- ! pc=252 ; trap 250 [[s:254]]
|
5333 |
|
|
rsp d=001374 -- ! sp=1374
|
5334 |
|
|
rr1 d=100002 -- ! r1=100002
|
5335 |
|
|
wal 177572 -- check SSR0/1
|
5336 |
|
|
brm 2
|
5337 |
|
|
d=100011 -- ! SSR0: (abo_nonres=1,seg=4,ena=1) see note [[s:100211]]
|
5338 |
|
|
d=000021 -- ! SSR1: ra=1,2
|
5339 |
|
|
rst -- console reset (to clear CPUERR reg)
|
5340 |
|
|
#
|
5341 |
|
|
C test 44.29/30b: If R->bad in mode 2, R inc'ed {others} / or not {4,34,44}
|
5342 |
|
|
C test for srcr chain (mov (r1)+,r0)
|
5343 |
|
|
#
|
5344 |
|
|
wal 177572 -- SSR0
|
5345 |
|
|
wmi 000001 -- set enable bit
|
5346 |
|
|
wr1 100000 -- r1=100000
|
5347 |
|
|
wsp 001400 -- sp=1400
|
5348 |
|
|
wpc 013040 -- pc=13040
|
5349 |
|
|
step -- step ((mov (r1)+,r0) [[s:2]]
|
5350 |
|
|
rpc d=000252 -- ! pc=252 ; trap 250 [[s:254]]
|
5351 |
|
|
rsp d=001374 -- ! sp=1374
|
5352 |
|
|
rr1 d=100002 -- ! r1=100002
|
5353 |
|
|
wal 177572 -- check SSR0/1
|
5354 |
|
|
brm 2
|
5355 |
|
|
d=100011 -- ! SSR0: (abo_nonres=1,seg=4,ena=1) see note [[s:100211]]
|
5356 |
|
|
d=000021 -- ! SSR1: ra=1,2
|
5357 |
|
|
rst -- console reset (to clear CPUERR reg)
|
5358 |
|
|
#
|
5359 |
|
|
C test 44.29/30c: If R->bad in mode 2, R inc'ed {others} / or not {4,34,44}
|
5360 |
|
|
C test for dstr chain (inc (r1)+)
|
5361 |
|
|
#
|
5362 |
|
|
wal 177572 -- SSR0
|
5363 |
|
|
wmi 000001 -- set enable bit
|
5364 |
|
|
wr1 100000 -- r1=100000
|
5365 |
|
|
wsp 001400 -- sp=1400
|
5366 |
|
|
wpc 013042 -- pc=13042
|
5367 |
|
|
step -- step (inc (r1)+) [[s:2]]
|
5368 |
|
|
rpc d=000252 -- ! pc=252 ; trap 250 [[s:254]]
|
5369 |
|
|
rsp d=001374 -- ! sp=1374
|
5370 |
|
|
rr1 d=100002 -- ! r1=100002
|
5371 |
|
|
wal 177572 -- check SSR0/1
|
5372 |
|
|
brm 2
|
5373 |
|
|
d=100011 -- ! SSR0: (abo_nonres=1,seg=4,ena=1) see note [[s:100211]]
|
5374 |
|
|
d=000021 -- ! SSR1: ra=1,2
|
5375 |
|
|
rst -- console reset (to clear CPUERR reg)
|
5376 |
|
|
C test 44.29/30d: If R->bad in mode 2, R inc'ed {others} / or not {4,34,44}
|
5377 |
|
|
C test for dsta chain (mtpd (r1)+)
|
5378 |
|
|
#
|
5379 |
|
|
wal 177572 -- SSR0
|
5380 |
|
|
wmi 000001 -- set enable bit
|
5381 |
|
|
wr1 100000 -- r1=100000
|
5382 |
|
|
wsp 001376 -- sp=1376
|
5383 |
|
|
wpc 013044 -- pc=13044
|
5384 |
|
|
wal 001376 -- push a word on stack for mtpd
|
5385 |
|
|
wmi 123456 --
|
5386 |
|
|
step -- step (mtpd (r1)+) [[s:2]]
|
5387 |
|
|
rpc d=000252 -- ! pc=252 ; trap 250 [[s:254]]
|
5388 |
|
|
rsp d=001374 -- ! sp=1374
|
5389 |
|
|
rr1 d=100002 -- ! r1=100002
|
5390 |
|
|
wal 177572 -- check SSR0/1
|
5391 |
|
|
brm 2
|
5392 |
|
|
d=100011 -- ! SSR0: (abo_nonres=1,seg=4,ena=1) see note [[s:100211]]
|
5393 |
|
|
d=010426 -- ! SSR1: rb=1,2; ra=6,2
|
5394 |
|
|
rst -- console reset (to clear CPUERR reg)
|
5395 |
|
|
#
|
5396 |
|
|
# simh notes:
|
5397 |
|
|
# 1. simh first pops, than writes to destination, reversing ra,rb in SSR1
|
5398 |
|
|
#
|
5399 |
|
|
# now reset MMU to default
|
5400 |
|
|
#
|
5401 |
|
|
wal 172310 -- kernel I space DR segment 4 (base 100000)
|
5402 |
|
|
wmi 077406 -- slf=127; ed=0(up); acf=6 (r/w)
|
5403 |
|
|
#
|
5404 |
|
|
C test 44.39: cmode=10 will cause abort {70,J11}, treated as kmode {23,24}
|
5405 |
|
|
#
|
5406 |
|
|
wal 177572 -- SSR0
|
5407 |
|
|
wmi 000001 -- set enable bit
|
5408 |
|
|
wr1 001400 -- r1=1400
|
5409 |
|
|
wsp 001400 -- sp=1400
|
5410 |
|
|
wps 100000 -- psw: set cm=10, pm=00
|
5411 |
|
|
wpc 013042 -- pc=13042
|
5412 |
|
|
step -- step (inc (r1)+) [[s:2]]
|
5413 |
|
|
rpc d=000252 -- ! pc=252 ; trap 250; as expected for 11/70 [[s:254]]
|
5414 |
|
|
rsp d=001374 -- ! sp=1374
|
5415 |
|
|
rr1 d=001400 -- ! r1=1400
|
5416 |
|
|
wal 177572 -- check SSR0/1
|
5417 |
|
|
brm 3
|
5418 |
|
|
d=140101 -- ! SSR0: (abo_nr=1,abo_l=1,m=10,seg=0,ena=1) [[s:140301]]
|
5419 |
|
|
d=000000 -- ! SSR1: ra=none
|
5420 |
|
|
d=013042 -- ! SSR2: PC of failed instruction
|
5421 |
|
|
wal 001374 -- check stack
|
5422 |
|
|
brm 2
|
5423 |
|
|
d=013044 -- ! PC after failed instruction [[s:013042]]
|
5424 |
|
|
d=100000 -- ! PS
|
5425 |
|
|
rst -- console reset (to clear CPUERR reg, PSW)
|
5426 |
|
|
#
|
5427 |
|
|
# simh notes:
|
5428 |
|
|
# 1. simh saves PC of failed instruction on stack, not PC after instruction
|
5429 |
|
|
#
|
5430 |
|
|
C test 44.43: user mode HALT: trap 4 {70} or 10 {others}
|
5431 |
|
|
#
|
5432 |
|
|
wal 177766 -- check CPUERR ;??? remove if console reset fixed
|
5433 |
|
|
wm 000000 -- clear
|
5434 |
|
|
wsp 001400 -- sp=1400
|
5435 |
|
|
wps 170000 -- psw: set cm=11, pm=11
|
5436 |
|
|
wpc 013022 -- pc=13022
|
5437 |
|
|
step -- step (halt in user mode) [[s:2]]
|
5438 |
|
|
rpc d=000006 -- ! pc=6 ; trap 4; as expected for 11/70 [[s:10]]
|
5439 |
|
|
rsp d=001374 -- ! sp=1374
|
5440 |
|
|
wal 001374 -- check stack
|
5441 |
|
|
brm 2
|
5442 |
|
|
d=013024 -- ! PC after failed instruction
|
5443 |
|
|
d=170000 -- ! PS
|
5444 |
|
|
wal 177766 -- check CPUERR
|
5445 |
|
|
rm d=000200 -- ! CPUERR: (illhalt=1)
|
5446 |
|
|
rst -- console reset (to clear CPUERR reg, PSW)
|
5447 |
|
|
#
|
5448 |
|
|
C test 44.44: PDR bit<0> implemented {70} or not {others}
|
5449 |
|
|
#
|
5450 |
|
|
wal 172310 -- kernel I space DR, segment 4
|
5451 |
|
|
wm 077401 -- set acf bit 0: slf=127; ed=0(up); acf=1 (r+trap)
|
5452 |
|
|
rm d=077401 -- ! check; works as expected for 11/70
|
5453 |
|
|
wm 077406 -- restore: slf=127; ed=0(up); acf=6(w/r)
|
5454 |
|
|
#
|
5455 |
|
|
C test 44.45: PDR bit<7>(AIB any access) implemented {70} or not {others}
|
5456 |
|
|
#
|
5457 |
|
|
wal 172300 -- kernel I space DR, reset segment 0 and 1
|
5458 |
|
|
bwm 2
|
5459 |
|
|
077404 -- slf=127; ed=0(up); acf=4(w/r and trap)
|
5460 |
|
|
077404 -- slf=127; ed=0(up); acf=4(w/r and trap)
|
5461 |
|
|
wal 172300 -- check kernel I space DR, segment 0 and 1
|
5462 |
|
|
brm 2
|
5463 |
|
|
d=077404 -- !
|
5464 |
|
|
d=077404 -- !
|
5465 |
|
|
wal 177572 -- SSR0
|
5466 |
|
|
wmi 000001 -- set enable bit
|
5467 |
|
|
wr0 123456 -- r0=123456
|
5468 |
|
|
wr1 030000 -- r1=30000
|
5469 |
|
|
wsp 001400 -- sp=1400
|
5470 |
|
|
wpc 013030 -- pc=13030
|
5471 |
|
|
step -- step (mov r0,(r1))
|
5472 |
|
|
rpc d=013032 -- ! pc=next
|
5473 |
|
|
rsp d=001400 -- ! sp=1400
|
5474 |
|
|
wal 030000 -- check target memory, untaint
|
5475 |
|
|
rm d=123456 -- !
|
5476 |
|
|
wm 000000 --
|
5477 |
|
|
wal 172300 -- check kernel I space DR, segment 0 and 1
|
5478 |
|
|
brm 2
|
5479 |
|
|
d=077604 -- ! slf=127; ed=0(up); acf=4(w/r+trap); aib=10 (A=1,W=0)
|
5480 |
|
|
d=077704 -- ! slf=127; ed=0(up); acf=4(w/r+trap); aib=11 (A=1,W=1)
|
5481 |
|
|
wal 172300 -- kernel I space DR, reset segment 0 and 1
|
5482 |
|
|
bwm 2
|
5483 |
|
|
077406 -- slf=127; ed=0(up); acf=6(w/r)
|
5484 |
|
|
077406 -- slf=127; ed=0(up); acf=6(w/r)
|
5485 |
|
|
rst -- console reset (to clear CPUERR reg)
|
5486 |
|
|
#
|
5487 |
|
|
C test 44.46: Full PAR implemented {44,70,J11} or not {others}
|
5488 |
|
|
#
|
5489 |
|
|
wal 172350 -- kernel I space AR, segment 4
|
5490 |
|
|
wm 177777 -- set all bits
|
5491 |
|
|
rm d=177777 -- ! check; works as expected for 11/70
|
5492 |
|
|
wm 001000 -- restore: 1000 100000 base
|
5493 |
|
|
#
|
5494 |
|
|
C test 44.47: MMR0<9>(mmu trap) implemented {70} or not {others}
|
5495 |
|
|
#
|
5496 |
|
|
wal 177572 -- SSR0
|
5497 |
|
|
wm 001000 -- set trap enable
|
5498 |
|
|
rm d=001000 -- ! check; works as expected for 11/70
|
5499 |
|
|
wm 000000 -- restore
|
5500 |
|
|
#
|
5501 |
|
|
C test 44.48: MMR3<2:0>(D space) implemented {44,70,J11} or not {others}
|
5502 |
|
|
#
|
5503 |
|
|
wal 172516 -- SSR3
|
5504 |
|
|
wm 000007 -- set D space bis
|
5505 |
|
|
rm d=000007 -- ! check; works as expected for 11/70
|
5506 |
|
|
wm 000000 -- restore
|
5507 |
|
|
#
|
5508 |
|
|
C test 44.49: MMR3<5:4>(UMAP, 22 bit) implemented {44,70,J11} or not {others}
|
5509 |
|
|
#
|
5510 |
|
|
wal 172516 -- SSR3
|
5511 |
|
|
wm 000060 -- set D space bits
|
5512 |
|
|
rm d=000060 -- ! check; available, as expected for 11/70
|
5513 |
|
|
wm 000000 -- restore
|
5514 |
|
|
#
|
5515 |
|
|
C test 44.50: MMR3<3>(CSM enable) implemented {44,J11} or not {others}
|
5516 |
|
|
#
|
5517 |
|
|
wal 172516 -- SSR3
|
5518 |
|
|
wm 000010 -- set D space bit
|
5519 |
|
|
rm d=000000 -- ! check; not available, as expected for 11/70
|
5520 |
|
|
wm 000000 -- restore
|
5521 |
|
|
#
|
5522 |
|
|
C test 44.51: MMR2 tracks fetches {70} or instructions only {others}
|
5523 |
|
|
C here W11 behaves like {others}, fetches are not tracked in SSR2
|
5524 |
|
|
C Also: instruction complete flag set in SSR0 after bpt.
|
5525 |
|
|
#
|
5526 |
|
|
wal 177572 -- SSR0
|
5527 |
|
|
wmi 000001 -- set enable bit
|
5528 |
|
|
wsp 001400 -- sp=1400
|
5529 |
|
|
wpc 013052 -- pc=13052
|
5530 |
|
|
step -- step (bpt)
|
5531 |
|
|
rpc d=000016 -- ! pc=16; trap 14 see note [[s:13054]]
|
5532 |
|
|
wal 177572 -- check SSR0/1/2
|
5533 |
|
|
brm 3
|
5534 |
|
|
d=000001 -- ! SSR0: (ena=1)
|
5535 |
|
|
d=000000 -- ! SSR1: ra=none
|
5536 |
|
|
d=013052 -- ! SSR2: PC of bpt
|
5537 |
|
|
step -- step (halt)
|
5538 |
|
|
rpc d=000020 -- ! pc=20 (after halt)
|
5539 |
|
|
wal 177572 -- check SSR0/1/2
|
5540 |
|
|
brm 3
|
5541 |
|
|
d=000001 -- ! SSR0: (ena=1)
|
5542 |
|
|
d=000000 -- ! SSR1: ra=none
|
5543 |
|
|
d=000016 -- ! SSR2: PC of halt
|
5544 |
|
|
rst -- console reset (to clear CPUERR reg, PSW)
|
5545 |
|
|
#
|
5546 |
|
|
# simh notes:
|
5547 |
|
|
# 1. when simh steps over a BPT,IOT,..., the PC is pointing after the
|
5548 |
|
|
# instruction. The trap sequence together with first instruction is
|
5549 |
|
|
# executed in next step.
|
5550 |
|
|
#
|
5551 |
|
|
C test 44.52: MT/FPx SP for pmode=10 unpredictable {others} / user SP {J11}
|
5552 |
|
|
# write registers
|
5553 |
|
|
#
|
5554 |
|
|
wr0 000001 -- set r0,..,r7
|
5555 |
|
|
wr1 000101 --
|
5556 |
|
|
wr2 000201 --
|
5557 |
|
|
wr3 000301 --
|
5558 |
|
|
wr4 000401 --
|
5559 |
|
|
wr5 000501 --
|
5560 |
|
|
wsp 001400 --
|
5561 |
|
|
wpc 000701 --
|
5562 |
|
|
# write register set 1, sm,um stack
|
5563 |
|
|
#
|
5564 |
|
|
wps 004000 -- psw: cm=kernel, set=1
|
5565 |
|
|
wr0 010001 -- set r0,..,r5 [[r10]]
|
5566 |
|
|
wr1 010101 -- [[r11]]
|
5567 |
|
|
wr2 010201 -- [[r12]]
|
5568 |
|
|
wr3 010301 -- [[r13]]
|
5569 |
|
|
wr4 010401 -- [[r14]]
|
5570 |
|
|
wr5 010501 -- [[r15]]
|
5571 |
|
|
wps 044000 -- psw: cm=super(01),set=1
|
5572 |
|
|
wsp 010601 -- set ssp [[ssp]]
|
5573 |
|
|
wps 144000 -- psw: cm=user(11),set=1
|
5574 |
|
|
wsp 110601 -- set usp [[usp]]
|
5575 |
|
|
#
|
5576 |
|
|
C 52a: MFPS for pmode=10
|
5577 |
|
|
#
|
5578 |
|
|
wps 020000 -- psw: set cm=00, pm=10
|
5579 |
|
|
wpc 013046 -- pc=13046
|
5580 |
|
|
step -- step (mfpd sp)
|
5581 |
|
|
rpc d=013050 -- ! pc=next
|
5582 |
|
|
rsp d=001376 -- ! sp=1376
|
5583 |
|
|
wal 001376 -- check stack
|
5584 |
|
|
rmi d=013046 -- ! it returns PC like 11/70 unpredictable [[s:0]]
|
5585 |
|
|
rst -- console reset (to clear CPUERR reg)
|
5586 |
|
|
#
|
5587 |
|
|
# simh note:
|
5588 |
|
|
# 1. simh returns 0 here, just unpredictable in a different way ...
|
5589 |
|
|
#
|
5590 |
|
|
C 52a: MTPS for pmode=10
|
5591 |
|
|
#
|
5592 |
|
|
wal 001376 -- setup stack with value for mtpd
|
5593 |
|
|
wmi 123446 --
|
5594 |
|
|
wps 020000 -- psw: set cm=00, pm=10
|
5595 |
|
|
wpc 013050 -- pc=13050
|
5596 |
|
|
step -- step (mtpd sp)
|
5597 |
|
|
rpc d=013052 -- ! pc=next
|
5598 |
|
|
rsp d=001400 -- ! sp=1400
|
5599 |
|
|
# check registers
|
5600 |
|
|
#
|
5601 |
|
|
rr0 d=000001 -- ! r0,..,r7
|
5602 |
|
|
rr1 d=000101 -- !
|
5603 |
|
|
rr2 d=000201 -- !
|
5604 |
|
|
rr3 d=000301 -- !
|
5605 |
|
|
rr4 d=000401 -- !
|
5606 |
|
|
rr5 d=000501 -- !
|
5607 |
|
|
# check register set 1, sm,um stack
|
5608 |
|
|
#
|
5609 |
|
|
wps 004000 -- psw: cm=kernel, set=1
|
5610 |
|
|
rr0 d=010001 -- ! r0,..,r5 [[r10]]
|
5611 |
|
|
rr1 d=010101 -- ! [[r11]]
|
5612 |
|
|
rr2 d=010201 -- ! [[r12]]
|
5613 |
|
|
rr3 d=010301 -- ! [[r13]]
|
5614 |
|
|
rr4 d=010401 -- ! [[r14]]
|
5615 |
|
|
rr5 d=010501 -- ! [[r15]]
|
5616 |
|
|
wps 044000 -- psw: cm=super(01),set=1
|
5617 |
|
|
rsp d=010601 -- ! ssp [[ssp]]
|
5618 |
|
|
wps 144000 -- psw: cm=user(11),set=1
|
5619 |
|
|
rsp d=110601 -- ! usp [[usp]]
|
5620 |
|
|
# --> all preset values intact; -> mtpd thus noop --> like 11/70 unpredictable
|
5621 |
|
|
#
|
5622 |
|
|
rst -- console reset (to clear CPUERR reg)
|
5623 |
|
|
#
|
5624 |
|
|
# simh notes on MMR0:
|
5625 |
|
|
# 1. simh doesn't freeze MMR0 bit 7, the instr.compl. bit is set again after
|
5626 |
|
|
# executing first instruction of trap handler.
|
5627 |
|
|
#
|
5628 |
|
|
#-----------------------------------------------------------------------------
|
5629 |
|
|
C Setup code 45 [base 13100] (mmr1 and instructions with implicit stack push/pop
|
5630 |
|
|
#
|
5631 |
|
|
wal 013100 -- code: (to be single stepped mostly)
|
5632 |
|
|
bwm 5
|
5633 |
|
|
106621 -- mtpd (r1)+
|
5634 |
|
|
106521 -- mfpd (r1)+
|
5635 |
|
|
004721 -- jsr pc,(r1)+
|
5636 |
|
|
000000 -- halt
|
5637 |
|
|
#13110
|
5638 |
|
|
000207 -- rts pc
|
5639 |
|
|
#-----
|
5640 |
|
|
C Exec code 45 (mmr1 and instructions with implicit stack push/pop)
|
5641 |
|
|
C test 45.1: mtpd (r1)+
|
5642 |
|
|
#
|
5643 |
|
|
wal 177572 -- SSR0
|
5644 |
|
|
wmi 000001 -- set enable bit
|
5645 |
|
|
wal 001376 -- setup stack with value for mtpd
|
5646 |
|
|
wmi 123456 --
|
5647 |
|
|
wr1 030000 -- r1=30000
|
5648 |
|
|
wsp 001376 -- sp=1376
|
5649 |
|
|
wpc 013100 -- pc=13100
|
5650 |
|
|
step -- step (mtpd (r1)+)
|
5651 |
|
|
rpc d=013102 -- ! pc=next
|
5652 |
|
|
rsp d=001400 -- ! sp=1400
|
5653 |
|
|
rr1 d=030002 -- ! r1=30002
|
5654 |
|
|
wal 177572 -- check SSR0/1/2
|
5655 |
|
|
brm 3
|
5656 |
|
|
d=000003 -- ! SSR0: (seg=1,ena=1)
|
5657 |
|
|
d=010426 -- ! SSR1: rb=1,2; ra=6,2
|
5658 |
|
|
d=013100 -- ! SSR2: PC of mtpd
|
5659 |
|
|
wal 030000 -- check target memory
|
5660 |
|
|
rm d=123456 -- !
|
5661 |
|
|
rst -- console reset
|
5662 |
|
|
#
|
5663 |
|
|
C test 45.2: mfpd (r1)+
|
5664 |
|
|
#
|
5665 |
|
|
wal 177572 -- SSR0
|
5666 |
|
|
wmi 000001 -- set enable bit
|
5667 |
|
|
wr1 030000 -- r1=30000
|
5668 |
|
|
wsp 001400 -- sp=1400
|
5669 |
|
|
wpc 013102 -- pc=13102
|
5670 |
|
|
step -- step (mfpd (r1)+)
|
5671 |
|
|
rpc d=013104 -- ! pc=next
|
5672 |
|
|
rsp d=001376 -- ! sp=1376
|
5673 |
|
|
rr1 d=030002 -- ! r1=30002
|
5674 |
|
|
wal 177572 -- check SSR0/1/2
|
5675 |
|
|
brm 3
|
5676 |
|
|
d=000001 -- ! SSR0: (seg=0,ena=1)
|
5677 |
|
|
d=173021 -- ! SSR1: rb=6,-2; ra=1,2
|
5678 |
|
|
d=013102 -- ! SSR2: PC of mtpd
|
5679 |
|
|
wal 001376 -- check stack
|
5680 |
|
|
rmi d=123456 -- !
|
5681 |
|
|
wal 030000 -- clear tainted target memory
|
5682 |
|
|
wm 000000 --
|
5683 |
|
|
rst -- console reset
|
5684 |
|
|
#
|
5685 |
|
|
C test 45.3: jsr pc,(r1)+ and rts pc
|
5686 |
|
|
#
|
5687 |
|
|
wal 177572 -- SSR0
|
5688 |
|
|
wmi 000001 -- set enable bit
|
5689 |
|
|
wr1 013110 -- r1=13110
|
5690 |
|
|
wsp 001400 -- sp=1400
|
5691 |
|
|
wpc 013104 -- pc=13104
|
5692 |
|
|
step -- step (jsr pc,(r1)+)
|
5693 |
|
|
rpc d=013110 -- ! pc=target
|
5694 |
|
|
rsp d=001376 -- ! sp=1376
|
5695 |
|
|
rr1 d=013112 -- ! r1=13112
|
5696 |
|
|
wal 177572 -- check SSR0/1/2
|
5697 |
|
|
brm 3
|
5698 |
|
|
d=000001 -- ! SSR0: (seg=0,ena=1)
|
5699 |
|
|
d=173021 -- ! SSR1: rb=6,-2; ra=1,2
|
5700 |
|
|
d=013104 -- ! SSR2: PC of jsr
|
5701 |
|
|
wal 001376 -- check stack
|
5702 |
|
|
rmi d=013106 -- ! PC after jsr
|
5703 |
|
|
step -- step (rts pc)
|
5704 |
|
|
rpc d=013106 -- ! pc=target
|
5705 |
|
|
rsp d=001400 -- ! sp=1400
|
5706 |
|
|
wal 177572 -- check SSR0/1/2
|
5707 |
|
|
brm 3
|
5708 |
|
|
d=000001 -- ! SSR0: (seg=0,ena=1)
|
5709 |
|
|
d=000026 -- ! SSR1: ra=6,2 [[s:0]]
|
5710 |
|
|
d=013110 -- ! SSR2: PC of rts
|
5711 |
|
|
rst -- console reset
|
5712 |
|
|
#
|
5713 |
|
|
# simh notes:
|
5714 |
|
|
# 1. simh reads stack and incremets sp later. In case of an MMU abort on
|
5715 |
|
|
# stack read, simh SSR1 will be 0, while W11 shows the sp increment
|
5716 |
|
|
#
|
5717 |
|
|
#-----------------------------------------------------------------------------
|
5718 |
|
|
C Setup code 46 [base 13200] (systematic result+cc test of 1+2op instructions)
|
5719 |
|
|
# the following codes expect:
|
5720 |
|
|
# r0-> psw
|
5721 |
|
|
# r1-> loop count
|
5722 |
|
|
# r2-> input ptr
|
5723 |
|
|
# r3-> output ptr
|
5724 |
|
|
# r4-> src reg
|
5725 |
|
|
# r5-> dst reg
|
5726 |
|
|
#
|
5727 |
|
|
wal 013200 -- code 1: test 1op register
|
5728 |
|
|
bwm 8
|
5729 |
|
|
000230 -- spl 0
|
5730 |
|
|
012205 -- L1: mov (r2)+,r5 ; load dst
|
5731 |
|
|
000000 -- halt ; ccmov set cc's
|
5732 |
|
|
000000 -- halt ; iut instr. under test
|
5733 |
|
|
011023 -- mov (r0),(r3)+ ; save psw
|
5734 |
|
|
010523 -- mov r5,(r3)+ ; save dst
|
5735 |
|
|
077106 -- sob r1,L1 (.-6)
|
5736 |
|
|
000000 -- halt
|
5737 |
|
|
#----
|
5738 |
|
|
wal 013220 -- code 2: test 1op memory
|
5739 |
|
|
bwm 8
|
5740 |
|
|
000230 -- spl 0
|
5741 |
|
|
012215 -- L1: mov (r2)+,(r5) ; load dst
|
5742 |
|
|
000000 -- halt ; ccmov set cc's
|
5743 |
|
|
000000 -- halt ; iut instr. under test
|
5744 |
|
|
011023 -- mov (r0),(r3)+ ; save psw
|
5745 |
|
|
011523 -- mov (r5),(r3)+ ; save dst
|
5746 |
|
|
077106 -- sob r1,L1 (.-6)
|
5747 |
|
|
000000 -- halt
|
5748 |
|
|
#-----
|
5749 |
|
|
wal 013240 -- code 3: test 2op register
|
5750 |
|
|
bwm 9
|
5751 |
|
|
000230 -- spl 0
|
5752 |
|
|
012204 -- L1: mov (r2)+,r4 ; load src
|
5753 |
|
|
012205 -- mov (r2)+,r5 ; load dst
|
5754 |
|
|
000000 -- halt ; ccmov set cc's
|
5755 |
|
|
000000 -- halt ; iut instr. under test
|
5756 |
|
|
011023 -- mov (r0),(r3)+ ; save psw
|
5757 |
|
|
010523 -- mov r5,(r3)+ ; save dst
|
5758 |
|
|
077107 -- sob r1,L1 (.-7)
|
5759 |
|
|
#13260
|
5760 |
|
|
000000 -- halt
|
5761 |
|
|
#-----
|
5762 |
|
|
wal 013270 -- code 4: test 2op memory
|
5763 |
|
|
bwm 9
|
5764 |
|
|
000230 -- spl 0
|
5765 |
|
|
012214 -- L1: mov (r2)+,(r4) ; load src
|
5766 |
|
|
012215 -- mov (r2)+,(r5) ; load dst
|
5767 |
|
|
000000 -- halt ; ccmov set cc's
|
5768 |
|
|
#13300
|
5769 |
|
|
000000 -- halt ; iut instr. under test
|
5770 |
|
|
011023 -- mov (r0),(r3)+ ; save psw
|
5771 |
|
|
011523 -- mov (r5),(r3)+ ; save dst
|
5772 |
|
|
077107 -- sob r1,L1 (.-7)
|
5773 |
|
|
000000 -- halt
|
5774 |
|
|
#----
|
5775 |
|
|
C Exec code 46 pass 1 (systematic result+cc test of 1+2op instructions; word)
|
5776 |
|
|
C Exec test 46.1wr: COM - reg
|
5777 |
|
|
#
|
5778 |
|
|
wal 036000 -- setup test vector: for com,inc,dec,neg,adc,sbc,tst
|
5779 |
|
|
bwm 5
|
5780 |
|
|
000000 -- com 000000
|
5781 |
|
|
000001 -- com 000001
|
5782 |
|
|
077777 -- com 077777
|
5783 |
|
|
100000 -- com 100000
|
5784 |
|
|
177777 -- com 177777
|
5785 |
|
|
wal 013204 -- setup test instructions:
|
5786 |
|
|
bwm 2
|
5787 |
|
|
000241 -- ccmov= clc
|
5788 |
|
|
005105 -- iut= com r5
|
5789 |
|
|
wr0 177776 -- r0=177776
|
5790 |
|
|
wr1 000005 -- r1=5
|
5791 |
|
|
wr2 036000 -- r2=36000
|
5792 |
|
|
wr3 037000 -- r3=37000
|
5793 |
|
|
wr4 000000 -- r4=0
|
5794 |
|
|
wr5 000000 -- r5=0
|
5795 |
|
|
wsp 001400 -- sp=1400
|
5796 |
|
|
stapc 013200 -- start @ 13200 (1op reg)
|
5797 |
|
|
wtgo
|
5798 |
|
|
rpc d=013220 -- ! pc=halt
|
5799 |
|
|
rr1 d=000000 -- ! r1=0
|
5800 |
|
|
wal 037000 -- check result area
|
5801 |
|
|
brm 10
|
5802 |
|
|
d=000011 -- ! com 000000 -> n1z0v0c1; 177777
|
5803 |
|
|
d=177777 -- !
|
5804 |
|
|
d=000011 -- ! com 000001 -> n1z0v0c1; 177776
|
5805 |
|
|
d=177776 -- !
|
5806 |
|
|
d=000011 -- ! com 077777 -> n1z0v0c1; 100000
|
5807 |
|
|
d=100000 -- !
|
5808 |
|
|
d=000001 -- ! com 100000 -> n0z0v0c1; 077777
|
5809 |
|
|
d=077777 -- !
|
5810 |
|
|
d=000005 -- ! com 177777 -> n0z1v0c1; 000000
|
5811 |
|
|
d=000000 -- !
|
5812 |
|
|
#--------
|
5813 |
|
|
C Exec test 46.1wm: COM - mem
|
5814 |
|
|
#
|
5815 |
|
|
wal 013224 -- setup test instructions:
|
5816 |
|
|
bwm 2
|
5817 |
|
|
000241 -- ccmov= clc
|
5818 |
|
|
005115 -- iut= com (r5)
|
5819 |
|
|
wr0 177776 -- r0=177776
|
5820 |
|
|
wr1 000005 -- r1=5
|
5821 |
|
|
wr2 036000 -- r2=36000
|
5822 |
|
|
wr3 037000 -- r3=37000
|
5823 |
|
|
wr4 001400 -- r4=1400
|
5824 |
|
|
wr5 001402 -- r5=1402
|
5825 |
|
|
wsp 001400 -- sp=1400
|
5826 |
|
|
stapc 013220 -- start @ 13220 (1op mem)
|
5827 |
|
|
wtgo
|
5828 |
|
|
rpc d=013240 -- ! pc=halt
|
5829 |
|
|
rr1 d=000000 -- ! r1=0
|
5830 |
|
|
wal 037000 -- check result area
|
5831 |
|
|
brm 10
|
5832 |
|
|
d=000011 -- ! com 000000 -> n1z0v0c1; 177777
|
5833 |
|
|
d=177777 -- !
|
5834 |
|
|
d=000011 -- ! com 000001 -> n1z0v0c1; 177776
|
5835 |
|
|
d=177776 -- !
|
5836 |
|
|
d=000011 -- ! com 077777 -> n1z0v0c1; 100000
|
5837 |
|
|
d=100000 -- !
|
5838 |
|
|
d=000001 -- ! com 100000 -> n0z0v0c1; 077777
|
5839 |
|
|
d=077777 -- !
|
5840 |
|
|
d=000005 -- ! com 177777 -> n0z1v0c1; 000000
|
5841 |
|
|
d=000000 -- !
|
5842 |
|
|
#--------
|
5843 |
|
|
C Exec test 46.2wrc0: INC - reg,C=0
|
5844 |
|
|
#
|
5845 |
|
|
wal 013204 -- setup test instructions:
|
5846 |
|
|
bwm 2
|
5847 |
|
|
000241 -- ccmov= clc
|
5848 |
|
|
005205 -- iut= inc r5
|
5849 |
|
|
wr0 177776 -- r0=177776
|
5850 |
|
|
wr1 000005 -- r1=5
|
5851 |
|
|
wr2 036000 -- r2=36000
|
5852 |
|
|
wr3 037000 -- r3=37000
|
5853 |
|
|
wr4 000000 -- r4=0
|
5854 |
|
|
wr5 000000 -- r5=0
|
5855 |
|
|
wsp 001400 -- sp=1400
|
5856 |
|
|
stapc 013200 -- start @ 13200 (1op reg)
|
5857 |
|
|
wtgo
|
5858 |
|
|
rpc d=013220 -- ! pc=halt
|
5859 |
|
|
rr1 d=000000 -- ! r1=0
|
5860 |
|
|
wal 037000 -- check result area
|
5861 |
|
|
brm 10
|
5862 |
|
|
d=000000 -- ! inc 000000 -> n0z0v0c0; 000001
|
5863 |
|
|
d=000001 -- !
|
5864 |
|
|
d=000000 -- ! inc 000001 -> n0z0v0c0; 000002
|
5865 |
|
|
d=000002 -- !
|
5866 |
|
|
d=000012 -- ! inc 077777 -> n1z0v1c0; 100000
|
5867 |
|
|
d=100000 -- !
|
5868 |
|
|
d=000010 -- ! inc 100000 -> n1z0v0c0; 100001
|
5869 |
|
|
d=100001 -- !
|
5870 |
|
|
d=000004 -- ! inc 177777 -> n0z1v0c0; 000000
|
5871 |
|
|
d=000000 -- !
|
5872 |
|
|
#--------
|
5873 |
|
|
C Exec test 46.2wrc1: INC - reg,C=1
|
5874 |
|
|
#
|
5875 |
|
|
wal 013204 -- setup test instructions:
|
5876 |
|
|
bwm 2
|
5877 |
|
|
000261 -- ccmov= sec
|
5878 |
|
|
005205 -- iut= inc r5
|
5879 |
|
|
wr0 177776 -- r0=177776
|
5880 |
|
|
wr1 000005 -- r1=5
|
5881 |
|
|
wr2 036000 -- r2=36000
|
5882 |
|
|
wr3 037000 -- r3=37000
|
5883 |
|
|
wr4 000000 -- r4=0
|
5884 |
|
|
wr5 000000 -- r5=0
|
5885 |
|
|
wsp 001400 -- sp=1400
|
5886 |
|
|
stapc 013200 -- start @ 13200 (1op reg)
|
5887 |
|
|
wtgo
|
5888 |
|
|
rpc d=013220 -- ! pc=halt
|
5889 |
|
|
rr1 d=000000 -- ! r1=0
|
5890 |
|
|
wal 037000 -- check result area
|
5891 |
|
|
brm 10
|
5892 |
|
|
d=000001 -- ! inc 000000 -> n0z0v0c1; 000001
|
5893 |
|
|
d=000001 -- !
|
5894 |
|
|
d=000001 -- ! inc 000001 -> n0z0v0c1; 000002
|
5895 |
|
|
d=000002 -- !
|
5896 |
|
|
d=000013 -- ! inc 077777 -> n1z0v1c1; 100000
|
5897 |
|
|
d=100000 -- !
|
5898 |
|
|
d=000011 -- ! inc 100000 -> n1z0v0c1; 100001
|
5899 |
|
|
d=100001 -- !
|
5900 |
|
|
d=000005 -- ! inc 177777 -> n0z1v0c1; 000000
|
5901 |
|
|
d=000000 -- !
|
5902 |
|
|
#--------
|
5903 |
|
|
C Exec test 46.3wrc0: DEC - reg,C=0
|
5904 |
|
|
#
|
5905 |
|
|
wal 013204 -- setup test instructions:
|
5906 |
|
|
bwm 2
|
5907 |
|
|
000241 -- ccmov= clc
|
5908 |
|
|
005305 -- iut= dec r5
|
5909 |
|
|
wr0 177776 -- r0=177776
|
5910 |
|
|
wr1 000005 -- r1=5
|
5911 |
|
|
wr2 036000 -- r2=36000
|
5912 |
|
|
wr3 037000 -- r3=37000
|
5913 |
|
|
wr4 000000 -- r4=0
|
5914 |
|
|
wr5 000000 -- r5=0
|
5915 |
|
|
wsp 001400 -- sp=1400
|
5916 |
|
|
stapc 013200 -- start @ 13200 (1op reg)
|
5917 |
|
|
wtgo
|
5918 |
|
|
rpc d=013220 -- ! pc=halt
|
5919 |
|
|
rr1 d=000000 -- ! r1=0
|
5920 |
|
|
wal 037000 -- check result area
|
5921 |
|
|
brm 10
|
5922 |
|
|
d=000010 -- ! dec 000000 -> n1z0v0c0; 177777
|
5923 |
|
|
d=177777 -- !
|
5924 |
|
|
d=000004 -- ! dec 000001 -> n0z1v0c0; 000000
|
5925 |
|
|
d=000000 -- !
|
5926 |
|
|
d=000000 -- ! dec 077777 -> n0z0v0c0; 077776
|
5927 |
|
|
d=077776 -- !
|
5928 |
|
|
d=000002 -- ! dec 100000 -> n0z0v1c0; 077777
|
5929 |
|
|
d=077777 -- !
|
5930 |
|
|
d=000010 -- ! dec 177777 -> n1z0v0c0; 177776
|
5931 |
|
|
d=177776 -- !
|
5932 |
|
|
#--------
|
5933 |
|
|
C Exec test 46.3wrc1: DEC - reg,C=1
|
5934 |
|
|
#
|
5935 |
|
|
wal 013204 -- setup test instructions:
|
5936 |
|
|
bwm 2
|
5937 |
|
|
000261 -- ccmov= sec
|
5938 |
|
|
005305 -- iut= dec r5
|
5939 |
|
|
wr0 177776 -- r0=177776
|
5940 |
|
|
wr1 000005 -- r1=5
|
5941 |
|
|
wr2 036000 -- r2=36000
|
5942 |
|
|
wr3 037000 -- r3=37000
|
5943 |
|
|
wr4 000000 -- r4=0
|
5944 |
|
|
wr5 000000 -- r5=0
|
5945 |
|
|
wsp 001400 -- sp=1400
|
5946 |
|
|
stapc 013200 -- start @ 13200 (1op reg)
|
5947 |
|
|
wtgo
|
5948 |
|
|
rpc d=013220 -- ! pc=halt
|
5949 |
|
|
rr1 d=000000 -- ! r1=0
|
5950 |
|
|
wal 037000 -- check result area
|
5951 |
|
|
brm 10
|
5952 |
|
|
d=000011 -- ! dec 000000 -> n1z0v0c1; 177777
|
5953 |
|
|
d=177777 -- !
|
5954 |
|
|
d=000005 -- ! dec 000001 -> n0z1v0c1; 000000
|
5955 |
|
|
d=000000 -- !
|
5956 |
|
|
d=000001 -- ! dec 077777 -> n0z0v0c1; 077776
|
5957 |
|
|
d=077776 -- !
|
5958 |
|
|
d=000003 -- ! dec 100000 -> n0z0v1c1; 077777
|
5959 |
|
|
d=077777 -- !
|
5960 |
|
|
d=000011 -- ! dec 177777 -> n1z0v0c1; 177776
|
5961 |
|
|
d=177776 -- !
|
5962 |
|
|
#--------
|
5963 |
|
|
C Exec test 46.4wr: NEG - reg
|
5964 |
|
|
#
|
5965 |
|
|
wal 013204 -- setup test instructions:
|
5966 |
|
|
bwm 2
|
5967 |
|
|
000241 -- ccmov= clc
|
5968 |
|
|
005405 -- iut= neg r5
|
5969 |
|
|
wr0 177776 -- r0=177776
|
5970 |
|
|
wr1 000005 -- r1=5
|
5971 |
|
|
wr2 036000 -- r2=36000
|
5972 |
|
|
wr3 037000 -- r3=37000
|
5973 |
|
|
wr4 000000 -- r4=0
|
5974 |
|
|
wr5 000000 -- r5=0
|
5975 |
|
|
wsp 001400 -- sp=1400
|
5976 |
|
|
stapc 013200 -- start @ 13200 (1op reg)
|
5977 |
|
|
wtgo
|
5978 |
|
|
rpc d=013220 -- ! pc=halt
|
5979 |
|
|
rr1 d=000000 -- ! r1=0
|
5980 |
|
|
wal 037000 -- check result area
|
5981 |
|
|
brm 10
|
5982 |
|
|
d=000004 -- ! neg 000000 -> n0z1v0c0; 000000
|
5983 |
|
|
d=000000 -- !
|
5984 |
|
|
d=000011 -- ! neg 000001 -> n1z0v0c1; 177777
|
5985 |
|
|
d=177777 -- !
|
5986 |
|
|
d=000011 -- ! neg 077777 -> n1z0v0c1; 100001
|
5987 |
|
|
d=100001 -- !
|
5988 |
|
|
d=000013 -- ! neg 100000 -> n1z0v1c1; 100000
|
5989 |
|
|
d=100000 -- !
|
5990 |
|
|
d=000001 -- ! neg 177777 -> n0z0v0c1; 000001
|
5991 |
|
|
d=000001 -- !
|
5992 |
|
|
#--------
|
5993 |
|
|
C Exec test 46.5wrc0: ADC - reg,C=0
|
5994 |
|
|
#
|
5995 |
|
|
wal 013204 -- setup test instructions:
|
5996 |
|
|
bwm 2
|
5997 |
|
|
000241 -- ccmov= clc
|
5998 |
|
|
005505 -- iut= adc r5
|
5999 |
|
|
wr0 177776 -- r0=177776
|
6000 |
|
|
wr1 000005 -- r1=5
|
6001 |
|
|
wr2 036000 -- r2=36000
|
6002 |
|
|
wr3 037000 -- r3=37000
|
6003 |
|
|
wr4 000000 -- r4=0
|
6004 |
|
|
wr5 000000 -- r5=0
|
6005 |
|
|
wsp 001400 -- sp=1400
|
6006 |
|
|
stapc 013200 -- start @ 13200 (1op reg)
|
6007 |
|
|
wtgo
|
6008 |
|
|
rpc d=013220 -- ! pc=halt
|
6009 |
|
|
rr1 d=000000 -- ! r1=0
|
6010 |
|
|
wal 037000 -- check result area
|
6011 |
|
|
brm 10
|
6012 |
|
|
d=000004 -- ! adc 000000 -> n0z1v0c0; 000000
|
6013 |
|
|
d=000000 -- !
|
6014 |
|
|
d=000000 -- ! adc 000001 -> n0z0v0c0; 000001
|
6015 |
|
|
d=000001 -- !
|
6016 |
|
|
d=000000 -- ! adc 077777 -> n0z0v0c0; 077777
|
6017 |
|
|
d=077777 -- !
|
6018 |
|
|
d=000010 -- ! adc 100000 -> n1z0v0c0; 100000
|
6019 |
|
|
d=100000 -- !
|
6020 |
|
|
d=000010 -- ! adc 177777 -> n1z0v0c0; 177777
|
6021 |
|
|
d=177777 -- !
|
6022 |
|
|
#--------
|
6023 |
|
|
C Exec test 46.5wrc1: ADC - reg,C=1
|
6024 |
|
|
#
|
6025 |
|
|
wal 013204 -- setup test instructions:
|
6026 |
|
|
bwm 2
|
6027 |
|
|
000261 -- ccmov= sec
|
6028 |
|
|
005505 -- iut= adc r5
|
6029 |
|
|
wr0 177776 -- r0=177776
|
6030 |
|
|
wr1 000005 -- r1=5
|
6031 |
|
|
wr2 036000 -- r2=36000
|
6032 |
|
|
wr3 037000 -- r3=37000
|
6033 |
|
|
wr4 000000 -- r4=0
|
6034 |
|
|
wr5 000000 -- r5=0
|
6035 |
|
|
wsp 001400 -- sp=1400
|
6036 |
|
|
stapc 013200 -- start @ 13200 (1op reg)
|
6037 |
|
|
wtgo
|
6038 |
|
|
rpc d=013220 -- ! pc=halt
|
6039 |
|
|
rr1 d=000000 -- ! r1=0
|
6040 |
|
|
wal 037000 -- check result area
|
6041 |
|
|
brm 10
|
6042 |
|
|
d=000000 -- ! adc 000000 -> n0z0v0c0; 000001
|
6043 |
|
|
d=000001 -- !
|
6044 |
|
|
d=000000 -- ! adc 000001 -> n0z0v0c0; 000002
|
6045 |
|
|
d=000002 -- !
|
6046 |
|
|
d=000012 -- ! adc 077777 -> n1z0v1c0; 100000
|
6047 |
|
|
d=100000 -- !
|
6048 |
|
|
d=000010 -- ! adc 100000 -> n1z0v0c0; 100001
|
6049 |
|
|
d=100001 -- !
|
6050 |
|
|
d=000005 -- ! adc 177777 -> n0z1v0c1; 000000
|
6051 |
|
|
d=000000 -- !
|
6052 |
|
|
#--------
|
6053 |
|
|
C Exec test 46.6wrc0: SBC - reg,C=0
|
6054 |
|
|
#
|
6055 |
|
|
wal 013204 -- setup test instructions:
|
6056 |
|
|
bwm 2
|
6057 |
|
|
000241 -- ccmov= clc
|
6058 |
|
|
005605 -- iut= sbc r5
|
6059 |
|
|
wr0 177776 -- r0=177776
|
6060 |
|
|
wr1 000005 -- r1=5
|
6061 |
|
|
wr2 036000 -- r2=36000
|
6062 |
|
|
wr3 037000 -- r3=37000
|
6063 |
|
|
wr4 000000 -- r4=0
|
6064 |
|
|
wr5 000000 -- r5=0
|
6065 |
|
|
wsp 001400 -- sp=1400
|
6066 |
|
|
stapc 013200 -- start @ 13200 (1op reg)
|
6067 |
|
|
wtgo
|
6068 |
|
|
rpc d=013220 -- ! pc=halt
|
6069 |
|
|
rr1 d=000000 -- ! r1=0
|
6070 |
|
|
wal 037000 -- check result area
|
6071 |
|
|
brm 10
|
6072 |
|
|
d=000004 -- ! sbc 000000 -> n0z1v0c0; 000000
|
6073 |
|
|
d=000000 -- !
|
6074 |
|
|
d=000000 -- ! sbc 000001 -> n0z0v0c0; 000001
|
6075 |
|
|
d=000001 -- !
|
6076 |
|
|
d=000000 -- ! sbc 077777 -> n0z0v0c0; 077777
|
6077 |
|
|
d=077777 -- !
|
6078 |
|
|
d=000010 -- ! sbc 100000 -> n1z0v0c0; 100000
|
6079 |
|
|
d=100000 -- !
|
6080 |
|
|
d=000010 -- ! sbc 177777 -> n1z0v0c0; 177777
|
6081 |
|
|
d=177777 -- !
|
6082 |
|
|
#--------
|
6083 |
|
|
C Exec test 46.6wrc1: SBC - reg,C=1
|
6084 |
|
|
#
|
6085 |
|
|
wal 013204 -- setup test instructions:
|
6086 |
|
|
bwm 2
|
6087 |
|
|
000261 -- ccmov= sec
|
6088 |
|
|
005605 -- iut= sbc r5
|
6089 |
|
|
wr0 177776 -- r0=177776
|
6090 |
|
|
wr1 000005 -- r1=5
|
6091 |
|
|
wr2 036000 -- r2=36000
|
6092 |
|
|
wr3 037000 -- r3=37000
|
6093 |
|
|
wr4 000000 -- r4=0
|
6094 |
|
|
wr5 000000 -- r5=0
|
6095 |
|
|
wsp 001400 -- sp=1400
|
6096 |
|
|
stapc 013200 -- start @ 13200 (1op reg)
|
6097 |
|
|
wtgo
|
6098 |
|
|
rpc d=013220 -- ! pc=halt
|
6099 |
|
|
rr1 d=000000 -- ! r1=0
|
6100 |
|
|
wal 037000 -- check result area
|
6101 |
|
|
brm 10
|
6102 |
|
|
d=000011 -- ! sbc 000000 -> n1z0v0c1; 177777
|
6103 |
|
|
d=177777 -- !
|
6104 |
|
|
d=000004 -- ! sbc 000001 -> n0z1v0c0; 000000
|
6105 |
|
|
d=000000 -- !
|
6106 |
|
|
d=000000 -- ! sbc 077777 -> n0z0v0c0; 077776
|
6107 |
|
|
d=077776 -- !
|
6108 |
|
|
d=000002 -- ! sbc 100000 -> n0z0v1c0; 077777
|
6109 |
|
|
d=077777 -- !
|
6110 |
|
|
d=000010 -- ! sbc 177777 -> n1z0v0c0; 177776
|
6111 |
|
|
d=177776 -- !
|
6112 |
|
|
#--------
|
6113 |
|
|
C Exec test 46.7wr: TST - reg
|
6114 |
|
|
#
|
6115 |
|
|
wal 013204 -- setup test instructions:
|
6116 |
|
|
bwm 2
|
6117 |
|
|
000261 -- ccmov= sec
|
6118 |
|
|
005705 -- iut= tst r5
|
6119 |
|
|
wr0 177776 -- r0=177776
|
6120 |
|
|
wr1 000005 -- r1=5
|
6121 |
|
|
wr2 036000 -- r2=36000
|
6122 |
|
|
wr3 037000 -- r3=37000
|
6123 |
|
|
wr4 000000 -- r4=0
|
6124 |
|
|
wr5 000000 -- r5=0
|
6125 |
|
|
wsp 001400 -- sp=1400
|
6126 |
|
|
stapc 013200 -- start @ 13200 (1op reg)
|
6127 |
|
|
wtgo
|
6128 |
|
|
rpc d=013220 -- ! pc=halt
|
6129 |
|
|
rr1 d=000000 -- ! r1=0
|
6130 |
|
|
wal 037000 -- check result area
|
6131 |
|
|
brm 10
|
6132 |
|
|
d=000004 -- ! tst 000000 -> n0z1v0c0;
|
6133 |
|
|
d=000000 -- !
|
6134 |
|
|
d=000000 -- ! tst 000001 -> n0z0v0c0;
|
6135 |
|
|
d=000001 -- !
|
6136 |
|
|
d=000000 -- ! tst 077777 -> n0z0v0c0;
|
6137 |
|
|
d=077777 -- !
|
6138 |
|
|
d=000010 -- ! tst 100000 -> n1z0v0c0;
|
6139 |
|
|
d=100000 -- !
|
6140 |
|
|
d=000010 -- ! tst 177777 -> n1z0v0c0;
|
6141 |
|
|
d=177777 -- !
|
6142 |
|
|
#--------
|
6143 |
|
|
C Exec test 46.7wm: TST - mem
|
6144 |
|
|
#
|
6145 |
|
|
wal 013224 -- setup test instructions:
|
6146 |
|
|
bwm 2
|
6147 |
|
|
000261 -- ccmov= sec
|
6148 |
|
|
005715 -- iut= tst (r5)
|
6149 |
|
|
wr0 177776 -- r0=177776
|
6150 |
|
|
wr1 000005 -- r1=5
|
6151 |
|
|
wr2 036000 -- r2=36000
|
6152 |
|
|
wr3 037000 -- r3=37000
|
6153 |
|
|
wr4 001400 -- r4=1400
|
6154 |
|
|
wr5 001402 -- r5=1402
|
6155 |
|
|
wsp 001400 -- sp=1400
|
6156 |
|
|
stapc 013220 -- start @ 13220 (1op mem)
|
6157 |
|
|
wtgo
|
6158 |
|
|
rpc d=013240 -- ! pc=halt
|
6159 |
|
|
rr1 d=000000 -- ! r1=0
|
6160 |
|
|
wal 037000 -- check result area
|
6161 |
|
|
brm 10
|
6162 |
|
|
d=000004 -- ! tst 000000 -> n0z1v0c0;
|
6163 |
|
|
d=000000 -- !
|
6164 |
|
|
d=000000 -- ! tst 000001 -> n0z0v0c0;
|
6165 |
|
|
d=000001 -- !
|
6166 |
|
|
d=000000 -- ! tst 077777 -> n0z0v0c0;
|
6167 |
|
|
d=077777 -- !
|
6168 |
|
|
d=000010 -- ! tst 100000 -> n1z0v0c0;
|
6169 |
|
|
d=100000 -- !
|
6170 |
|
|
d=000010 -- ! tst 177777 -> n1z0v0c0;
|
6171 |
|
|
d=177777 -- !
|
6172 |
|
|
#--------
|
6173 |
|
|
C Exec test 46.8wrc0: ROR - reg, C=0
|
6174 |
|
|
#
|
6175 |
|
|
wal 036000 -- setup test vector: for ror,rol,ars,asl
|
6176 |
|
|
bwm 7
|
6177 |
|
|
000000 -- ror 000000
|
6178 |
|
|
000001 -- ror 000001
|
6179 |
|
|
100000 -- ror 100000
|
6180 |
|
|
000100 -- ror 000100
|
6181 |
|
|
000101 -- ror 000101
|
6182 |
|
|
040100 -- ror 040100
|
6183 |
|
|
100100 -- ror 100100
|
6184 |
|
|
wal 013204 -- setup test instructions:
|
6185 |
|
|
bwm 2
|
6186 |
|
|
000241 -- ccmov= clc
|
6187 |
|
|
006005 -- iut= ror r5
|
6188 |
|
|
wr0 177776 -- r0=177776
|
6189 |
|
|
wr1 000007 -- r1=7
|
6190 |
|
|
wr2 036000 -- r2=36000
|
6191 |
|
|
wr3 037000 -- r3=37000
|
6192 |
|
|
wr4 000000 -- r4=0
|
6193 |
|
|
wr5 000000 -- r5=0
|
6194 |
|
|
wsp 001400 -- sp=1400
|
6195 |
|
|
stapc 013200 -- start @ 13200 (1op reg)
|
6196 |
|
|
wtgo
|
6197 |
|
|
rpc d=013220 -- ! pc=halt
|
6198 |
|
|
rr1 d=000000 -- ! r1=0
|
6199 |
|
|
wal 037000 -- check result area (Note: V = N xor C !)
|
6200 |
|
|
brm 14
|
6201 |
|
|
d=000004 -- ! ror 000000 -> n0z1v0c0; 000000
|
6202 |
|
|
d=000000 -- !
|
6203 |
|
|
d=000007 -- ! ror 000001 -> n0z1v1c1; 000000
|
6204 |
|
|
d=000000 -- !
|
6205 |
|
|
d=000000 -- ! ror 100000 -> n0z0v0c0; 040000
|
6206 |
|
|
d=040000 -- !
|
6207 |
|
|
d=000000 -- ! ror 000100 -> n0z0v0c0; 000040
|
6208 |
|
|
d=000040 -- !
|
6209 |
|
|
d=000003 -- ! ror 000101 -> n0z0v1c1; 000040
|
6210 |
|
|
d=000040 -- !
|
6211 |
|
|
d=000000 -- ! ror 040100 -> n0z0v0c0; 020040
|
6212 |
|
|
d=020040 -- !
|
6213 |
|
|
d=000000 -- ! ror 100100 -> n0z0v0c0; 040040
|
6214 |
|
|
d=040040 -- !
|
6215 |
|
|
#--------
|
6216 |
|
|
C Exec test 46.8wrc1: ROR - reg, C=1
|
6217 |
|
|
#
|
6218 |
|
|
wal 013204 -- setup test instructions:
|
6219 |
|
|
bwm 2
|
6220 |
|
|
000261 -- ccmov= sec
|
6221 |
|
|
006005 -- iut= ror r5
|
6222 |
|
|
wr0 177776 -- r0=177776
|
6223 |
|
|
wr1 000007 -- r1=7
|
6224 |
|
|
wr2 036000 -- r2=36000
|
6225 |
|
|
wr3 037000 -- r3=37000
|
6226 |
|
|
wr4 000000 -- r4=0
|
6227 |
|
|
wr5 000000 -- r5=0
|
6228 |
|
|
wsp 001400 -- sp=1400
|
6229 |
|
|
stapc 013200 -- start @ 13200 (1op reg)
|
6230 |
|
|
wtgo
|
6231 |
|
|
rpc d=013220 -- ! pc=halt
|
6232 |
|
|
rr1 d=000000 -- ! r1=0
|
6233 |
|
|
wal 037000 -- check result area (Note: V = N xor C !)
|
6234 |
|
|
brm 14
|
6235 |
|
|
d=000012 -- ! ror 000000 -> n1z0v1c0; 100000
|
6236 |
|
|
d=100000 -- !
|
6237 |
|
|
d=000011 -- ! ror 000001 -> n1z0v0c1; 100000
|
6238 |
|
|
d=100000 -- !
|
6239 |
|
|
d=000012 -- ! ror 100000 -> n1z0v1c0; 140000
|
6240 |
|
|
d=140000 -- !
|
6241 |
|
|
d=000012 -- ! ror 000100 -> n1z0v1c0; 100040
|
6242 |
|
|
d=100040 -- !
|
6243 |
|
|
d=000011 -- ! ror 000101 -> n1z0v0c1; 100040
|
6244 |
|
|
d=100040 -- !
|
6245 |
|
|
d=000012 -- ! ror 040100 -> n1z0v1c0; 120040
|
6246 |
|
|
d=120040 -- !
|
6247 |
|
|
d=000012 -- ! ror 100100 -> n1z0v1c0; 140040
|
6248 |
|
|
d=140040 -- !
|
6249 |
|
|
#--------
|
6250 |
|
|
C Exec test 46.9wrc0: ROL - reg, C=0
|
6251 |
|
|
#
|
6252 |
|
|
wal 013204 -- setup test instructions:
|
6253 |
|
|
bwm 2
|
6254 |
|
|
000241 -- ccmov= clc
|
6255 |
|
|
006105 -- iut= rol r5
|
6256 |
|
|
wr0 177776 -- r0=177776
|
6257 |
|
|
wr1 000007 -- r1=7
|
6258 |
|
|
wr2 036000 -- r2=36000
|
6259 |
|
|
wr3 037000 -- r3=37000
|
6260 |
|
|
wr4 000000 -- r4=0
|
6261 |
|
|
wr5 000000 -- r5=0
|
6262 |
|
|
wsp 001400 -- sp=1400
|
6263 |
|
|
stapc 013200 -- start @ 13200 (1op reg)
|
6264 |
|
|
wtgo
|
6265 |
|
|
rpc d=013220 -- ! pc=halt
|
6266 |
|
|
rr1 d=000000 -- ! r1=0
|
6267 |
|
|
wal 037000 -- check result area (Note: V = N xor C !)
|
6268 |
|
|
brm 14
|
6269 |
|
|
d=000004 -- ! rol 000000 -> n0z1v0c0; 000000
|
6270 |
|
|
d=000000 -- !
|
6271 |
|
|
d=000000 -- ! rol 000001 -> n0z0v0c0; 000002
|
6272 |
|
|
d=000002 -- !
|
6273 |
|
|
d=000007 -- ! rol 100000 -> n0z1v1c1; 000000
|
6274 |
|
|
d=000000 -- !
|
6275 |
|
|
d=000000 -- ! rol 000100 -> n0z0v0c0; 000200
|
6276 |
|
|
d=000200 -- !
|
6277 |
|
|
d=000000 -- ! rol 000101 -> n0z0v0c0; 000202
|
6278 |
|
|
d=000202 -- !
|
6279 |
|
|
d=000012 -- ! rol 040100 -> n1z0v1c0; 100200
|
6280 |
|
|
d=100200 -- !
|
6281 |
|
|
d=000003 -- ! rol 100100 -> n0z0v1c1; 000200
|
6282 |
|
|
d=000200 -- !
|
6283 |
|
|
#--------
|
6284 |
|
|
C Exec test 46.9wrc1: ROL - reg, C=1
|
6285 |
|
|
#
|
6286 |
|
|
wal 013204 -- setup test instructions:
|
6287 |
|
|
bwm 2
|
6288 |
|
|
000261 -- ccmov= sec
|
6289 |
|
|
006105 -- iut= rol r5
|
6290 |
|
|
wr0 177776 -- r0=177776
|
6291 |
|
|
wr1 000007 -- r1=7
|
6292 |
|
|
wr2 036000 -- r2=36000
|
6293 |
|
|
wr3 037000 -- r3=37000
|
6294 |
|
|
wr4 000000 -- r4=0
|
6295 |
|
|
wr5 000000 -- r5=0
|
6296 |
|
|
wsp 001400 -- sp=1400
|
6297 |
|
|
stapc 013200 -- start @ 13200 (1op reg)
|
6298 |
|
|
wtgo
|
6299 |
|
|
rpc d=013220 -- ! pc=halt
|
6300 |
|
|
rr1 d=000000 -- ! r1=0
|
6301 |
|
|
wal 037000 -- check result area (Note: V = N xor C !)
|
6302 |
|
|
brm 14
|
6303 |
|
|
d=000000 -- ! rol 000000 -> n0z0v0c0; 000001
|
6304 |
|
|
d=000001 -- !
|
6305 |
|
|
d=000000 -- ! rol 000001 -> n0z0v0c0; 000003
|
6306 |
|
|
d=000003 -- !
|
6307 |
|
|
d=000003 -- ! rol 100000 -> n0z0v1c1; 000001
|
6308 |
|
|
d=000001 -- !
|
6309 |
|
|
d=000000 -- ! rol 000100 -> n0z0v0c0; 000201
|
6310 |
|
|
d=000201 -- !
|
6311 |
|
|
d=000000 -- ! rol 000101 -> n0z0v0c0; 000203
|
6312 |
|
|
d=000203 -- !
|
6313 |
|
|
d=000012 -- ! rol 040100 -> n1z0v1c0; 100201
|
6314 |
|
|
d=100201 -- !
|
6315 |
|
|
d=000003 -- ! rol 100100 -> n0z0v1c1; 000201
|
6316 |
|
|
d=000201 -- !
|
6317 |
|
|
#--------
|
6318 |
|
|
C Exec test 46.10wrc0: ASR - reg, C=0
|
6319 |
|
|
#
|
6320 |
|
|
wal 013204 -- setup test instructions:
|
6321 |
|
|
bwm 2
|
6322 |
|
|
000241 -- ccmov= clc
|
6323 |
|
|
006205 -- iut= asr r5
|
6324 |
|
|
wr0 177776 -- r0=177776
|
6325 |
|
|
wr1 000007 -- r1=7
|
6326 |
|
|
wr2 036000 -- r2=36000
|
6327 |
|
|
wr3 037000 -- r3=37000
|
6328 |
|
|
wr4 000000 -- r4=0
|
6329 |
|
|
wr5 000000 -- r5=0
|
6330 |
|
|
wsp 001400 -- sp=1400
|
6331 |
|
|
stapc 013200 -- start @ 13200 (1op reg)
|
6332 |
|
|
wtgo
|
6333 |
|
|
rpc d=013220 -- ! pc=halt
|
6334 |
|
|
rr1 d=000000 -- ! r1=0
|
6335 |
|
|
wal 037000 -- check result area (Note: V = N xor C !)
|
6336 |
|
|
brm 14
|
6337 |
|
|
d=000004 -- ! asr 000000 -> n0z1v0c0; 000000
|
6338 |
|
|
d=000000 -- !
|
6339 |
|
|
d=000007 -- ! asr 000001 -> n0z1v1c1; 000000
|
6340 |
|
|
d=000000 -- !
|
6341 |
|
|
d=000012 -- ! asr 100000 -> n1z0v1c0; 140000
|
6342 |
|
|
d=140000 -- !
|
6343 |
|
|
d=000000 -- ! asr 000100 -> n0z0v0c0; 000040
|
6344 |
|
|
d=000040 -- !
|
6345 |
|
|
d=000003 -- ! asr 000101 -> n0z0v1c1; 000040
|
6346 |
|
|
d=000040 -- !
|
6347 |
|
|
d=000000 -- ! asr 040100 -> n0z0v0c0; 020040
|
6348 |
|
|
d=020040 -- !
|
6349 |
|
|
d=000012 -- ! asr 100100 -> n1z0v1c0; 140040
|
6350 |
|
|
d=140040 -- !
|
6351 |
|
|
#--------
|
6352 |
|
|
C Exec test 46.10wrc1: ASR - reg, C=1
|
6353 |
|
|
#
|
6354 |
|
|
wal 013204 -- setup test instructions:
|
6355 |
|
|
bwm 2
|
6356 |
|
|
000261 -- ccmov= sec
|
6357 |
|
|
006205 -- iut= asr r5
|
6358 |
|
|
wr0 177776 -- r0=177776
|
6359 |
|
|
wr1 000007 -- r1=7
|
6360 |
|
|
wr2 036000 -- r2=36000
|
6361 |
|
|
wr3 037000 -- r3=37000
|
6362 |
|
|
wr4 000000 -- r4=0
|
6363 |
|
|
wr5 000000 -- r5=0
|
6364 |
|
|
wsp 001400 -- sp=1400
|
6365 |
|
|
stapc 013200 -- start @ 13200 (1op reg)
|
6366 |
|
|
wtgo
|
6367 |
|
|
rpc d=013220 -- ! pc=halt
|
6368 |
|
|
rr1 d=000000 -- ! r1=0
|
6369 |
|
|
wal 037000 -- check result area (Note: V = N xor C !)
|
6370 |
|
|
brm 14
|
6371 |
|
|
d=000004 -- ! asr 000000 -> n0z1v0c0; 000000
|
6372 |
|
|
d=000000 -- !
|
6373 |
|
|
d=000007 -- ! asr 000001 -> n0z1v1c1; 000000
|
6374 |
|
|
d=000000 -- !
|
6375 |
|
|
d=000012 -- ! asr 100000 -> n1z0v1c0; 140000
|
6376 |
|
|
d=140000 -- !
|
6377 |
|
|
d=000000 -- ! asr 000100 -> n0z0v0c0; 000040
|
6378 |
|
|
d=000040 -- !
|
6379 |
|
|
d=000003 -- ! asr 000101 -> n0z0v1c1; 000040
|
6380 |
|
|
d=000040 -- !
|
6381 |
|
|
d=000000 -- ! asr 040100 -> n0z0v0c0; 020040
|
6382 |
|
|
d=020040 -- !
|
6383 |
|
|
d=000012 -- ! asr 100100 -> n1z0v1c0; 140040
|
6384 |
|
|
d=140040 -- !
|
6385 |
|
|
#--------
|
6386 |
|
|
C Exec test 46.11wrc0: ASL - reg, C=0
|
6387 |
|
|
#
|
6388 |
|
|
wal 013204 -- setup test instructions:
|
6389 |
|
|
bwm 2
|
6390 |
|
|
000241 -- ccmov= clc
|
6391 |
|
|
006305 -- iut= asl r5
|
6392 |
|
|
wr0 177776 -- r0=177776
|
6393 |
|
|
wr1 000007 -- r1=7
|
6394 |
|
|
wr2 036000 -- r2=36000
|
6395 |
|
|
wr3 037000 -- r3=37000
|
6396 |
|
|
wr4 000000 -- r4=0
|
6397 |
|
|
wr5 000000 -- r5=0
|
6398 |
|
|
wsp 001400 -- sp=1400
|
6399 |
|
|
stapc 013200 -- start @ 13200 (1op reg)
|
6400 |
|
|
wtgo
|
6401 |
|
|
rpc d=013220 -- ! pc=halt
|
6402 |
|
|
rr1 d=000000 -- ! r1=0
|
6403 |
|
|
wal 037000 -- check result area (Note: V = N xor C !)
|
6404 |
|
|
brm 14
|
6405 |
|
|
d=000004 -- ! asl 000000 -> n0z1v0c0; 000000
|
6406 |
|
|
d=000000 -- !
|
6407 |
|
|
d=000000 -- ! asl 000001 -> n0z0v0c0; 000002
|
6408 |
|
|
d=000002 -- !
|
6409 |
|
|
d=000007 -- ! asl 100000 -> n0z1v1c1; 000000
|
6410 |
|
|
d=000000 -- !
|
6411 |
|
|
d=000000 -- ! asl 000100 -> n0z0v0c0; 000200
|
6412 |
|
|
d=000200 -- !
|
6413 |
|
|
d=000000 -- ! asl 000101 -> n0z0v0c0; 000202
|
6414 |
|
|
d=000202 -- !
|
6415 |
|
|
d=000012 -- ! asl 040100 -> n1z0v1c0; 100200
|
6416 |
|
|
d=100200 -- !
|
6417 |
|
|
d=000003 -- ! asl 100100 -> n0z0v1c1; 000200
|
6418 |
|
|
d=000200 -- !
|
6419 |
|
|
#--------
|
6420 |
|
|
C Exec test 46.11wrc1: ASL - reg, C=1
|
6421 |
|
|
#
|
6422 |
|
|
wal 013204 -- setup test instructions:
|
6423 |
|
|
bwm 2
|
6424 |
|
|
000261 -- ccmov= sec
|
6425 |
|
|
006305 -- iut= asl r5
|
6426 |
|
|
wr0 177776 -- r0=177776
|
6427 |
|
|
wr1 000007 -- r1=7
|
6428 |
|
|
wr2 036000 -- r2=36000
|
6429 |
|
|
wr3 037000 -- r3=37000
|
6430 |
|
|
wr4 000000 -- r4=0
|
6431 |
|
|
wr5 000000 -- r5=0
|
6432 |
|
|
wsp 001400 -- sp=1400
|
6433 |
|
|
stapc 013200 -- start @ 13200 (1op reg)
|
6434 |
|
|
wtgo
|
6435 |
|
|
rpc d=013220 -- ! pc=halt
|
6436 |
|
|
rr1 d=000000 -- ! r1=0
|
6437 |
|
|
wal 037000 -- check result area (Note: V = N xor C !)
|
6438 |
|
|
brm 14
|
6439 |
|
|
d=000004 -- ! asl 000000 -> n0z1v0c0; 000000
|
6440 |
|
|
d=000000 -- !
|
6441 |
|
|
d=000000 -- ! asl 000001 -> n0z0v0c0; 000002
|
6442 |
|
|
d=000002 -- !
|
6443 |
|
|
d=000007 -- ! asl 100000 -> n0z1v1c1; 000000
|
6444 |
|
|
d=000000 -- !
|
6445 |
|
|
d=000000 -- ! asl 000100 -> n0z0v0c0; 000200
|
6446 |
|
|
d=000200 -- !
|
6447 |
|
|
d=000000 -- ! asl 000101 -> n0z0v0c0; 000202
|
6448 |
|
|
d=000202 -- !
|
6449 |
|
|
d=000012 -- ! asl 040100 -> n1z0v1c0; 100200
|
6450 |
|
|
d=100200 -- !
|
6451 |
|
|
d=000003 -- ! asl 100100 -> n0z0v1c1; 000200
|
6452 |
|
|
d=000200 -- !
|
6453 |
|
|
#--------
|
6454 |
|
|
C Exec test 46.12wrc0: MOV - reg, C=0
|
6455 |
|
|
#
|
6456 |
|
|
wal 036000 -- setup test vector: for mov
|
6457 |
|
|
bwm 6
|
6458 |
|
|
000000 -- mov 000000,000000
|
6459 |
|
|
000000 --
|
6460 |
|
|
000001 -- mov 000001,000000
|
6461 |
|
|
000000 --
|
6462 |
|
|
100000 -- mov 100000,000000
|
6463 |
|
|
000000 --
|
6464 |
|
|
wal 013246 -- setup test instructions:
|
6465 |
|
|
bwm 2
|
6466 |
|
|
000241 -- ccmov= clc
|
6467 |
|
|
010405 -- iut= mov r4,r5
|
6468 |
|
|
wr0 177776 -- r0=177776
|
6469 |
|
|
wr1 000003 -- r1=3
|
6470 |
|
|
wr2 036000 -- r2=36000
|
6471 |
|
|
wr3 037000 -- r3=37000
|
6472 |
|
|
wr4 000000 -- r4=0
|
6473 |
|
|
wr5 000000 -- r5=0
|
6474 |
|
|
wsp 001400 -- sp=1400
|
6475 |
|
|
stapc 013240 -- start @ 13240 (2op reg)
|
6476 |
|
|
wtgo
|
6477 |
|
|
rpc d=013262 -- ! pc=halt
|
6478 |
|
|
rr1 d=000000 -- ! r1=0
|
6479 |
|
|
wal 037000 -- check result area
|
6480 |
|
|
brm 6
|
6481 |
|
|
d=000004 -- ! mov 000000,000000 -> n0z1v0c0; 000000
|
6482 |
|
|
d=000000 -- !
|
6483 |
|
|
d=000000 -- ! mov 000001,000000 -> n0z0v0c0; 000001
|
6484 |
|
|
d=000001 -- !
|
6485 |
|
|
d=000010 -- ! mov 100000,000000 -> n1z0v0c0; 100000
|
6486 |
|
|
d=100000 -- !
|
6487 |
|
|
#--------
|
6488 |
|
|
C Exec test 46.12wrc1: MOV - reg, C=1
|
6489 |
|
|
#
|
6490 |
|
|
wal 013246 -- setup test instructions:
|
6491 |
|
|
bwm 2
|
6492 |
|
|
000261 -- ccmov= sec
|
6493 |
|
|
010405 -- iut= mov r4,r5
|
6494 |
|
|
wr0 177776 -- r0=177776
|
6495 |
|
|
wr1 000003 -- r1=3
|
6496 |
|
|
wr2 036000 -- r2=36000
|
6497 |
|
|
wr3 037000 -- r3=37000
|
6498 |
|
|
wr4 000000 -- r4=0
|
6499 |
|
|
wr5 000000 -- r5=0
|
6500 |
|
|
wsp 001400 -- sp=1400
|
6501 |
|
|
stapc 013240 -- start @ 13240 (2op reg)
|
6502 |
|
|
wtgo
|
6503 |
|
|
rpc d=013262 -- ! pc=halt
|
6504 |
|
|
rr1 d=000000 -- ! r1=0
|
6505 |
|
|
wal 037000 -- check result area
|
6506 |
|
|
brm 6
|
6507 |
|
|
d=000005 -- ! mov 000000,000000 -> n0z1v0c1; 000000
|
6508 |
|
|
d=000000 -- !
|
6509 |
|
|
d=000001 -- ! mov 000001,000000 -> n0z0v0c1; 000001
|
6510 |
|
|
d=000001 -- !
|
6511 |
|
|
d=000011 -- ! mov 100000,000000 -> n1z0v0c1; 100000
|
6512 |
|
|
d=100000 -- !
|
6513 |
|
|
#--------
|
6514 |
|
|
C Exec test 46.12mc0: MOV - mem, C=0
|
6515 |
|
|
#
|
6516 |
|
|
wal 013276 -- setup test instructions:
|
6517 |
|
|
bwm 2
|
6518 |
|
|
000241 -- ccmov= clc
|
6519 |
|
|
011415 -- iut= mov (r4),(r5)
|
6520 |
|
|
wr0 177776 -- r0=177776
|
6521 |
|
|
wr1 000003 -- r1=3
|
6522 |
|
|
wr2 036000 -- r2=36000
|
6523 |
|
|
wr3 037000 -- r3=37000
|
6524 |
|
|
wr4 001400 -- r4=1400
|
6525 |
|
|
wr5 001402 -- r5=1402
|
6526 |
|
|
wsp 001400 -- sp=1400
|
6527 |
|
|
stapc 013270 -- start @ 13270 (2op mem)
|
6528 |
|
|
wtgo
|
6529 |
|
|
rpc d=013312 -- ! pc=halt
|
6530 |
|
|
rr1 d=000000 -- ! r1=0
|
6531 |
|
|
wal 037000 -- check result area
|
6532 |
|
|
brm 6
|
6533 |
|
|
d=000004 -- ! mov 000000,000000 -> n0z1v0c0; 000000
|
6534 |
|
|
d=000000 -- !
|
6535 |
|
|
d=000000 -- ! mov 000001,000000 -> n0z0v0c0; 000001
|
6536 |
|
|
d=000001 -- !
|
6537 |
|
|
d=000010 -- ! mov 100000,000000 -> n1z0v0c0; 100000
|
6538 |
|
|
d=100000 -- !
|
6539 |
|
|
#--------
|
6540 |
|
|
C Exec test 46.13wrc0: BIT - reg, C=0
|
6541 |
|
|
#
|
6542 |
|
|
wal 036000 -- setup test vector: for bit,bic,bis,xor
|
6543 |
|
|
bwm 12
|
6544 |
|
|
000000 -- bit 000000,000000
|
6545 |
|
|
000000 --
|
6546 |
|
|
000011 -- bit 000011,000000
|
6547 |
|
|
000000 --
|
6548 |
|
|
000011 -- bit 000011,000110
|
6549 |
|
|
000110 --
|
6550 |
|
|
000011 -- bit 000011,001100
|
6551 |
|
|
001100 --
|
6552 |
|
|
110000 -- bit 110000,011000
|
6553 |
|
|
011000 --
|
6554 |
|
|
110000 -- bit 110000,110000
|
6555 |
|
|
110000 --
|
6556 |
|
|
wal 013246 -- setup test instructions:
|
6557 |
|
|
bwm 2
|
6558 |
|
|
000241 -- ccmov= clc
|
6559 |
|
|
030405 -- iut= bit r4,r5
|
6560 |
|
|
wr0 177776 -- r0=177776
|
6561 |
|
|
wr1 000006 -- r1=6
|
6562 |
|
|
wr2 036000 -- r2=36000
|
6563 |
|
|
wr3 037000 -- r3=37000
|
6564 |
|
|
wr4 000000 -- r4=0
|
6565 |
|
|
wr5 000000 -- r5=0
|
6566 |
|
|
wsp 001400 -- sp=1400
|
6567 |
|
|
stapc 013240 -- start @ 13240 (2op reg)
|
6568 |
|
|
wtgo
|
6569 |
|
|
rpc d=013262 -- ! pc=halt
|
6570 |
|
|
rr1 d=000000 -- ! r1=0
|
6571 |
|
|
wal 037000 -- check result area
|
6572 |
|
|
brm 12
|
6573 |
|
|
d=000004 -- ! bit 000000,000000 -> n0z1v0c0; (000000)
|
6574 |
|
|
d=000000 -- !
|
6575 |
|
|
d=000004 -- ! bit 000011,000000 -> n0z1v0c0; (000000)
|
6576 |
|
|
d=000000 -- !
|
6577 |
|
|
d=000000 -- ! bit 000011,000110 -> n0z0v0c0; (000010)
|
6578 |
|
|
d=000110 -- !
|
6579 |
|
|
d=000004 -- ! bit 000011,001100 -> n0z1v0c0; (000000)
|
6580 |
|
|
d=001100 -- !
|
6581 |
|
|
d=000000 -- ! bit 110000,011000 -> n0z0v0c0; (010000)
|
6582 |
|
|
d=011000 -- !
|
6583 |
|
|
d=000010 -- ! bit 110000,110000 -> n1z0v0c0; (100000)
|
6584 |
|
|
d=110000 -- !
|
6585 |
|
|
#--------
|
6586 |
|
|
C Exec test 46.13wrc1: BIT - reg, C=1
|
6587 |
|
|
#
|
6588 |
|
|
wal 013246 -- setup test instructions:
|
6589 |
|
|
bwm 2
|
6590 |
|
|
000261 -- ccmov= sec
|
6591 |
|
|
030405 -- iut= bit r4,r5
|
6592 |
|
|
wr0 177776 -- r0=177776
|
6593 |
|
|
wr1 000006 -- r1=6
|
6594 |
|
|
wr2 036000 -- r2=36000
|
6595 |
|
|
wr3 037000 -- r3=37000
|
6596 |
|
|
wr4 000000 -- r4=0
|
6597 |
|
|
wr5 000000 -- r5=0
|
6598 |
|
|
wsp 001400 -- sp=1400
|
6599 |
|
|
stapc 013240 -- start @ 13240 (2op reg)
|
6600 |
|
|
wtgo
|
6601 |
|
|
rpc d=013262 -- ! pc=halt
|
6602 |
|
|
rr1 d=000000 -- ! r1=0
|
6603 |
|
|
wal 037000 -- check result area
|
6604 |
|
|
brm 12
|
6605 |
|
|
d=000005 -- ! bit 000000,000000 -> n0z1v0c1; (000000)
|
6606 |
|
|
d=000000 -- !
|
6607 |
|
|
d=000005 -- ! bit 000011,000000 -> n0z1v0c1; (000000)
|
6608 |
|
|
d=000000 -- !
|
6609 |
|
|
d=000001 -- ! bit 000011,000110 -> n0z0v0c1; (000010)
|
6610 |
|
|
d=000110 -- !
|
6611 |
|
|
d=000005 -- ! bit 000011,001100 -> n0z1v0c1; (000000)
|
6612 |
|
|
d=001100 -- !
|
6613 |
|
|
d=000001 -- ! bit 110000,011000 -> n0z0v0c1; (010000)
|
6614 |
|
|
d=011000 -- !
|
6615 |
|
|
d=000011 -- ! bit 110000,110000 -> n1z0v0c1; (100000)
|
6616 |
|
|
d=110000 -- !
|
6617 |
|
|
#--------
|
6618 |
|
|
C Exec test 46.13wmc0: BIT - mem, C=0
|
6619 |
|
|
#
|
6620 |
|
|
wal 013276 -- setup test instructions:
|
6621 |
|
|
bwm 2
|
6622 |
|
|
000241 -- ccmov= clc
|
6623 |
|
|
031415 -- iut= bit (r4),(r5)
|
6624 |
|
|
wr0 177776 -- r0=177776
|
6625 |
|
|
wr1 000006 -- r1=6
|
6626 |
|
|
wr2 036000 -- r2=36000
|
6627 |
|
|
wr3 037000 -- r3=37000
|
6628 |
|
|
wr4 001400 -- r4=1400
|
6629 |
|
|
wr5 001402 -- r5=1402
|
6630 |
|
|
wsp 001400 -- sp=1400
|
6631 |
|
|
stapc 013270 -- start @ 13270 (2op mem)
|
6632 |
|
|
wtgo
|
6633 |
|
|
rpc d=013312 -- ! pc=halt
|
6634 |
|
|
rr1 d=000000 -- ! r1=0
|
6635 |
|
|
wal 037000 -- check result area
|
6636 |
|
|
brm 12
|
6637 |
|
|
d=000004 -- ! bit 000000,000000 -> n0z1v0c0; (000000)
|
6638 |
|
|
d=000000 -- !
|
6639 |
|
|
d=000004 -- ! bit 000011,000000 -> n0z1v0c0; (000000)
|
6640 |
|
|
d=000000 -- !
|
6641 |
|
|
d=000000 -- ! bit 000011,000110 -> n0z0v0c0; (000010)
|
6642 |
|
|
d=000110 -- !
|
6643 |
|
|
d=000004 -- ! bit 000011,001100 -> n0z1v0c0; (000000)
|
6644 |
|
|
d=001100 -- !
|
6645 |
|
|
d=000000 -- ! bit 110000,011000 -> n0z0v0c0; (010000)
|
6646 |
|
|
d=011000 -- !
|
6647 |
|
|
d=000010 -- ! bit 110000,110000 -> n1z0v0c0; (100000)
|
6648 |
|
|
d=110000 -- !
|
6649 |
|
|
#--------
|
6650 |
|
|
C Exec test 46.14wrc0: BIC - reg, C=0
|
6651 |
|
|
#
|
6652 |
|
|
wal 013246 -- setup test instructions:
|
6653 |
|
|
bwm 2
|
6654 |
|
|
000241 -- ccmov= clc
|
6655 |
|
|
040405 -- iut= bic r4,r5
|
6656 |
|
|
wr0 177776 -- r0=177776
|
6657 |
|
|
wr1 000006 -- r1=6
|
6658 |
|
|
wr2 036000 -- r2=36000
|
6659 |
|
|
wr3 037000 -- r3=37000
|
6660 |
|
|
wr4 000000 -- r4=0
|
6661 |
|
|
wr5 000000 -- r5=0
|
6662 |
|
|
wsp 001400 -- sp=1400
|
6663 |
|
|
stapc 013240 -- start @ 13240 (2op reg)
|
6664 |
|
|
wtgo
|
6665 |
|
|
rpc d=013262 -- ! pc=halt
|
6666 |
|
|
rr1 d=000000 -- ! r1=0
|
6667 |
|
|
wal 037000 -- check result area
|
6668 |
|
|
brm 12
|
6669 |
|
|
d=000004 -- ! bic 000000,000000 -> n0z1v0c0; 000000
|
6670 |
|
|
d=000000 -- !
|
6671 |
|
|
d=000004 -- ! bic 000011,000000 -> n0z1v0c0; 000000
|
6672 |
|
|
d=000000 -- !
|
6673 |
|
|
d=000000 -- ! bic 000011,000110 -> n0z0v0c0; 000100
|
6674 |
|
|
d=000100 -- !
|
6675 |
|
|
d=000000 -- ! bic 000011,001100 -> n0z0v0c0; 001100
|
6676 |
|
|
d=001100 -- !
|
6677 |
|
|
d=000000 -- ! bic 110000,011000 -> n0z0v0c0; 001000
|
6678 |
|
|
d=001000 -- !
|
6679 |
|
|
d=000004 -- ! bic 110000,110000 -> n0z1v0c0; 000000
|
6680 |
|
|
d=000000 -- !
|
6681 |
|
|
#--------
|
6682 |
|
|
C Exec test 46.14wrc1: BIC - reg, C=1
|
6683 |
|
|
#
|
6684 |
|
|
wal 013246 -- setup test instructions:
|
6685 |
|
|
bwm 2
|
6686 |
|
|
000261 -- ccmov= sec
|
6687 |
|
|
040405 -- iut= bic r4,r5
|
6688 |
|
|
wr0 177776 -- r0=177776
|
6689 |
|
|
wr1 000006 -- r1=6
|
6690 |
|
|
wr2 036000 -- r2=36000
|
6691 |
|
|
wr3 037000 -- r3=37000
|
6692 |
|
|
wr4 000000 -- r4=0
|
6693 |
|
|
wr5 000000 -- r5=0
|
6694 |
|
|
wsp 001400 -- sp=1400
|
6695 |
|
|
stapc 013240 -- start @ 13240 (2op reg)
|
6696 |
|
|
wtgo
|
6697 |
|
|
rpc d=013262 -- ! pc=halt
|
6698 |
|
|
rr1 d=000000 -- ! r1=0
|
6699 |
|
|
wal 037000 -- check result area
|
6700 |
|
|
brm 12
|
6701 |
|
|
d=000005 -- ! bic 000000,000000 -> n0z1v0c1; 000000
|
6702 |
|
|
d=000000 -- !
|
6703 |
|
|
d=000005 -- ! bic 000011,000000 -> n0z1v0c1; 000000
|
6704 |
|
|
d=000000 -- !
|
6705 |
|
|
d=000001 -- ! bic 000011,000110 -> n0z0v0c1; 000100
|
6706 |
|
|
d=000100 -- !
|
6707 |
|
|
d=000001 -- ! bic 000011,001100 -> n0z0v0c1; 001100
|
6708 |
|
|
d=001100 -- !
|
6709 |
|
|
d=000001 -- ! bic 110000,011000 -> n0z0v0c1; 001000
|
6710 |
|
|
d=001000 -- !
|
6711 |
|
|
d=000005 -- ! bic 110000,110000 -> n0z1v0c1; 000000
|
6712 |
|
|
d=000000 -- !
|
6713 |
|
|
#--------
|
6714 |
|
|
C Exec test 46.14wrc0: BIC - mem, C=0
|
6715 |
|
|
#
|
6716 |
|
|
wal 013276 -- setup test instructions:
|
6717 |
|
|
bwm 2
|
6718 |
|
|
000241 -- ccmov= clc
|
6719 |
|
|
041415 -- iut= bic (r4),(r5)
|
6720 |
|
|
wr0 177776 -- r0=177776
|
6721 |
|
|
wr1 000006 -- r1=6
|
6722 |
|
|
wr2 036000 -- r2=36000
|
6723 |
|
|
wr3 037000 -- r3=37000
|
6724 |
|
|
wr4 001400 -- r4=1400
|
6725 |
|
|
wr5 001402 -- r5=1402
|
6726 |
|
|
wsp 001400 -- sp=1400
|
6727 |
|
|
stapc 013270 -- start @ 13270 (2op mem)
|
6728 |
|
|
wtgo
|
6729 |
|
|
rpc d=013312 -- ! pc=halt
|
6730 |
|
|
rr1 d=000000 -- ! r1=0
|
6731 |
|
|
wal 037000 -- check result area
|
6732 |
|
|
brm 12
|
6733 |
|
|
d=000004 -- ! bic 000000,000000 -> n0z1v0c0; 000000
|
6734 |
|
|
d=000000 -- !
|
6735 |
|
|
d=000004 -- ! bic 000011,000000 -> n0z1v0c0; 000000
|
6736 |
|
|
d=000000 -- !
|
6737 |
|
|
d=000000 -- ! bic 000011,000110 -> n0z0v0c0; 000100
|
6738 |
|
|
d=000100 -- !
|
6739 |
|
|
d=000000 -- ! bic 000011,001100 -> n0z0v0c0; 001100
|
6740 |
|
|
d=001100 -- !
|
6741 |
|
|
d=000000 -- ! bic 110000,011000 -> n0z0v0c0; 001000
|
6742 |
|
|
d=001000 -- !
|
6743 |
|
|
d=000004 -- ! bic 110000,110000 -> n0z1v0c0; 000000
|
6744 |
|
|
d=000000 -- !
|
6745 |
|
|
#--------
|
6746 |
|
|
C Exec test 46.15wrc0: BIS - reg, C=0
|
6747 |
|
|
#
|
6748 |
|
|
wal 013246 -- setup test instructions:
|
6749 |
|
|
bwm 2
|
6750 |
|
|
000241 -- ccmov= clc
|
6751 |
|
|
050405 -- iut= bis r4,r5
|
6752 |
|
|
wr0 177776 -- r0=177776
|
6753 |
|
|
wr1 000006 -- r1=6
|
6754 |
|
|
wr2 036000 -- r2=36000
|
6755 |
|
|
wr3 037000 -- r3=37000
|
6756 |
|
|
wr4 000000 -- r4=0
|
6757 |
|
|
wr5 000000 -- r5=0
|
6758 |
|
|
wsp 001400 -- sp=1400
|
6759 |
|
|
stapc 013240 -- start @ 13240 (2op reg)
|
6760 |
|
|
wtgo
|
6761 |
|
|
rpc d=013262 -- ! pc=halt
|
6762 |
|
|
rr1 d=000000 -- ! r1=0
|
6763 |
|
|
wal 037000 -- check result area
|
6764 |
|
|
brm 12
|
6765 |
|
|
d=000004 -- ! bis 000000,000000 -> n0z1v0c0; 000000
|
6766 |
|
|
d=000000 -- !
|
6767 |
|
|
d=000000 -- ! bis 000011,000000 -> n0z0v0c0; 000011
|
6768 |
|
|
d=000011 -- !
|
6769 |
|
|
d=000000 -- ! bis 000011,000110 -> n0z0v0c0; 000111
|
6770 |
|
|
d=000111 -- !
|
6771 |
|
|
d=000000 -- ! bis 000011,001100 -> n0z0v0c0; 001111
|
6772 |
|
|
d=001111 -- !
|
6773 |
|
|
d=000010 -- ! bis 110000,011000 -> n1z0v0c0; 111000
|
6774 |
|
|
d=111000 -- !
|
6775 |
|
|
d=000010 -- ! bis 110000,110000 -> n1z0v0c0; 110000
|
6776 |
|
|
d=110000 -- !
|
6777 |
|
|
#--------
|
6778 |
|
|
C Exec test 46.15wrc1: BIS - reg, C=1
|
6779 |
|
|
#
|
6780 |
|
|
wal 013246 -- setup test instructions:
|
6781 |
|
|
bwm 2
|
6782 |
|
|
000261 -- ccmov= sec
|
6783 |
|
|
050405 -- iut= bis r4,r5
|
6784 |
|
|
wr0 177776 -- r0=177776
|
6785 |
|
|
wr1 000006 -- r1=6
|
6786 |
|
|
wr2 036000 -- r2=36000
|
6787 |
|
|
wr3 037000 -- r3=37000
|
6788 |
|
|
wr4 000000 -- r4=0
|
6789 |
|
|
wr5 000000 -- r5=0
|
6790 |
|
|
wsp 001400 -- sp=1400
|
6791 |
|
|
stapc 013240 -- start @ 13240 (2op reg)
|
6792 |
|
|
wtgo
|
6793 |
|
|
rpc d=013262 -- ! pc=halt
|
6794 |
|
|
rr1 d=000000 -- ! r1=0
|
6795 |
|
|
wal 037000 -- check result area
|
6796 |
|
|
brm 12
|
6797 |
|
|
d=000005 -- ! bis 000000,000000 -> n0z1v0c1; 000000
|
6798 |
|
|
d=000000 -- !
|
6799 |
|
|
d=000001 -- ! bis 000011,000000 -> n0z0v0c1; 000011
|
6800 |
|
|
d=000011 -- !
|
6801 |
|
|
d=000001 -- ! bis 000011,000110 -> n0z0v0c1; 000111
|
6802 |
|
|
d=000111 -- !
|
6803 |
|
|
d=000001 -- ! bis 000011,001100 -> n0z0v0c1; 001111
|
6804 |
|
|
d=001111 -- !
|
6805 |
|
|
d=000011 -- ! bis 110000,011000 -> n1z0v0c1; 111000
|
6806 |
|
|
d=111000 -- !
|
6807 |
|
|
d=000011 -- ! bis 110000,110000 -> n1z0v0c1; 110000
|
6808 |
|
|
d=110000 -- !
|
6809 |
|
|
#--------
|
6810 |
|
|
C Exec test 46.16wrc0: XOR - reg, C=0
|
6811 |
|
|
#
|
6812 |
|
|
wal 013246 -- setup test instructions:
|
6813 |
|
|
bwm 2
|
6814 |
|
|
000241 -- ccmov= clc
|
6815 |
|
|
074405 -- iut= xor r4,r5
|
6816 |
|
|
wr0 177776 -- r0=177776
|
6817 |
|
|
wr1 000006 -- r1=6
|
6818 |
|
|
wr2 036000 -- r2=36000
|
6819 |
|
|
wr3 037000 -- r3=37000
|
6820 |
|
|
wr4 000000 -- r4=0
|
6821 |
|
|
wr5 000000 -- r5=0
|
6822 |
|
|
wsp 001400 -- sp=1400
|
6823 |
|
|
stapc 013240 -- start @ 13240 (2op reg)
|
6824 |
|
|
wtgo
|
6825 |
|
|
rpc d=013262 -- ! pc=halt
|
6826 |
|
|
rr1 d=000000 -- ! r1=0
|
6827 |
|
|
wal 037000 -- check result area
|
6828 |
|
|
brm 12
|
6829 |
|
|
d=000004 -- ! xor 000000,000000 -> n0z1v0c0; 000000
|
6830 |
|
|
d=000000 -- !
|
6831 |
|
|
d=000000 -- ! xor 000011,000000 -> n0z0v0c0; 000011
|
6832 |
|
|
d=000011 -- !
|
6833 |
|
|
d=000000 -- ! xor 000011,000110 -> n0z0v0c0; 000101
|
6834 |
|
|
d=000101 -- !
|
6835 |
|
|
d=000000 -- ! xor 000011,001100 -> n0z0v0c0; 001111
|
6836 |
|
|
d=001111 -- !
|
6837 |
|
|
d=000010 -- ! xor 110000,011000 -> n1z0v0c0; 101000
|
6838 |
|
|
d=101000 -- !
|
6839 |
|
|
d=000004 -- ! xor 110000,110000 -> n1z0v0c0; 000000
|
6840 |
|
|
d=000000 -- !
|
6841 |
|
|
#--------
|
6842 |
|
|
C Exec test 46.16wrc1: XOR - reg, C=1
|
6843 |
|
|
#
|
6844 |
|
|
wal 013246 -- setup test instructions:
|
6845 |
|
|
bwm 2
|
6846 |
|
|
000261 -- ccmov= sec
|
6847 |
|
|
074405 -- iut= xor r4,r5
|
6848 |
|
|
wr0 177776 -- r0=177776
|
6849 |
|
|
wr1 000006 -- r1=6
|
6850 |
|
|
wr2 036000 -- r2=36000
|
6851 |
|
|
wr3 037000 -- r3=37000
|
6852 |
|
|
wr4 000000 -- r4=0
|
6853 |
|
|
wr5 000000 -- r5=0
|
6854 |
|
|
wsp 001400 -- sp=1400
|
6855 |
|
|
stapc 013240 -- start @ 13240 (2op reg)
|
6856 |
|
|
wtgo
|
6857 |
|
|
rpc d=013262 -- ! pc=halt
|
6858 |
|
|
rr1 d=000000 -- ! r1=0
|
6859 |
|
|
wal 037000 -- check result area
|
6860 |
|
|
brm 12
|
6861 |
|
|
d=000005 -- ! xor 000000,000000 -> n0z1v0c1; 000000
|
6862 |
|
|
d=000000 -- !
|
6863 |
|
|
d=000001 -- ! xor 000011,000000 -> n0z0v0c1; 000011
|
6864 |
|
|
d=000011 -- !
|
6865 |
|
|
d=000001 -- ! xor 000011,000110 -> n0z0v0c1; 000101
|
6866 |
|
|
d=000101 -- !
|
6867 |
|
|
d=000001 -- ! xor 000011,001100 -> n0z0v0c1; 001111
|
6868 |
|
|
d=001111 -- !
|
6869 |
|
|
d=000011 -- ! xor 110000,011000 -> n1z0v0c1; 101000
|
6870 |
|
|
d=101000 -- !
|
6871 |
|
|
d=000005 -- ! xor 110000,110000 -> n1z0v0c1; 000000
|
6872 |
|
|
d=000000 -- !
|
6873 |
|
|
#--------
|
6874 |
|
|
C Exec test 46.17wr: CMP - reg
|
6875 |
|
|
#
|
6876 |
|
|
wal 036000 -- setup test vector: for cmp,add,sub
|
6877 |
|
|
bwm 38
|
6878 |
|
|
000000 -- cmp 000000,000000
|
6879 |
|
|
000000 --
|
6880 |
|
|
000001 -- cmp 000001,000000
|
6881 |
|
|
000000 --
|
6882 |
|
|
177777 -- cmp 177777,000000
|
6883 |
|
|
000000 --
|
6884 |
|
|
000000 -- cmp 000000,000001
|
6885 |
|
|
000001 --
|
6886 |
|
|
000001 -- cmp 000001,000001
|
6887 |
|
|
000001 --
|
6888 |
|
|
177777 -- cmp 177777,000001
|
6889 |
|
|
000001 --
|
6890 |
|
|
077776 -- cmp 077776,077777
|
6891 |
|
|
077777 --
|
6892 |
|
|
077777 -- cmp 077777,077777
|
6893 |
|
|
077777 --
|
6894 |
|
|
100000 -- cmp 100000,077777
|
6895 |
|
|
077777 --
|
6896 |
|
|
000001 -- cmp 000001,077777
|
6897 |
|
|
077777 --
|
6898 |
|
|
177777 -- cmp 177777,077777
|
6899 |
|
|
077777 --
|
6900 |
|
|
077777 -- cmp 077777,100000
|
6901 |
|
|
100000 --
|
6902 |
|
|
100000 -- cmp 100000,100000
|
6903 |
|
|
100000 --
|
6904 |
|
|
100001 -- cmp 100001,100000
|
6905 |
|
|
100000 --
|
6906 |
|
|
000001 -- cmp 000001,100000
|
6907 |
|
|
100000 --
|
6908 |
|
|
177777 -- cmp 177777,100000
|
6909 |
|
|
100000 --
|
6910 |
|
|
000000 -- cmp 000000,177777
|
6911 |
|
|
177777 --
|
6912 |
|
|
000001 -- cmp 000001,177777
|
6913 |
|
|
177777 --
|
6914 |
|
|
177777 -- cmp 177777,177777
|
6915 |
|
|
177777 --
|
6916 |
|
|
wal 013246 -- setup test instructions:
|
6917 |
|
|
bwm 2
|
6918 |
|
|
000241 -- ccmov= clc
|
6919 |
|
|
020405 -- iut= cmp r4,r5
|
6920 |
|
|
wr0 177776 -- r0=177776
|
6921 |
|
|
wr1 000023 -- r1=23 (19.)
|
6922 |
|
|
wr2 036000 -- r2=36000
|
6923 |
|
|
wr3 037000 -- r3=37000
|
6924 |
|
|
wr4 000000 -- r4=0
|
6925 |
|
|
wr5 000000 -- r5=0
|
6926 |
|
|
wsp 001400 -- sp=1400
|
6927 |
|
|
stapc 013240 -- start @ 13240 (2op reg)
|
6928 |
|
|
wtgo
|
6929 |
|
|
rpc d=013262 -- ! pc=halt
|
6930 |
|
|
rr1 d=000000 -- ! r1=0 (Note: C=1 if dst > src unsigned)
|
6931 |
|
|
wal 037000 -- check result area (Note: V=1 if s xor d and r eq d)
|
6932 |
|
|
brm 38
|
6933 |
|
|
d=000004 -- ! cmp 000000,000000 -> n0z1v0c0; (000000)
|
6934 |
|
|
d=000000 -- !
|
6935 |
|
|
d=000000 -- ! cmp 000001,000000 -> n0z0v0c0; (000001)
|
6936 |
|
|
d=000000 -- !
|
6937 |
|
|
d=000010 -- ! cmp 177777,000000 -> n1z0v0c0; (177777)
|
6938 |
|
|
d=000000 -- !
|
6939 |
|
|
d=000011 -- ! cmp 000000,000001 -> n1z0v0c1; (177777+C)
|
6940 |
|
|
d=000001 -- !
|
6941 |
|
|
d=000004 -- ! cmp 000001,000001 -> n0z1v0c0; (000000)
|
6942 |
|
|
d=000001 -- !
|
6943 |
|
|
d=000010 -- ! cmp 177777,000001 -> n1z0v0c0; (177776)
|
6944 |
|
|
d=000001 -- !
|
6945 |
|
|
d=000011 -- ! cmp 077776,077777 -> n1z0v0c1; (177777+C)
|
6946 |
|
|
d=077777 -- !
|
6947 |
|
|
d=000004 -- ! cmp 077777,077777 -> n0z1v0c0; (000000)
|
6948 |
|
|
d=077777 -- !
|
6949 |
|
|
d=000002 -- ! cmp 100000,077777 -> n0z0v1c0; (000001)
|
6950 |
|
|
d=077777 -- !
|
6951 |
|
|
d=000011 -- ! cmp 000001,077777 -> n1z0v0c1; (100002+C)
|
6952 |
|
|
d=077777 -- !
|
6953 |
|
|
d=000010 -- ! cmp 177777,077777 -> n1z0v0c0; (100000)
|
6954 |
|
|
d=077777 -- !
|
6955 |
|
|
d=000013 -- ! cmp 077777,100000 -> n1z0v1c1; (177777+C)
|
6956 |
|
|
d=100000 -- !
|
6957 |
|
|
d=000004 -- ! cmp 100000,100000 -> n0z1v0c0; (000000)
|
6958 |
|
|
d=100000 -- !
|
6959 |
|
|
d=000000 -- ! cmp 100001,100000 -> n0z0v0c0; (000001)
|
6960 |
|
|
d=100000 -- !
|
6961 |
|
|
d=000013 -- ! cmp 000001,100000 -> n1z0v1c1; (100001+C)
|
6962 |
|
|
d=100000 -- !
|
6963 |
|
|
d=000000 -- ! cmp 177777,100000 -> n0z0v0c0; (077777)
|
6964 |
|
|
d=100000 -- !
|
6965 |
|
|
d=000001 -- ! cmp 000000,177777 -> n0z0v0c1; (000001+C)
|
6966 |
|
|
d=177777 -- !
|
6967 |
|
|
d=000001 -- ! cmp 000001,177777 -> n0z0v0c1; (000002+C)
|
6968 |
|
|
d=177777 -- !
|
6969 |
|
|
d=000004 -- ! cmp 177777,177777 -> n0z1v0c0; (000000)
|
6970 |
|
|
d=177777 -- !
|
6971 |
|
|
#--------
|
6972 |
|
|
C Exec test 46.18r: ADD - reg
|
6973 |
|
|
#
|
6974 |
|
|
wal 013246 -- setup test instructions:
|
6975 |
|
|
bwm 2
|
6976 |
|
|
000241 -- ccmov= clc
|
6977 |
|
|
060405 -- iut= add r4,r5
|
6978 |
|
|
wr0 177776 -- r0=177776
|
6979 |
|
|
wr1 000023 -- r1=23 (19.)
|
6980 |
|
|
wr2 036000 -- r2=36000
|
6981 |
|
|
wr3 037000 -- r3=37000
|
6982 |
|
|
wr4 000000 -- r4=0
|
6983 |
|
|
wr5 000000 -- r5=0
|
6984 |
|
|
wsp 001400 -- sp=1400
|
6985 |
|
|
stapc 013240 -- start @ 13240 (2op reg)
|
6986 |
|
|
wtgo
|
6987 |
|
|
rpc d=013262 -- ! pc=halt
|
6988 |
|
|
rr1 d=000000 -- ! r1=0
|
6989 |
|
|
wal 037000 -- check result area (Note: V=1 if s eq d and r neq d)
|
6990 |
|
|
brm 38
|
6991 |
|
|
d=000004 -- ! add 000000,000000 -> n0z1v0c0; 000000
|
6992 |
|
|
d=000000 -- !
|
6993 |
|
|
d=000000 -- ! add 000001,000000 -> n0z0v0c0; 000001
|
6994 |
|
|
d=000001 -- !
|
6995 |
|
|
d=000010 -- ! add 177777,000000 -> n1z0v0c0; 177777
|
6996 |
|
|
d=177777 -- !
|
6997 |
|
|
d=000000 -- ! add 000000,000001 -> n0z0v0c0; 000001
|
6998 |
|
|
d=000001 -- !
|
6999 |
|
|
d=000000 -- ! add 000001,000001 -> n0z0v0c0; 000002
|
7000 |
|
|
d=000002 -- !
|
7001 |
|
|
d=000005 -- ! add 177777,000001 -> n0z1v0c1; 000000+C
|
7002 |
|
|
d=000000 -- !
|
7003 |
|
|
d=000012 -- ! add 077776,077777 -> n1z0v1c0; 177775
|
7004 |
|
|
d=177775 -- !
|
7005 |
|
|
d=000012 -- ! add 077777,077777 -> n1z0v1c0; 177776
|
7006 |
|
|
d=177776 -- !
|
7007 |
|
|
d=000010 -- ! add 100000,077777 -> n1z0v0c0; 177777
|
7008 |
|
|
d=177777 -- !
|
7009 |
|
|
d=000012 -- ! add 000001,077777 -> n1z0v1c0; 100000
|
7010 |
|
|
d=100000 -- !
|
7011 |
|
|
d=000001 -- ! add 177777,077777 -> n0z0v0c1; 077776+C
|
7012 |
|
|
d=077776 -- !
|
7013 |
|
|
d=000010 -- ! add 077777,100000 -> n1z0v0c1; 177777+C
|
7014 |
|
|
d=177777 -- !
|
7015 |
|
|
d=000007 -- ! add 100000,100000 -> n0z1v1c1; 000000+C
|
7016 |
|
|
d=000000 -- !
|
7017 |
|
|
d=000003 -- ! add 100001,100000 -> n0z0v1c1; 000001+C
|
7018 |
|
|
d=000001 -- !
|
7019 |
|
|
d=000010 -- ! add 000001,100000 -> n1z0v0c0; 100001
|
7020 |
|
|
d=100001 -- !
|
7021 |
|
|
d=000003 -- ! add 177777,100000 -> n0z0v1c1; 077777+C
|
7022 |
|
|
d=077777 -- !
|
7023 |
|
|
d=000010 -- ! add 000000,177777 -> n1z0v0c0; 177777
|
7024 |
|
|
d=177777 -- !
|
7025 |
|
|
d=000005 -- ! add 000001,177777 -> n0z1v0c1; 000000+C
|
7026 |
|
|
d=000000 -- !
|
7027 |
|
|
d=000011 -- ! add 177777,177777 -> n1z0v0c1; 177776+C
|
7028 |
|
|
d=177776 -- !
|
7029 |
|
|
#--------
|
7030 |
|
|
C Exec test 46.19r: SUB - reg
|
7031 |
|
|
#
|
7032 |
|
|
wal 013246 -- setup test instructions:
|
7033 |
|
|
bwm 2
|
7034 |
|
|
000241 -- ccmov= clc
|
7035 |
|
|
160405 -- iut= sub r4,r5
|
7036 |
|
|
wr0 177776 -- r0=177776
|
7037 |
|
|
wr1 000023 -- r1=23 (19.)
|
7038 |
|
|
wr2 036000 -- r2=36000
|
7039 |
|
|
wr3 037000 -- r3=37000
|
7040 |
|
|
wr4 000000 -- r4=0
|
7041 |
|
|
wr5 000000 -- r5=0
|
7042 |
|
|
wsp 001400 -- sp=1400
|
7043 |
|
|
stapc 013240 -- start @ 13240 (2op reg)
|
7044 |
|
|
wtgo
|
7045 |
|
|
rpc d=013262 -- ! pc=halt
|
7046 |
|
|
rr1 d=000000 -- ! r1=0 (Note: C=1 if src > dst unsigned)
|
7047 |
|
|
wal 037000 -- check result area (Note: V=1 if s xor d and r eq s)
|
7048 |
|
|
brm 38
|
7049 |
|
|
d=000004 -- ! sub 000000,000000 -> n0z1v0c0; 000000
|
7050 |
|
|
d=000000 -- !
|
7051 |
|
|
d=000011 -- ! sub 000001,000000 -> n1z0v0c1; 177777+C
|
7052 |
|
|
d=177777 -- !
|
7053 |
|
|
d=000001 -- ! sub 177777,000000 -> n0z0v0c1; 000001+C
|
7054 |
|
|
d=000001 -- !
|
7055 |
|
|
d=000000 -- ! sub 000000,000001 -> n0z0v0c0; 000001
|
7056 |
|
|
d=000001 -- !
|
7057 |
|
|
d=000004 -- ! sub 000001,000001 -> n0z1v0c0; 000000
|
7058 |
|
|
d=000000 -- !
|
7059 |
|
|
d=000001 -- ! sub 177777,000001 -> n0z0v0c1; 000002+C
|
7060 |
|
|
d=000002 -- !
|
7061 |
|
|
d=000000 -- ! sub 077776,077777 -> n0z0v0c0; 000001
|
7062 |
|
|
d=000001 -- !
|
7063 |
|
|
d=000004 -- ! sub 077777,077777 -> n0z1v0c0; 000000
|
7064 |
|
|
d=000000 -- !
|
7065 |
|
|
d=000013 -- ! sub 100000,077777 -> n1z0v1c1; 177777+C
|
7066 |
|
|
d=177777 -- !
|
7067 |
|
|
d=000000 -- ! sub 000001,077777 -> n0z0v0c0; 077776
|
7068 |
|
|
d=077776 -- !
|
7069 |
|
|
d=000013 -- ! sub 177777,077777 -> n1z0v1c1; 100000+C
|
7070 |
|
|
d=100000 -- !
|
7071 |
|
|
d=000002 -- ! sub 077777,100000 -> n0z0v1c0; 000001
|
7072 |
|
|
d=000001 -- !
|
7073 |
|
|
d=000004 -- ! sub 100000,100000 -> n0z1v0c0; 000000
|
7074 |
|
|
d=000000 -- !
|
7075 |
|
|
d=000011 -- ! sub 100001,100000 -> n1z0v0c1; 177777+C
|
7076 |
|
|
d=177777 -- !
|
7077 |
|
|
d=000002 -- ! sub 000001,100000 -> n0z0v1c0; 077777
|
7078 |
|
|
d=077777 -- !
|
7079 |
|
|
d=000011 -- ! sub 177777,100000 -> n1z0v0c1: 100001+C
|
7080 |
|
|
d=100001 -- !
|
7081 |
|
|
d=000010 -- ! sub 000000,177777 -> n1z0v0c0; 177777
|
7082 |
|
|
d=177777 -- !
|
7083 |
|
|
d=000010 -- ! sub 000001,177777 -> n1z0v0c0; 177776
|
7084 |
|
|
d=177776 -- !
|
7085 |
|
|
d=000004 -- ! sub 177777,177777 -> n0z1v0c0; 000000
|
7086 |
|
|
d=000000 -- !
|
7087 |
|
|
#
|
7088 |
|
|
C Exec test 46.20r: SWAP - reg
|
7089 |
|
|
#
|
7090 |
|
|
wal 036000 -- setup test vector: for swap
|
7091 |
|
|
bwm 9
|
7092 |
|
|
000000 -- swap 000000
|
7093 |
|
|
000001 -- swap 000001
|
7094 |
|
|
000200 -- swap 000200
|
7095 |
|
|
000400 -- swap 000400
|
7096 |
|
|
100000 -- swap 100000
|
7097 |
|
|
000401 -- swap 000401
|
7098 |
|
|
000600 -- swap 000600
|
7099 |
|
|
100001 -- swap 100001
|
7100 |
|
|
100200 -- swap 100200
|
7101 |
|
|
wal 013204 -- setup test instructions:
|
7102 |
|
|
bwm 2
|
7103 |
|
|
000241 -- ccmov= clc
|
7104 |
|
|
000305 -- iut= swap r5
|
7105 |
|
|
wr0 177776 -- r0=177776
|
7106 |
|
|
wr1 000011 -- r1=11 (9.)
|
7107 |
|
|
wr2 036000 -- r2=36000
|
7108 |
|
|
wr3 037000 -- r3=37000
|
7109 |
|
|
wr4 000000 -- r4=0
|
7110 |
|
|
wr5 000000 -- r5=0
|
7111 |
|
|
wsp 001400 -- sp=1400
|
7112 |
|
|
stapc 013200 -- start @ 13200 (1op reg)
|
7113 |
|
|
wtgo
|
7114 |
|
|
rpc d=013220 -- ! pc=halt
|
7115 |
|
|
rr1 d=000000 -- ! r1=0
|
7116 |
|
|
wal 037000 -- check result area (Note: N,Z from lsb of result)
|
7117 |
|
|
brm 18
|
7118 |
|
|
d=000004 -- ! swap 000000 -> n0z1v0c0; 000000
|
7119 |
|
|
d=000000 -- !
|
7120 |
|
|
d=000004 -- ! swap 000001 -> n0z1v0c0; 000400
|
7121 |
|
|
d=000400 -- !
|
7122 |
|
|
d=000004 -- ! swap 000200 -> n0z1v0c0; 100000
|
7123 |
|
|
d=100000 -- !
|
7124 |
|
|
d=000000 -- ! swap 000400 -> n0z0v0c0; 000001
|
7125 |
|
|
d=000001 -- !
|
7126 |
|
|
d=000010 -- ! swap 100000 -> n1z0v0c0; 000200
|
7127 |
|
|
d=000200 -- !
|
7128 |
|
|
d=000000 -- ! swap 000401 -> n0z0v0c0; 000401
|
7129 |
|
|
d=000401 -- !
|
7130 |
|
|
d=000000 -- ! swap 000600 -> n0z0v0c0; 100001
|
7131 |
|
|
d=100001 -- !
|
7132 |
|
|
d=000010 -- ! swap 100001 -> n1z0v0c0; 000600
|
7133 |
|
|
d=000600 -- !
|
7134 |
|
|
d=000010 -- ! swap 100200 -> n1z0v0c0; 100200
|
7135 |
|
|
d=100200 -- !
|
7136 |
|
|
#--------
|
7137 |
|
|
C Exec code 46 pass 2 (systematic result+cc test of 1+2op instructions; byte)
|
7138 |
|
|
C Exec test 46.1br: COMB - reg
|
7139 |
|
|
#
|
7140 |
|
|
wal 036000 -- setup test vector: for com,inc,dec,neg,adc,sbc,tst (b)
|
7141 |
|
|
bwm 5
|
7142 |
|
|
000000 -- comb 000000
|
7143 |
|
|
000001 -- comb 000001
|
7144 |
|
|
000177 -- comb 000177
|
7145 |
|
|
000200 -- comb 000200
|
7146 |
|
|
000377 -- comb 000377
|
7147 |
|
|
wal 013204 -- setup test instructions:
|
7148 |
|
|
bwm 2
|
7149 |
|
|
000241 -- ccmov= clc
|
7150 |
|
|
105105 -- iut= comb r5
|
7151 |
|
|
wr0 177776 -- r0=177776
|
7152 |
|
|
wr1 000005 -- r1=5
|
7153 |
|
|
wr2 036000 -- r2=36000
|
7154 |
|
|
wr3 037000 -- r3=37000
|
7155 |
|
|
wr4 000000 -- r4=0
|
7156 |
|
|
wr5 000000 -- r5=0
|
7157 |
|
|
wsp 001400 -- sp=1400
|
7158 |
|
|
stapc 013200 -- start @ 13200 (1op reg)
|
7159 |
|
|
wtgo
|
7160 |
|
|
rpc d=013220 -- ! pc=halt
|
7161 |
|
|
rr1 d=000000 -- ! r1=0
|
7162 |
|
|
wal 037000 -- check result area
|
7163 |
|
|
brm 10
|
7164 |
|
|
d=000011 -- ! comb 000000 -> n1z0v0c1; 000377
|
7165 |
|
|
d=000377 -- !
|
7166 |
|
|
d=000011 -- ! comb 000001 -> n1z0v0c1; 000376
|
7167 |
|
|
d=000376 -- !
|
7168 |
|
|
d=000011 -- ! comb 000177 -> n1z0v0c1; 000200
|
7169 |
|
|
d=000200 -- !
|
7170 |
|
|
d=000001 -- ! comb 000200 -> n0z0v0c1; 000177
|
7171 |
|
|
d=000177 -- !
|
7172 |
|
|
d=000005 -- ! comb 000377 -> n0z1v0c1; 000000
|
7173 |
|
|
d=000000 -- !
|
7174 |
|
|
#--------
|
7175 |
|
|
C Exec test 46.1bm: COMB - mem
|
7176 |
|
|
#
|
7177 |
|
|
wal 013224 -- setup test instructions:
|
7178 |
|
|
bwm 2
|
7179 |
|
|
000241 -- ccmov= clc
|
7180 |
|
|
105115 -- iut= comb (r5)
|
7181 |
|
|
wr0 177776 -- r0=177776
|
7182 |
|
|
wr1 000005 -- r1=5
|
7183 |
|
|
wr2 036000 -- r2=36000
|
7184 |
|
|
wr3 037000 -- r3=37000
|
7185 |
|
|
wr4 001400 -- r4=1400
|
7186 |
|
|
wr5 001402 -- r5=1402
|
7187 |
|
|
wsp 001400 -- sp=1400
|
7188 |
|
|
stapc 013220 -- start @ 13220 (1op mem)
|
7189 |
|
|
wtgo
|
7190 |
|
|
rpc d=013240 -- ! pc=halt
|
7191 |
|
|
rr1 d=000000 -- ! r1=0
|
7192 |
|
|
wal 037000 -- check result area
|
7193 |
|
|
brm 10
|
7194 |
|
|
d=000011 -- ! comb 000000 -> n1z0v0c1; 000377
|
7195 |
|
|
d=000377 -- !
|
7196 |
|
|
d=000011 -- ! comb 000001 -> n1z0v0c1; 000376
|
7197 |
|
|
d=000376 -- !
|
7198 |
|
|
d=000011 -- ! comb 000177 -> n1z0v0c1; 000200
|
7199 |
|
|
d=000200 -- !
|
7200 |
|
|
d=000001 -- ! comb 000200 -> n0z0v0c1; 000177
|
7201 |
|
|
d=000177 -- !
|
7202 |
|
|
d=000005 -- ! comb 000377 -> n0z1v0c1; 000000
|
7203 |
|
|
d=000000 -- !
|
7204 |
|
|
#--------
|
7205 |
|
|
C Exec test 46.2brc0: INCB - reg,C=0
|
7206 |
|
|
#
|
7207 |
|
|
wal 013204 -- setup test instructions:
|
7208 |
|
|
bwm 2
|
7209 |
|
|
000241 -- ccmov= clc
|
7210 |
|
|
105205 -- iut= incb r5
|
7211 |
|
|
wr0 177776 -- r0=177776
|
7212 |
|
|
wr1 000005 -- r1=5
|
7213 |
|
|
wr2 036000 -- r2=36000
|
7214 |
|
|
wr3 037000 -- r3=37000
|
7215 |
|
|
wr4 000000 -- r4=0
|
7216 |
|
|
wr5 000000 -- r5=0
|
7217 |
|
|
wsp 001400 -- sp=1400
|
7218 |
|
|
stapc 013200 -- start @ 13200 (1op reg)
|
7219 |
|
|
wtgo
|
7220 |
|
|
rpc d=013220 -- ! pc=halt
|
7221 |
|
|
rr1 d=000000 -- ! r1=0
|
7222 |
|
|
wal 037000 -- check result area
|
7223 |
|
|
brm 10
|
7224 |
|
|
d=000000 -- ! incb 000000 -> n0z0v0c0; 000001
|
7225 |
|
|
d=000001 -- !
|
7226 |
|
|
d=000000 -- ! incb 000001 -> n0z0v0c0; 000002
|
7227 |
|
|
d=000002 -- !
|
7228 |
|
|
d=000012 -- ! incb 000177 -> n1z0v1c0; 000200
|
7229 |
|
|
d=000200 -- !
|
7230 |
|
|
d=000010 -- ! incb 000200 -> n1z0v0c0; 000201
|
7231 |
|
|
d=000201 -- !
|
7232 |
|
|
d=000004 -- ! incb 000377 -> n0z1v0c0; 000000
|
7233 |
|
|
d=000000 -- !
|
7234 |
|
|
#--------
|
7235 |
|
|
C Exec test 46.2brc1: INCB - reg,C=1
|
7236 |
|
|
#
|
7237 |
|
|
wal 013204 -- setup test instructions:
|
7238 |
|
|
bwm 2
|
7239 |
|
|
000261 -- ccmov= sec
|
7240 |
|
|
105205 -- iut= incb r5
|
7241 |
|
|
wr0 177776 -- r0=177776
|
7242 |
|
|
wr1 000005 -- r1=5
|
7243 |
|
|
wr2 036000 -- r2=36000
|
7244 |
|
|
wr3 037000 -- r3=37000
|
7245 |
|
|
wr4 000000 -- r4=0
|
7246 |
|
|
wr5 000000 -- r5=0
|
7247 |
|
|
wsp 001400 -- sp=1400
|
7248 |
|
|
stapc 013200 -- start @ 13200 (1op reg)
|
7249 |
|
|
wtgo
|
7250 |
|
|
rpc d=013220 -- ! pc=halt
|
7251 |
|
|
rr1 d=000000 -- ! r1=0
|
7252 |
|
|
wal 037000 -- check result area
|
7253 |
|
|
brm 10
|
7254 |
|
|
d=000001 -- ! incb 000000 -> n0z0v0c1; 000001
|
7255 |
|
|
d=000001 -- !
|
7256 |
|
|
d=000001 -- ! incb 000001 -> n0z0v0c1; 000002
|
7257 |
|
|
d=000002 -- !
|
7258 |
|
|
d=000013 -- ! incb 000177 -> n1z0v1c1; 000200
|
7259 |
|
|
d=000200 -- !
|
7260 |
|
|
d=000011 -- ! incb 000200 -> n1z0v0c1; 000201
|
7261 |
|
|
d=000201 -- !
|
7262 |
|
|
d=000005 -- ! incb 000377 -> n0z1v0c1; 000000
|
7263 |
|
|
d=000000 -- !
|
7264 |
|
|
#--------
|
7265 |
|
|
C Exec test 46.3brc0: DECB - reg,C=0
|
7266 |
|
|
#
|
7267 |
|
|
wal 013204 -- setup test instructions:
|
7268 |
|
|
bwm 2
|
7269 |
|
|
000241 -- ccmov= clc
|
7270 |
|
|
105305 -- iut= decb r5
|
7271 |
|
|
wr0 177776 -- r0=177776
|
7272 |
|
|
wr1 000005 -- r1=5
|
7273 |
|
|
wr2 036000 -- r2=36000
|
7274 |
|
|
wr3 037000 -- r3=37000
|
7275 |
|
|
wr4 000000 -- r4=0
|
7276 |
|
|
wr5 000000 -- r5=0
|
7277 |
|
|
wsp 001400 -- sp=1400
|
7278 |
|
|
stapc 013200 -- start @ 13200 (1op reg)
|
7279 |
|
|
wtgo
|
7280 |
|
|
rpc d=013220 -- ! pc=halt
|
7281 |
|
|
rr1 d=000000 -- ! r1=0
|
7282 |
|
|
wal 037000 -- check result area
|
7283 |
|
|
brm 10
|
7284 |
|
|
d=000010 -- ! decb 000000 -> n1z0v0c0; 000377
|
7285 |
|
|
d=000377 -- !
|
7286 |
|
|
d=000004 -- ! decb 000001 -> n0z1v0c0; 000000
|
7287 |
|
|
d=000000 -- !
|
7288 |
|
|
d=000000 -- ! decb 000177 -> n0z0v0c0; 000176
|
7289 |
|
|
d=000176 -- !
|
7290 |
|
|
d=000002 -- ! decb 000200 -> n0z0v1c0; 000177
|
7291 |
|
|
d=000177 -- !
|
7292 |
|
|
d=000010 -- ! decb 000377 -> n1z0v0c0; 000376
|
7293 |
|
|
d=000376 -- !
|
7294 |
|
|
#--------
|
7295 |
|
|
C Exec test 46.3brc1: DECB - reg,C=1
|
7296 |
|
|
#
|
7297 |
|
|
wal 013204 -- setup test instructions:
|
7298 |
|
|
bwm 2
|
7299 |
|
|
000261 -- ccmov= sec
|
7300 |
|
|
105305 -- iut= decb r5
|
7301 |
|
|
wr0 177776 -- r0=177776
|
7302 |
|
|
wr1 000005 -- r1=5
|
7303 |
|
|
wr2 036000 -- r2=36000
|
7304 |
|
|
wr3 037000 -- r3=37000
|
7305 |
|
|
wr4 000000 -- r4=0
|
7306 |
|
|
wr5 000000 -- r5=0
|
7307 |
|
|
wsp 001400 -- sp=1400
|
7308 |
|
|
stapc 013200 -- start @ 13200 (1op reg)
|
7309 |
|
|
wtgo
|
7310 |
|
|
rpc d=013220 -- ! pc=halt
|
7311 |
|
|
rr1 d=000000 -- ! r1=0
|
7312 |
|
|
wal 037000 -- check result area
|
7313 |
|
|
brm 10
|
7314 |
|
|
d=000011 -- ! decb 000000 -> n1z0v0c1; 000377
|
7315 |
|
|
d=000377 -- !
|
7316 |
|
|
d=000005 -- ! decb 000001 -> n0z1v0c1; 000000
|
7317 |
|
|
d=000000 -- !
|
7318 |
|
|
d=000001 -- ! decb 000177 -> n0z0v0c1; 000176
|
7319 |
|
|
d=000176 -- !
|
7320 |
|
|
d=000003 -- ! decb 000200 -> n0z0v1c1; 000177
|
7321 |
|
|
d=000177 -- !
|
7322 |
|
|
d=000011 -- ! decb 000377 -> n1z0v0c1; 000376
|
7323 |
|
|
d=000376 -- !
|
7324 |
|
|
#--------
|
7325 |
|
|
C Exec test 46.4br: NEGB - reg
|
7326 |
|
|
#
|
7327 |
|
|
wal 013204 -- setup test instructions:
|
7328 |
|
|
bwm 2
|
7329 |
|
|
000241 -- ccmov= clc
|
7330 |
|
|
105405 -- iut= negb r5
|
7331 |
|
|
wr0 177776 -- r0=177776
|
7332 |
|
|
wr1 000005 -- r1=5
|
7333 |
|
|
wr2 036000 -- r2=36000
|
7334 |
|
|
wr3 037000 -- r3=37000
|
7335 |
|
|
wr4 000000 -- r4=0
|
7336 |
|
|
wr5 000000 -- r5=0
|
7337 |
|
|
wsp 001400 -- sp=1400
|
7338 |
|
|
stapc 013200 -- start @ 13200 (1op reg)
|
7339 |
|
|
wtgo
|
7340 |
|
|
rpc d=013220 -- ! pc=halt
|
7341 |
|
|
rr1 d=000000 -- ! r1=0
|
7342 |
|
|
wal 037000 -- check result area
|
7343 |
|
|
brm 10
|
7344 |
|
|
d=000004 -- ! negb 000000 -> n0z1v0c0; 000000
|
7345 |
|
|
d=000000 -- !
|
7346 |
|
|
d=000011 -- ! negb 000001 -> n1z0v0c1; 000377
|
7347 |
|
|
d=000377 -- !
|
7348 |
|
|
d=000011 -- ! negb 000177 -> n1z0v0c1; 000201
|
7349 |
|
|
d=000201 -- !
|
7350 |
|
|
d=000013 -- ! negb 000200 -> n1z0v1c1; 000200
|
7351 |
|
|
d=000200 -- !
|
7352 |
|
|
d=000001 -- ! negb 000377 -> n0z0v0c1; 000001
|
7353 |
|
|
d=000001 -- !
|
7354 |
|
|
#--------
|
7355 |
|
|
C Exec test 46.5brc0: ADCB - reg,C=0
|
7356 |
|
|
#
|
7357 |
|
|
wal 013204 -- setup test instructions:
|
7358 |
|
|
bwm 2
|
7359 |
|
|
000241 -- ccmov= clc
|
7360 |
|
|
105505 -- iut= adcb r5
|
7361 |
|
|
wr0 177776 -- r0=177776
|
7362 |
|
|
wr1 000005 -- r1=5
|
7363 |
|
|
wr2 036000 -- r2=36000
|
7364 |
|
|
wr3 037000 -- r3=37000
|
7365 |
|
|
wr4 000000 -- r4=0
|
7366 |
|
|
wr5 000000 -- r5=0
|
7367 |
|
|
wsp 001400 -- sp=1400
|
7368 |
|
|
stapc 013200 -- start @ 13200 (1op reg)
|
7369 |
|
|
wtgo
|
7370 |
|
|
rpc d=013220 -- ! pc=halt
|
7371 |
|
|
rr1 d=000000 -- ! r1=0
|
7372 |
|
|
wal 037000 -- check result area
|
7373 |
|
|
brm 10
|
7374 |
|
|
d=000004 -- ! adcb 000000 -> n0z1v0c0; 000000
|
7375 |
|
|
d=000000 -- !
|
7376 |
|
|
d=000000 -- ! adcb 000001 -> n0z0v0c0; 000001
|
7377 |
|
|
d=000001 -- !
|
7378 |
|
|
d=000000 -- ! adcb 000177 -> n0z0v0c0; 000177
|
7379 |
|
|
d=000177 -- !
|
7380 |
|
|
d=000010 -- ! adcb 000200 -> n1z0v0c0; 000200
|
7381 |
|
|
d=000200 -- !
|
7382 |
|
|
d=000010 -- ! adcb 000377 -> n1z0v0c0; 000377
|
7383 |
|
|
d=000377 -- !
|
7384 |
|
|
#--------
|
7385 |
|
|
C Exec test 46.5brc1: ADCB - reg,C=1
|
7386 |
|
|
#
|
7387 |
|
|
wal 013204 -- setup test instructions:
|
7388 |
|
|
bwm 2
|
7389 |
|
|
000261 -- ccmov= sec
|
7390 |
|
|
105505 -- iut= adcb r5
|
7391 |
|
|
wr0 177776 -- r0=177776
|
7392 |
|
|
wr1 000005 -- r1=5
|
7393 |
|
|
wr2 036000 -- r2=36000
|
7394 |
|
|
wr3 037000 -- r3=37000
|
7395 |
|
|
wr4 000000 -- r4=0
|
7396 |
|
|
wr5 000000 -- r5=0
|
7397 |
|
|
wsp 001400 -- sp=1400
|
7398 |
|
|
stapc 013200 -- start @ 13200 (1op reg)
|
7399 |
|
|
wtgo
|
7400 |
|
|
rpc d=013220 -- ! pc=halt
|
7401 |
|
|
rr1 d=000000 -- ! r1=0
|
7402 |
|
|
wal 037000 -- check result area
|
7403 |
|
|
brm 10
|
7404 |
|
|
d=000000 -- ! adcb 000000 -> n0z0v0c0; 000001
|
7405 |
|
|
d=000001 -- !
|
7406 |
|
|
d=000000 -- ! adcb 000001 -> n0z0v0c0; 000002
|
7407 |
|
|
d=000002 -- !
|
7408 |
|
|
d=000012 -- ! adcb 000177 -> n1z0v1c0; 000200
|
7409 |
|
|
d=000200 -- !
|
7410 |
|
|
d=000010 -- ! adcb 000200 -> n1z0v0c0; 000201
|
7411 |
|
|
d=000201 -- !
|
7412 |
|
|
d=000005 -- ! adcb 000377 -> n0z1v0c1; 000000
|
7413 |
|
|
d=000000 -- !
|
7414 |
|
|
#--------
|
7415 |
|
|
C Exec test 46.6brc0: SBCB - reg,C=0
|
7416 |
|
|
#
|
7417 |
|
|
wal 013204 -- setup test instructions:
|
7418 |
|
|
bwm 2
|
7419 |
|
|
000241 -- ccmov= clc
|
7420 |
|
|
105605 -- iut= sbcb r5
|
7421 |
|
|
wr0 177776 -- r0=177776
|
7422 |
|
|
wr1 000005 -- r1=5
|
7423 |
|
|
wr2 036000 -- r2=36000
|
7424 |
|
|
wr3 037000 -- r3=37000
|
7425 |
|
|
wr4 000000 -- r4=0
|
7426 |
|
|
wr5 000000 -- r5=0
|
7427 |
|
|
wsp 001400 -- sp=1400
|
7428 |
|
|
stapc 013200 -- start @ 13200 (1op reg)
|
7429 |
|
|
wtgo
|
7430 |
|
|
rpc d=013220 -- ! pc=halt
|
7431 |
|
|
rr1 d=000000 -- ! r1=0
|
7432 |
|
|
wal 037000 -- check result area
|
7433 |
|
|
brm 10
|
7434 |
|
|
d=000004 -- ! sbcb 000000 -> n0z1v0c0; 000000
|
7435 |
|
|
d=000000 -- !
|
7436 |
|
|
d=000000 -- ! sbcb 000001 -> n0z0v0c0; 000001
|
7437 |
|
|
d=000001 -- !
|
7438 |
|
|
d=000000 -- ! sbcb 000177 -> n0z0v0c0; 000177
|
7439 |
|
|
d=000177 -- !
|
7440 |
|
|
d=000010 -- ! sbcb 000200 -> n1z0v0c0; 000200
|
7441 |
|
|
d=000200 -- !
|
7442 |
|
|
d=000010 -- ! sbcb 000377 -> n1z0v0c0; 000377
|
7443 |
|
|
d=000377 -- !
|
7444 |
|
|
#--------
|
7445 |
|
|
C Exec test 46.6brc1: SBCB - reg,C=1
|
7446 |
|
|
#
|
7447 |
|
|
wal 013204 -- setup test instructions:
|
7448 |
|
|
bwm 2
|
7449 |
|
|
000261 -- ccmov= sec
|
7450 |
|
|
105605 -- iut= sbcb r5
|
7451 |
|
|
wr0 177776 -- r0=177776
|
7452 |
|
|
wr1 000005 -- r1=5
|
7453 |
|
|
wr2 036000 -- r2=36000
|
7454 |
|
|
wr3 037000 -- r3=37000
|
7455 |
|
|
wr4 000000 -- r4=0
|
7456 |
|
|
wr5 000000 -- r5=0
|
7457 |
|
|
wsp 001400 -- sp=1400
|
7458 |
|
|
stapc 013200 -- start @ 13200 (1op reg)
|
7459 |
|
|
wtgo
|
7460 |
|
|
rpc d=013220 -- ! pc=halt
|
7461 |
|
|
rr1 d=000000 -- ! r1=0
|
7462 |
|
|
wal 037000 -- check result area
|
7463 |
|
|
brm 10
|
7464 |
|
|
d=000011 -- ! sbcb 000000 -> n1z0v0c1; 000377
|
7465 |
|
|
d=000377 -- !
|
7466 |
|
|
d=000004 -- ! sbcb 000001 -> n0z1v0c0; 000000
|
7467 |
|
|
d=000000 -- !
|
7468 |
|
|
d=000000 -- ! sbcb 000177 -> n0z0v0c0; 000176
|
7469 |
|
|
d=000176 -- !
|
7470 |
|
|
d=000002 -- ! sbcb 000200 -> n0z0v1c0; 000177
|
7471 |
|
|
d=000177 -- !
|
7472 |
|
|
d=000010 -- ! sbcb 000377 -> n1z0v0c0; 000376
|
7473 |
|
|
d=000376 -- !
|
7474 |
|
|
#--------
|
7475 |
|
|
C Exec test 46.7br: TSTB - reg
|
7476 |
|
|
#
|
7477 |
|
|
wal 013204 -- setup test instructions:
|
7478 |
|
|
bwm 2
|
7479 |
|
|
000261 -- ccmov= sec
|
7480 |
|
|
105705 -- iut= tstb r5
|
7481 |
|
|
wr0 177776 -- r0=177776
|
7482 |
|
|
wr1 000005 -- r1=5
|
7483 |
|
|
wr2 036000 -- r2=36000
|
7484 |
|
|
wr3 037000 -- r3=37000
|
7485 |
|
|
wr4 000000 -- r4=0
|
7486 |
|
|
wr5 000000 -- r5=0
|
7487 |
|
|
wsp 001400 -- sp=1400
|
7488 |
|
|
stapc 013200 -- start @ 13200 (1op reg)
|
7489 |
|
|
wtgo
|
7490 |
|
|
rpc d=013220 -- ! pc=halt
|
7491 |
|
|
rr1 d=000000 -- ! r1=0
|
7492 |
|
|
wal 037000 -- check result area
|
7493 |
|
|
brm 10
|
7494 |
|
|
d=000004 -- ! tstb 000000 -> n0z1v0c0;
|
7495 |
|
|
d=000000 -- !
|
7496 |
|
|
d=000000 -- ! tstb 000001 -> n0z0v0c0;
|
7497 |
|
|
d=000001 -- !
|
7498 |
|
|
d=000000 -- ! tstb 000177 -> n0z0v0c0;
|
7499 |
|
|
d=000177 -- !
|
7500 |
|
|
d=000010 -- ! tstb 000200 -> n1z0v0c0;
|
7501 |
|
|
d=000200 -- !
|
7502 |
|
|
d=000010 -- ! tstb 000377 -> n1z0v0c0;
|
7503 |
|
|
d=000377 -- !
|
7504 |
|
|
#--------
|
7505 |
|
|
C Exec test 46.7bm: TSTB - mem
|
7506 |
|
|
#
|
7507 |
|
|
wal 013224 -- setup test instructions:
|
7508 |
|
|
bwm 2
|
7509 |
|
|
000261 -- ccmov= sec
|
7510 |
|
|
105715 -- iut= tstb (r5)
|
7511 |
|
|
wr0 177776 -- r0=177776
|
7512 |
|
|
wr1 000005 -- r1=5
|
7513 |
|
|
wr2 036000 -- r2=36000
|
7514 |
|
|
wr3 037000 -- r3=37000
|
7515 |
|
|
wr4 001400 -- r4=1400
|
7516 |
|
|
wr5 001402 -- r5=1402
|
7517 |
|
|
wsp 001400 -- sp=1400
|
7518 |
|
|
stapc 013220 -- start @ 13220 (1op mem)
|
7519 |
|
|
wtgo
|
7520 |
|
|
rpc d=013240 -- ! pc=halt
|
7521 |
|
|
rr1 d=000000 -- ! r1=0
|
7522 |
|
|
wal 037000 -- check result area
|
7523 |
|
|
brm 10
|
7524 |
|
|
d=000004 -- ! tstb 000000 -> n0z1v0c0;
|
7525 |
|
|
d=000000 -- !
|
7526 |
|
|
d=000000 -- ! tstb 000001 -> n0z0v0c0;
|
7527 |
|
|
d=000001 -- !
|
7528 |
|
|
d=000000 -- ! tstb 000177 -> n0z0v0c0;
|
7529 |
|
|
d=000177 -- !
|
7530 |
|
|
d=000010 -- ! tstb 000200 -> n1z0v0c0;
|
7531 |
|
|
d=000200 -- !
|
7532 |
|
|
d=000010 -- ! tstb 000377 -> n1z0v0c0;
|
7533 |
|
|
d=000377 -- !
|
7534 |
|
|
#--------
|
7535 |
|
|
C Exec test 46.8brc0: RORB - reg, C=0
|
7536 |
|
|
#
|
7537 |
|
|
wal 036000 -- setup test vector: for ror,rol,ars,asl (b)
|
7538 |
|
|
bwm 7
|
7539 |
|
|
000000 -- ror 000000
|
7540 |
|
|
000001 -- ror 000001
|
7541 |
|
|
000200 -- ror 000200
|
7542 |
|
|
000010 -- ror 000010
|
7543 |
|
|
000011 -- ror 000011
|
7544 |
|
|
000110 -- ror 000110
|
7545 |
|
|
000210 -- ror 000210
|
7546 |
|
|
wal 013204 -- setup test instructions:
|
7547 |
|
|
bwm 2
|
7548 |
|
|
000241 -- ccmov= clc
|
7549 |
|
|
106005 -- iut= rorb r5
|
7550 |
|
|
wr0 177776 -- r0=177776
|
7551 |
|
|
wr1 000007 -- r1=7
|
7552 |
|
|
wr2 036000 -- r2=36000
|
7553 |
|
|
wr3 037000 -- r3=37000
|
7554 |
|
|
wr4 000000 -- r4=0
|
7555 |
|
|
wr5 000000 -- r5=0
|
7556 |
|
|
wsp 001400 -- sp=1400
|
7557 |
|
|
stapc 013200 -- start @ 13200 (1op reg)
|
7558 |
|
|
wtgo
|
7559 |
|
|
rpc d=013220 -- ! pc=halt
|
7560 |
|
|
rr1 d=000000 -- ! r1=0
|
7561 |
|
|
wal 037000 -- check result area (Note: V = N xor C !)
|
7562 |
|
|
brm 14
|
7563 |
|
|
d=000004 -- ! rorb 000000 -> n0z1v0c0; 000000
|
7564 |
|
|
d=000000 -- !
|
7565 |
|
|
d=000007 -- ! rorb 000001 -> n0z1v1c1; 000000
|
7566 |
|
|
d=000000 -- !
|
7567 |
|
|
d=000000 -- ! rorb 000200 -> n0z0v0c0; 000100
|
7568 |
|
|
d=000100 -- !
|
7569 |
|
|
d=000000 -- ! rorb 000010 -> n0z0v0c0; 000004
|
7570 |
|
|
d=000004 -- !
|
7571 |
|
|
d=000003 -- ! rorb 000011 -> n0z0v1c1; 000004
|
7572 |
|
|
d=000004 -- !
|
7573 |
|
|
d=000000 -- ! rorb 000110 -> n0z0v0c0; 000044
|
7574 |
|
|
d=000044 -- !
|
7575 |
|
|
d=000000 -- ! rorb 000210 -> n0z0v0c0; 000104
|
7576 |
|
|
d=000104 -- !
|
7577 |
|
|
#--------
|
7578 |
|
|
C Exec test 46.8brc1: RORB - reg, C=1
|
7579 |
|
|
#
|
7580 |
|
|
wal 013204 -- setup test instructions:
|
7581 |
|
|
bwm 2
|
7582 |
|
|
000261 -- ccmov= sec
|
7583 |
|
|
106005 -- iut= rorb r5
|
7584 |
|
|
wr0 177776 -- r0=177776
|
7585 |
|
|
wr1 000007 -- r1=7
|
7586 |
|
|
wr2 036000 -- r2=36000
|
7587 |
|
|
wr3 037000 -- r3=37000
|
7588 |
|
|
wr4 000000 -- r4=0
|
7589 |
|
|
wr5 000000 -- r5=0
|
7590 |
|
|
wsp 001400 -- sp=1400
|
7591 |
|
|
stapc 013200 -- start @ 13200 (1op reg)
|
7592 |
|
|
wtgo
|
7593 |
|
|
rpc d=013220 -- ! pc=halt
|
7594 |
|
|
rr1 d=000000 -- ! r1=0
|
7595 |
|
|
wal 037000 -- check result area (Note: V = N xor C !)
|
7596 |
|
|
brm 14
|
7597 |
|
|
d=000012 -- ! rorb 000000 -> n1z0v1c0; 000200
|
7598 |
|
|
d=000200 -- !
|
7599 |
|
|
d=000011 -- ! rorb 000001 -> n1z0v0c1; 000200
|
7600 |
|
|
d=000200 -- !
|
7601 |
|
|
d=000012 -- ! rorb 000200 -> n1z0v1c0; 000300
|
7602 |
|
|
d=000300 -- !
|
7603 |
|
|
d=000012 -- ! rorb 000010 -> n1z0v1c0; 000204
|
7604 |
|
|
d=000204 -- !
|
7605 |
|
|
d=000011 -- ! rorb 000011 -> n1z0v0c1; 000204
|
7606 |
|
|
d=000204 -- !
|
7607 |
|
|
d=000012 -- ! rorb 000110 -> n1z0v1c0; 000244
|
7608 |
|
|
d=000244 -- !
|
7609 |
|
|
d=000012 -- ! rorb 000210 -> n1z0v1c0; 000304
|
7610 |
|
|
d=000304 -- !
|
7611 |
|
|
#--------
|
7612 |
|
|
C Exec test 46.9brc0: ROLB - reg, C=0
|
7613 |
|
|
#
|
7614 |
|
|
wal 013204 -- setup test instructions:
|
7615 |
|
|
bwm 2
|
7616 |
|
|
000241 -- ccmov= clc
|
7617 |
|
|
106105 -- iut= rolb r5
|
7618 |
|
|
wr0 177776 -- r0=177776
|
7619 |
|
|
wr1 000007 -- r1=7
|
7620 |
|
|
wr2 036000 -- r2=36000
|
7621 |
|
|
wr3 037000 -- r3=37000
|
7622 |
|
|
wr4 000000 -- r4=0
|
7623 |
|
|
wr5 000000 -- r5=0
|
7624 |
|
|
wsp 001400 -- sp=1400
|
7625 |
|
|
stapc 013200 -- start @ 13200 (1op reg)
|
7626 |
|
|
wtgo
|
7627 |
|
|
rpc d=013220 -- ! pc=halt
|
7628 |
|
|
rr1 d=000000 -- ! r1=0
|
7629 |
|
|
wal 037000 -- check result area (Note: V = N xor C !)
|
7630 |
|
|
brm 14
|
7631 |
|
|
d=000004 -- ! rolb 000000 -> n0z1v0c0; 000000
|
7632 |
|
|
d=000000 -- !
|
7633 |
|
|
d=000000 -- ! rolb 000001 -> n0z0v0c0; 000002
|
7634 |
|
|
d=000002 -- !
|
7635 |
|
|
d=000007 -- ! rolb 000200 -> n0z1v1c1; 000000
|
7636 |
|
|
d=000000 -- !
|
7637 |
|
|
d=000000 -- ! rolb 000010 -> n0z0v0c0; 000020
|
7638 |
|
|
d=000020 -- !
|
7639 |
|
|
d=000000 -- ! rolb 000011 -> n0z0v0c0; 000022
|
7640 |
|
|
d=000022 -- !
|
7641 |
|
|
d=000012 -- ! rolb 000110 -> n1z0v1c0; 000220
|
7642 |
|
|
d=000220 -- !
|
7643 |
|
|
d=000003 -- ! rolb 000210 -> n0z0v1c1; 000020
|
7644 |
|
|
d=000020 -- !
|
7645 |
|
|
#--------
|
7646 |
|
|
C Exec test 46.9brc1: ROLB - reg, C=1
|
7647 |
|
|
#
|
7648 |
|
|
wal 013204 -- setup test instructions:
|
7649 |
|
|
bwm 2
|
7650 |
|
|
000261 -- ccmov= sec
|
7651 |
|
|
106105 -- iut= rolb r5
|
7652 |
|
|
wr0 177776 -- r0=177776
|
7653 |
|
|
wr1 000007 -- r1=7
|
7654 |
|
|
wr2 036000 -- r2=36000
|
7655 |
|
|
wr3 037000 -- r3=37000
|
7656 |
|
|
wr4 000000 -- r4=0
|
7657 |
|
|
wr5 000000 -- r5=0
|
7658 |
|
|
wsp 001400 -- sp=1400
|
7659 |
|
|
stapc 013200 -- start @ 13200 (1op reg)
|
7660 |
|
|
wtgo
|
7661 |
|
|
rpc d=013220 -- ! pc=halt
|
7662 |
|
|
rr1 d=000000 -- ! r1=0
|
7663 |
|
|
wal 037000 -- check result area (Note: V = N xor C !)
|
7664 |
|
|
brm 14
|
7665 |
|
|
d=000000 -- ! rolb 000000 -> n0z0v0c0; 000001
|
7666 |
|
|
d=000001 -- !
|
7667 |
|
|
d=000000 -- ! rolb 000001 -> n0z0v0c0; 000003
|
7668 |
|
|
d=000003 -- !
|
7669 |
|
|
d=000003 -- ! rolb 000200 -> n0z0v1c1; 000001
|
7670 |
|
|
d=000001 -- !
|
7671 |
|
|
d=000000 -- ! rolb 000010 -> n0z0v0c0; 000021
|
7672 |
|
|
d=000021 -- !
|
7673 |
|
|
d=000000 -- ! rolb 000011 -> n0z0v0c0; 000023
|
7674 |
|
|
d=000023 -- !
|
7675 |
|
|
d=000012 -- ! rolb 000110 -> n1z0v1c0; 000221
|
7676 |
|
|
d=000221 -- !
|
7677 |
|
|
d=000003 -- ! rolb 000210 -> n0z0v1c1; 000021
|
7678 |
|
|
d=000021 -- !
|
7679 |
|
|
#--------
|
7680 |
|
|
C Exec test 46.10brc0: ASRB - reg, C=0
|
7681 |
|
|
#
|
7682 |
|
|
wal 013204 -- setup test instructions:
|
7683 |
|
|
bwm 2
|
7684 |
|
|
000241 -- ccmov= clc
|
7685 |
|
|
106205 -- iut= asrb r5
|
7686 |
|
|
wr0 177776 -- r0=177776
|
7687 |
|
|
wr1 000007 -- r1=7
|
7688 |
|
|
wr2 036000 -- r2=36000
|
7689 |
|
|
wr3 037000 -- r3=37000
|
7690 |
|
|
wr4 000000 -- r4=0
|
7691 |
|
|
wr5 000000 -- r5=0
|
7692 |
|
|
wsp 001400 -- sp=1400
|
7693 |
|
|
stapc 013200 -- start @ 13200 (1op reg)
|
7694 |
|
|
wtgo
|
7695 |
|
|
rpc d=013220 -- ! pc=halt
|
7696 |
|
|
rr1 d=000000 -- ! r1=0
|
7697 |
|
|
wal 037000 -- check result area (Note: V = N xor C !)
|
7698 |
|
|
brm 14
|
7699 |
|
|
d=000004 -- ! asrb 000000 -> n0z1v0c0; 000000
|
7700 |
|
|
d=000000 -- !
|
7701 |
|
|
d=000007 -- ! asrb 000001 -> n0z1v1c1; 000000
|
7702 |
|
|
d=000000 -- !
|
7703 |
|
|
d=000012 -- ! asrb 000200 -> n1z0v1c0; 000300
|
7704 |
|
|
d=000300 -- !
|
7705 |
|
|
d=000000 -- ! asrb 000010 -> n0z0v0c0; 000004
|
7706 |
|
|
d=000004 -- !
|
7707 |
|
|
d=000003 -- ! asrb 000011 -> n0z0v1c1; 000004
|
7708 |
|
|
d=000004 -- !
|
7709 |
|
|
d=000000 -- ! asrb 000110 -> n0z0v0c0; 000044
|
7710 |
|
|
d=000044 -- !
|
7711 |
|
|
d=000012 -- ! asrb 000210 -> n1z0v1c0; 000304
|
7712 |
|
|
d=000304 -- !
|
7713 |
|
|
#--------
|
7714 |
|
|
C Exec test 46.10brc1: ASRB - reg, C=1
|
7715 |
|
|
#
|
7716 |
|
|
wal 013204 -- setup test instructions:
|
7717 |
|
|
bwm 2
|
7718 |
|
|
000261 -- ccmov= sec
|
7719 |
|
|
106205 -- iut= asrb r5
|
7720 |
|
|
wr0 177776 -- r0=177776
|
7721 |
|
|
wr1 000007 -- r1=7
|
7722 |
|
|
wr2 036000 -- r2=36000
|
7723 |
|
|
wr3 037000 -- r3=37000
|
7724 |
|
|
wr4 000000 -- r4=0
|
7725 |
|
|
wr5 000000 -- r5=0
|
7726 |
|
|
wsp 001400 -- sp=1400
|
7727 |
|
|
stapc 013200 -- start @ 13200 (1op reg)
|
7728 |
|
|
wtgo
|
7729 |
|
|
rpc d=013220 -- ! pc=halt
|
7730 |
|
|
rr1 d=000000 -- ! r1=0
|
7731 |
|
|
wal 037000 -- check result area (Note: V = N xor C !)
|
7732 |
|
|
brm 14
|
7733 |
|
|
d=000004 -- ! asrb 000000 -> n0z1v0c0; 000000
|
7734 |
|
|
d=000000 -- !
|
7735 |
|
|
d=000007 -- ! asrb 000001 -> n0z1v1c1; 000000
|
7736 |
|
|
d=000000 -- !
|
7737 |
|
|
d=000012 -- ! asrb 000200 -> n1z0v1c0; 000300
|
7738 |
|
|
d=000300 -- !
|
7739 |
|
|
d=000000 -- ! asrb 000010 -> n0z0v0c0; 000004
|
7740 |
|
|
d=000004 -- !
|
7741 |
|
|
d=000003 -- ! asrb 000011 -> n0z0v1c1; 000004
|
7742 |
|
|
d=000004 -- !
|
7743 |
|
|
d=000000 -- ! asrb 000110 -> n0z0v0c0; 000044
|
7744 |
|
|
d=000044 -- !
|
7745 |
|
|
d=000012 -- ! asrb 000210 -> n1z0v1c0; 000304
|
7746 |
|
|
d=000304 -- !
|
7747 |
|
|
#--------
|
7748 |
|
|
C Exec test 46.11brc0: ASLB - reg, C=0
|
7749 |
|
|
#
|
7750 |
|
|
wal 013204 -- setup test instructions:
|
7751 |
|
|
bwm 2
|
7752 |
|
|
000241 -- ccmov= clc
|
7753 |
|
|
106305 -- iut= aslb r5
|
7754 |
|
|
wr0 177776 -- r0=177776
|
7755 |
|
|
wr1 000007 -- r1=7
|
7756 |
|
|
wr2 036000 -- r2=36000
|
7757 |
|
|
wr3 037000 -- r3=37000
|
7758 |
|
|
wr4 000000 -- r4=0
|
7759 |
|
|
wr5 000000 -- r5=0
|
7760 |
|
|
wsp 001400 -- sp=1400
|
7761 |
|
|
stapc 013200 -- start @ 13200 (1op reg)
|
7762 |
|
|
wtgo
|
7763 |
|
|
rpc d=013220 -- ! pc=halt
|
7764 |
|
|
rr1 d=000000 -- ! r1=0
|
7765 |
|
|
wal 037000 -- check result area (Note: V = N xor C !)
|
7766 |
|
|
brm 14
|
7767 |
|
|
d=000004 -- ! aslb 000000 -> n0z1v0c0; 000000
|
7768 |
|
|
d=000000 -- !
|
7769 |
|
|
d=000000 -- ! aslb 000001 -> n0z0v0c0; 000002
|
7770 |
|
|
d=000002 -- !
|
7771 |
|
|
d=000007 -- ! aslb 000200 -> n0z1v1c1; 000000
|
7772 |
|
|
d=000000 -- !
|
7773 |
|
|
d=000000 -- ! aslb 000010 -> n0z0v0c0; 000020
|
7774 |
|
|
d=000020 -- !
|
7775 |
|
|
d=000000 -- ! aslb 000011 -> n0z0v0c0; 000022
|
7776 |
|
|
d=000022 -- !
|
7777 |
|
|
d=000012 -- ! aslb 000110 -> n1z0v1c0; 000220
|
7778 |
|
|
d=000220 -- !
|
7779 |
|
|
d=000003 -- ! aslb 000210 -> n0z0v1c1; 000020
|
7780 |
|
|
d=000020 -- !
|
7781 |
|
|
#--------
|
7782 |
|
|
C Exec test 46.11brc1: ASLB - reg, C=1
|
7783 |
|
|
#
|
7784 |
|
|
wal 013204 -- setup test instructions:
|
7785 |
|
|
bwm 2
|
7786 |
|
|
000261 -- ccmov= sec
|
7787 |
|
|
106305 -- iut= aslb r5
|
7788 |
|
|
wr0 177776 -- r0=177776
|
7789 |
|
|
wr1 000007 -- r1=7
|
7790 |
|
|
wr2 036000 -- r2=36000
|
7791 |
|
|
wr3 037000 -- r3=37000
|
7792 |
|
|
wr4 000000 -- r4=0
|
7793 |
|
|
wr5 000000 -- r5=0
|
7794 |
|
|
wsp 001400 -- sp=1400
|
7795 |
|
|
stapc 013200 -- start @ 13200 (1op reg)
|
7796 |
|
|
wtgo
|
7797 |
|
|
rpc d=013220 -- ! pc=halt
|
7798 |
|
|
rr1 d=000000 -- ! r1=0
|
7799 |
|
|
wal 037000 -- check result area (Note: V = N xor C !)
|
7800 |
|
|
brm 14
|
7801 |
|
|
d=000004 -- ! aslb 000000 -> n0z1v0c0; 000000
|
7802 |
|
|
d=000000 -- !
|
7803 |
|
|
d=000000 -- ! aslb 000001 -> n0z0v0c0; 000002
|
7804 |
|
|
d=000002 -- !
|
7805 |
|
|
d=000007 -- ! aslb 000200 -> n0z1v1c1; 000000
|
7806 |
|
|
d=000000 -- !
|
7807 |
|
|
d=000000 -- ! aslb 000010 -> n0z0v0c0; 000020
|
7808 |
|
|
d=000020 -- !
|
7809 |
|
|
d=000000 -- ! aslb 000011 -> n0z0v0c0; 000022
|
7810 |
|
|
d=000022 -- !
|
7811 |
|
|
d=000012 -- ! aslb 000110 -> n1z0v1c0; 000220
|
7812 |
|
|
d=000220 -- !
|
7813 |
|
|
d=000003 -- ! aslb 000210 -> n0z0v1c1; 000020
|
7814 |
|
|
d=000020 -- !
|
7815 |
|
|
#--------
|
7816 |
|
|
C Exec test 46.12brc0: MOVB - reg, C=0
|
7817 |
|
|
#
|
7818 |
|
|
wal 036000 -- setup test vector: for mov
|
7819 |
|
|
bwm 6
|
7820 |
|
|
000000 -- movb 000000,000000
|
7821 |
|
|
000000 --
|
7822 |
|
|
000001 -- movb 000001,000000
|
7823 |
|
|
000000 --
|
7824 |
|
|
000200 -- movb 000200,000000
|
7825 |
|
|
000000 --
|
7826 |
|
|
wal 013246 -- setup test instructions:
|
7827 |
|
|
bwm 2
|
7828 |
|
|
000241 -- ccmov= clc
|
7829 |
|
|
110405 -- iut= movb r4,r5
|
7830 |
|
|
wr0 177776 -- r0=177776
|
7831 |
|
|
wr1 000003 -- r1=3
|
7832 |
|
|
wr2 036000 -- r2=36000
|
7833 |
|
|
wr3 037000 -- r3=37000
|
7834 |
|
|
wr4 000000 -- r4=0
|
7835 |
|
|
wr5 000000 -- r5=0
|
7836 |
|
|
wsp 001400 -- sp=1400
|
7837 |
|
|
stapc 013240 -- start @ 13240 (2op reg)
|
7838 |
|
|
wtgo
|
7839 |
|
|
rpc d=013262 -- ! pc=halt
|
7840 |
|
|
rr1 d=000000 -- ! r1=0
|
7841 |
|
|
wal 037000 -- check result area
|
7842 |
|
|
brm 6
|
7843 |
|
|
d=000004 -- ! movb 000000,000000 -> n0z1v0c0; 000000
|
7844 |
|
|
d=000000 -- !
|
7845 |
|
|
d=000000 -- ! movb 000001,000000 -> n0z0v0c0; 000001
|
7846 |
|
|
d=000001 -- !
|
7847 |
|
|
d=000010 -- ! movb 000200,000000 -> n1z0v0c0; 177600
|
7848 |
|
|
d=177600 -- !
|
7849 |
|
|
#--------
|
7850 |
|
|
C Exec test 46.12brc1: MOVB - reg, C=1
|
7851 |
|
|
#
|
7852 |
|
|
wal 013246 -- setup test instructions:
|
7853 |
|
|
bwm 2
|
7854 |
|
|
000261 -- ccmov= sec
|
7855 |
|
|
110405 -- iut= movb r4,r5
|
7856 |
|
|
wr0 177776 -- r0=177776
|
7857 |
|
|
wr1 000003 -- r1=3
|
7858 |
|
|
wr2 036000 -- r2=36000
|
7859 |
|
|
wr3 037000 -- r3=37000
|
7860 |
|
|
wr4 000000 -- r4=0
|
7861 |
|
|
wr5 000000 -- r5=0
|
7862 |
|
|
wsp 001400 -- sp=1400
|
7863 |
|
|
stapc 013240 -- start @ 13240 (2op reg)
|
7864 |
|
|
wtgo
|
7865 |
|
|
rpc d=013262 -- ! pc=halt
|
7866 |
|
|
rr1 d=000000 -- ! r1=0
|
7867 |
|
|
wal 037000 -- check result area
|
7868 |
|
|
brm 6
|
7869 |
|
|
d=000005 -- ! movb 000000,000000 -> n0z1v0c1; 000000
|
7870 |
|
|
d=000000 -- !
|
7871 |
|
|
d=000001 -- ! movb 000001,000000 -> n0z0v0c1; 000001
|
7872 |
|
|
d=000001 -- !
|
7873 |
|
|
d=000011 -- ! movb 000200,000000 -> n1z0v0c1; 177600
|
7874 |
|
|
d=177600 -- !
|
7875 |
|
|
#--------
|
7876 |
|
|
C Exec test 46.12bmc0: MOVB - mem, C=0
|
7877 |
|
|
#
|
7878 |
|
|
wal 013276 -- setup test instructions:
|
7879 |
|
|
bwm 2
|
7880 |
|
|
000241 -- ccmov= clc
|
7881 |
|
|
111415 -- iut= movb (r4),(r5)
|
7882 |
|
|
wr0 177776 -- r0=177776
|
7883 |
|
|
wr1 000003 -- r1=3
|
7884 |
|
|
wr2 036000 -- r2=36000
|
7885 |
|
|
wr3 037000 -- r3=37000
|
7886 |
|
|
wr4 001400 -- r4=1400
|
7887 |
|
|
wr5 001402 -- r5=1402
|
7888 |
|
|
wsp 001400 -- sp=1400
|
7889 |
|
|
stapc 013270 -- start @ 13270 (2op mem)
|
7890 |
|
|
wtgo
|
7891 |
|
|
rpc d=013312 -- ! pc=halt
|
7892 |
|
|
rr1 d=000000 -- ! r1=0
|
7893 |
|
|
wal 037000 -- check result area
|
7894 |
|
|
brm 6
|
7895 |
|
|
d=000004 -- ! movb 000000,000000 -> n0z1v0c0; 000000
|
7896 |
|
|
d=000000 -- !
|
7897 |
|
|
d=000000 -- ! movb 000001,000000 -> n0z0v0c0; 000001
|
7898 |
|
|
d=000001 -- !
|
7899 |
|
|
d=000010 -- ! movb 000200,000000 -> n1z0v0c0; 000200
|
7900 |
|
|
d=000200 -- !
|
7901 |
|
|
#--------
|
7902 |
|
|
C Exec test 46.13brc0: BITB - reg, C=0
|
7903 |
|
|
#
|
7904 |
|
|
wal 036000 -- setup test vector: for bit,bic,bis (b)
|
7905 |
|
|
bwm 12
|
7906 |
|
|
000000 -- bitb 000000,000000
|
7907 |
|
|
000000 --
|
7908 |
|
|
000003 -- bitb 000003,000000
|
7909 |
|
|
000000 --
|
7910 |
|
|
000003 -- bitb 000003,000006
|
7911 |
|
|
000006 --
|
7912 |
|
|
000003 -- bitb 000003,000014
|
7913 |
|
|
000014 --
|
7914 |
|
|
000300 -- bitb 000300,000140
|
7915 |
|
|
000140 --
|
7916 |
|
|
000300 -- bitb 000300,000300
|
7917 |
|
|
000300 --
|
7918 |
|
|
wal 013246 -- setup test instructions:
|
7919 |
|
|
bwm 2
|
7920 |
|
|
000241 -- ccmov= clc
|
7921 |
|
|
130405 -- iut= bitb r4,r5
|
7922 |
|
|
wr0 177776 -- r0=177776
|
7923 |
|
|
wr1 000006 -- r1=6
|
7924 |
|
|
wr2 036000 -- r2=36000
|
7925 |
|
|
wr3 037000 -- r3=37000
|
7926 |
|
|
wr4 000000 -- r4=0
|
7927 |
|
|
wr5 000000 -- r5=0
|
7928 |
|
|
wsp 001400 -- sp=1400
|
7929 |
|
|
stapc 013240 -- start @ 13240 (2op reg)
|
7930 |
|
|
wtgo
|
7931 |
|
|
rpc d=013262 -- ! pc=halt
|
7932 |
|
|
rr1 d=000000 -- ! r1=0
|
7933 |
|
|
wal 037000 -- check result area
|
7934 |
|
|
brm 12
|
7935 |
|
|
d=000004 -- ! bitb 000000,000000 -> n0z1v0c0; (000000)
|
7936 |
|
|
d=000000 -- !
|
7937 |
|
|
d=000004 -- ! bitb 000003,000000 -> n0z1v0c0; (000000)
|
7938 |
|
|
d=000000 -- !
|
7939 |
|
|
d=000000 -- ! bitb 000003,000006 -> n0z0v0c0; (000002)
|
7940 |
|
|
d=000006 -- !
|
7941 |
|
|
d=000004 -- ! bitb 000003,000014 -> n0z1v0c0; (000000)
|
7942 |
|
|
d=000014 -- !
|
7943 |
|
|
d=000000 -- ! bitb 000300,000140 -> n0z0v0c0; (000100)
|
7944 |
|
|
d=000140 -- !
|
7945 |
|
|
d=000010 -- ! bitb 000300,000300 -> n1z0v0c0; (000300)
|
7946 |
|
|
d=000300 -- !
|
7947 |
|
|
#--------
|
7948 |
|
|
C Exec test 46.13brc1: BITB - reg, C=1
|
7949 |
|
|
#
|
7950 |
|
|
wal 013246 -- setup test instructions:
|
7951 |
|
|
bwm 2
|
7952 |
|
|
000261 -- ccmov= sec
|
7953 |
|
|
130405 -- iut= bitb r4,r5
|
7954 |
|
|
wr0 177776 -- r0=177776
|
7955 |
|
|
wr1 000006 -- r1=6
|
7956 |
|
|
wr2 036000 -- r2=36000
|
7957 |
|
|
wr3 037000 -- r3=37000
|
7958 |
|
|
wr4 000000 -- r4=0
|
7959 |
|
|
wr5 000000 -- r5=0
|
7960 |
|
|
wsp 001400 -- sp=1400
|
7961 |
|
|
stapc 013240 -- start @ 13240 (2op reg)
|
7962 |
|
|
wtgo
|
7963 |
|
|
rpc d=013262 -- ! pc=halt
|
7964 |
|
|
rr1 d=000000 -- ! r1=0
|
7965 |
|
|
wal 037000 -- check result area
|
7966 |
|
|
brm 12
|
7967 |
|
|
d=000005 -- ! bitb 000000,000000 -> n0z1v0c1; (000000)
|
7968 |
|
|
d=000000 -- !
|
7969 |
|
|
d=000005 -- ! bitb 000003,000000 -> n0z1v0c1; (000000)
|
7970 |
|
|
d=000000 -- !
|
7971 |
|
|
d=000001 -- ! bitb 000003,000006 -> n0z0v0c1; (000002)
|
7972 |
|
|
d=000006 -- !
|
7973 |
|
|
d=000005 -- ! bitb 000003,000014 -> n0z1v0c1; (000000)
|
7974 |
|
|
d=000014 -- !
|
7975 |
|
|
d=000001 -- ! bitb 000300,000140 -> n0z0v0c1; (000100)
|
7976 |
|
|
d=000140 -- !
|
7977 |
|
|
d=000011 -- ! bitb 000300,000300 -> n1z0v0c1; (000300)
|
7978 |
|
|
d=000300 -- !
|
7979 |
|
|
#--------
|
7980 |
|
|
C Exec test 46.13bmc0: BITB - mem, C=0
|
7981 |
|
|
#
|
7982 |
|
|
wal 013276 -- setup test instructions:
|
7983 |
|
|
bwm 2
|
7984 |
|
|
000241 -- ccmov= clc
|
7985 |
|
|
131415 -- iut= bitb (r4),(r5)
|
7986 |
|
|
wr0 177776 -- r0=177776
|
7987 |
|
|
wr1 000006 -- r1=6
|
7988 |
|
|
wr2 036000 -- r2=36000
|
7989 |
|
|
wr3 037000 -- r3=37000
|
7990 |
|
|
wr4 001400 -- r4=1400
|
7991 |
|
|
wr5 001402 -- r5=1402
|
7992 |
|
|
wsp 001400 -- sp=1400
|
7993 |
|
|
stapc 013270 -- start @ 13270 (2op mem)
|
7994 |
|
|
wtgo
|
7995 |
|
|
rpc d=013312 -- ! pc=halt
|
7996 |
|
|
rr1 d=000000 -- ! r1=0
|
7997 |
|
|
wal 037000 -- check result area
|
7998 |
|
|
brm 12
|
7999 |
|
|
d=000004 -- ! bitb 000000,000000 -> n0z1v0c0; (000000)
|
8000 |
|
|
d=000000 -- !
|
8001 |
|
|
d=000004 -- ! bitb 000003,000000 -> n0z1v0c0; (000000)
|
8002 |
|
|
d=000000 -- !
|
8003 |
|
|
d=000000 -- ! bitb 000003,000006 -> n0z0v0c0; (000002)
|
8004 |
|
|
d=000006 -- !
|
8005 |
|
|
d=000004 -- ! bitb 000003,000014 -> n0z1v0c0; (000000)
|
8006 |
|
|
d=000014 -- !
|
8007 |
|
|
d=000000 -- ! bitb 000300,000140 -> n0z0v0c0; (000100)
|
8008 |
|
|
d=000140 -- !
|
8009 |
|
|
d=000010 -- ! bitb 000300,000300 -> n1z0v0c0; (000300)
|
8010 |
|
|
d=000300 -- !
|
8011 |
|
|
#--------
|
8012 |
|
|
C Exec test 46.14brc0: BICB - reg, C=0
|
8013 |
|
|
#
|
8014 |
|
|
wal 013246 -- setup test instructions:
|
8015 |
|
|
bwm 2
|
8016 |
|
|
000241 -- ccmov= clc
|
8017 |
|
|
140405 -- iut= bicb r4,r5
|
8018 |
|
|
wr0 177776 -- r0=177776
|
8019 |
|
|
wr1 000006 -- r1=6
|
8020 |
|
|
wr2 036000 -- r2=36000
|
8021 |
|
|
wr3 037000 -- r3=37000
|
8022 |
|
|
wr4 000000 -- r4=0
|
8023 |
|
|
wr5 000000 -- r5=0
|
8024 |
|
|
wsp 001400 -- sp=1400
|
8025 |
|
|
stapc 013240 -- start @ 13240 (2op reg)
|
8026 |
|
|
wtgo
|
8027 |
|
|
rpc d=013262 -- ! pc=halt
|
8028 |
|
|
rr1 d=000000 -- ! r1=0
|
8029 |
|
|
wal 037000 -- check result area
|
8030 |
|
|
brm 12
|
8031 |
|
|
d=000004 -- ! bicb 000000,000000 -> n0z1v0c0; 000000
|
8032 |
|
|
d=000000 -- !
|
8033 |
|
|
d=000004 -- ! bicb 000003,000000 -> n0z1v0c0; 000000
|
8034 |
|
|
d=000000 -- !
|
8035 |
|
|
d=000000 -- ! bicb 000003,000006 -> n0z0v0c0; 000004
|
8036 |
|
|
d=000004 -- !
|
8037 |
|
|
d=000000 -- ! bicb 000003,000014 -> n0z0v0c0; 000014
|
8038 |
|
|
d=000014 -- !
|
8039 |
|
|
d=000000 -- ! bicb 000300,000140 -> n0z0v0c0; 000040
|
8040 |
|
|
d=000040 -- !
|
8041 |
|
|
d=000004 -- ! bicb 000300,000300 -> n0z1v0c0; 000000
|
8042 |
|
|
d=000000 -- !
|
8043 |
|
|
#--------
|
8044 |
|
|
C Exec test 46.14brc1: BICB - reg, C=1
|
8045 |
|
|
#
|
8046 |
|
|
wal 013246 -- setup test instructions:
|
8047 |
|
|
bwm 2
|
8048 |
|
|
000261 -- ccmov= sec
|
8049 |
|
|
140405 -- iut= bicb r4,r5
|
8050 |
|
|
wr0 177776 -- r0=177776
|
8051 |
|
|
wr1 000006 -- r1=6
|
8052 |
|
|
wr2 036000 -- r2=36000
|
8053 |
|
|
wr3 037000 -- r3=37000
|
8054 |
|
|
wr4 000000 -- r4=0
|
8055 |
|
|
wr5 000000 -- r5=0
|
8056 |
|
|
wsp 001400 -- sp=1400
|
8057 |
|
|
stapc 013240 -- start @ 13240 (2op reg)
|
8058 |
|
|
wtgo
|
8059 |
|
|
rpc d=013262 -- ! pc=halt
|
8060 |
|
|
rr1 d=000000 -- ! r1=0
|
8061 |
|
|
wal 037000 -- check result area
|
8062 |
|
|
brm 12
|
8063 |
|
|
d=000005 -- ! bicb 000000,000000 -> n0z1v0c1; 000000
|
8064 |
|
|
d=000000 -- !
|
8065 |
|
|
d=000005 -- ! bicb 000003,000000 -> n0z1v0c1; 000000
|
8066 |
|
|
d=000000 -- !
|
8067 |
|
|
d=000001 -- ! bicb 000003,000006 -> n0z0v0c1; 000004
|
8068 |
|
|
d=000004 -- !
|
8069 |
|
|
d=000001 -- ! bicb 000003,000014 -> n0z0v0c1; 000014
|
8070 |
|
|
d=000014 -- !
|
8071 |
|
|
d=000001 -- ! bicb 000300,000140 -> n0z0v0c1; 000040
|
8072 |
|
|
d=000040 -- !
|
8073 |
|
|
d=000005 -- ! bicb 000300,000300 -> n0z1v0c1; 000000
|
8074 |
|
|
d=000000 -- !
|
8075 |
|
|
#--------
|
8076 |
|
|
C Exec test 46.14bmrc0: BICB - mem, C=0
|
8077 |
|
|
#
|
8078 |
|
|
wal 013276 -- setup test instructions:
|
8079 |
|
|
bwm 2
|
8080 |
|
|
000241 -- ccmov= clc
|
8081 |
|
|
141415 -- iut= bicb (r4),(r5)
|
8082 |
|
|
wr0 177776 -- r0=177776
|
8083 |
|
|
wr1 000006 -- r1=6
|
8084 |
|
|
wr2 036000 -- r2=36000
|
8085 |
|
|
wr3 037000 -- r3=37000
|
8086 |
|
|
wr4 001400 -- r4=1400
|
8087 |
|
|
wr5 001402 -- r5=1402
|
8088 |
|
|
wsp 001400 -- sp=1400
|
8089 |
|
|
stapc 013270 -- start @ 13270 (2op mem)
|
8090 |
|
|
wtgo
|
8091 |
|
|
rpc d=013312 -- ! pc=halt
|
8092 |
|
|
rr1 d=000000 -- ! r1=0
|
8093 |
|
|
wal 037000 -- check result area
|
8094 |
|
|
brm 12
|
8095 |
|
|
d=000004 -- ! bicb 000000,000000 -> n0z1v0c0; 000000
|
8096 |
|
|
d=000000 -- !
|
8097 |
|
|
d=000004 -- ! bicb 000003,000000 -> n0z1v0c0; 000000
|
8098 |
|
|
d=000000 -- !
|
8099 |
|
|
d=000000 -- ! bicb 000003,000006 -> n0z0v0c0; 000004
|
8100 |
|
|
d=000004 -- !
|
8101 |
|
|
d=000000 -- ! bicb 000003,000014 -> n0z0v0c0; 000014
|
8102 |
|
|
d=000014 -- !
|
8103 |
|
|
d=000000 -- ! bicb 000300,000140 -> n0z0v0c0; 000040
|
8104 |
|
|
d=000040 -- !
|
8105 |
|
|
d=000004 -- ! bicb 000300,000300 -> n0z1v0c0; 000000
|
8106 |
|
|
d=000000 -- !
|
8107 |
|
|
#--------
|
8108 |
|
|
C Exec test 46.15brc0: BISB - reg, C=0
|
8109 |
|
|
#
|
8110 |
|
|
wal 013246 -- setup test instructions:
|
8111 |
|
|
bwm 2
|
8112 |
|
|
000241 -- ccmov= clc
|
8113 |
|
|
150405 -- iut= bisb r4,r5
|
8114 |
|
|
wr0 177776 -- r0=177776
|
8115 |
|
|
wr1 000006 -- r1=6
|
8116 |
|
|
wr2 036000 -- r2=36000
|
8117 |
|
|
wr3 037000 -- r3=37000
|
8118 |
|
|
wr4 000000 -- r4=0
|
8119 |
|
|
wr5 000000 -- r5=0
|
8120 |
|
|
wsp 001400 -- sp=1400
|
8121 |
|
|
stapc 013240 -- start @ 13240 (2op reg)
|
8122 |
|
|
wtgo
|
8123 |
|
|
rpc d=013262 -- ! pc=halt
|
8124 |
|
|
rr1 d=000000 -- ! r1=0
|
8125 |
|
|
wal 037000 -- check result area
|
8126 |
|
|
brm 12
|
8127 |
|
|
d=000004 -- ! bisb 000000,000000 -> n0z1v0c0; 000000
|
8128 |
|
|
d=000000 -- !
|
8129 |
|
|
d=000000 -- ! bisb 000003,000000 -> n0z0v0c0; 000003
|
8130 |
|
|
d=000003 -- !
|
8131 |
|
|
d=000000 -- ! bisb 000003,000006 -> n0z0v0c0; 000007
|
8132 |
|
|
d=000007 -- !
|
8133 |
|
|
d=000000 -- ! bisb 000003,000014 -> n0z0v0c0; 000017
|
8134 |
|
|
d=000017 -- !
|
8135 |
|
|
d=000010 -- ! bisb 000300,000140 -> n1z0v0c0; 000340
|
8136 |
|
|
d=000340 -- !
|
8137 |
|
|
d=000010 -- ! bisb 000300,000300 -> n1z0v0c0; 000300
|
8138 |
|
|
d=000300 -- !
|
8139 |
|
|
#--------
|
8140 |
|
|
C Exec test 46.15brc1: BISB - reg, C=1
|
8141 |
|
|
#
|
8142 |
|
|
wal 013246 -- setup test instructions:
|
8143 |
|
|
bwm 2
|
8144 |
|
|
000261 -- ccmov= sec
|
8145 |
|
|
150405 -- iut= bisb r4,r5
|
8146 |
|
|
wr0 177776 -- r0=177776
|
8147 |
|
|
wr1 000006 -- r1=6
|
8148 |
|
|
wr2 036000 -- r2=36000
|
8149 |
|
|
wr3 037000 -- r3=37000
|
8150 |
|
|
wr4 000000 -- r4=0
|
8151 |
|
|
wr5 000000 -- r5=0
|
8152 |
|
|
wsp 001400 -- sp=1400
|
8153 |
|
|
stapc 013240 -- start @ 13240 (2op reg)
|
8154 |
|
|
wtgo
|
8155 |
|
|
rpc d=013262 -- ! pc=halt
|
8156 |
|
|
rr1 d=000000 -- ! r1=0
|
8157 |
|
|
wal 037000 -- check result area
|
8158 |
|
|
brm 12
|
8159 |
|
|
d=000005 -- ! bisb 000000,000000 -> n0z1v0c1; 000000
|
8160 |
|
|
d=000000 -- !
|
8161 |
|
|
d=000001 -- ! bisb 000003,000000 -> n0z0v0c1; 000003
|
8162 |
|
|
d=000003 -- !
|
8163 |
|
|
d=000001 -- ! bisb 000003,000006 -> n0z0v0c1; 000007
|
8164 |
|
|
d=000007 -- !
|
8165 |
|
|
d=000001 -- ! bisb 000003,000014 -> n0z0v0c1; 000017
|
8166 |
|
|
d=000017 -- !
|
8167 |
|
|
d=000011 -- ! bisb 000300,000140 -> n1z0v0c1; 000340
|
8168 |
|
|
d=000340 -- !
|
8169 |
|
|
d=000011 -- ! bisb 000300,000300 -> n1z0v0c1; 000300
|
8170 |
|
|
d=000300 -- !
|
8171 |
|
|
#--------
|
8172 |
|
|
C Exec test 46.17br: CMPB - reg
|
8173 |
|
|
#
|
8174 |
|
|
wal 036000 -- setup test vector: for cmp (b)
|
8175 |
|
|
bwm 38
|
8176 |
|
|
000000 -- cmpb 000000,000000
|
8177 |
|
|
000000 --
|
8178 |
|
|
000001 -- cmpb 000001,000000
|
8179 |
|
|
000000 --
|
8180 |
|
|
000377 -- cmpb 000377,000000
|
8181 |
|
|
000000 --
|
8182 |
|
|
000000 -- cmpb 000000,000001
|
8183 |
|
|
000001 --
|
8184 |
|
|
000001 -- cmpb 000001,000001
|
8185 |
|
|
000001 --
|
8186 |
|
|
000377 -- cmpb 000377,000001
|
8187 |
|
|
000001 --
|
8188 |
|
|
000176 -- cmpb 000176,000177
|
8189 |
|
|
000177 --
|
8190 |
|
|
000177 -- cmpb 000177,000177
|
8191 |
|
|
000177 --
|
8192 |
|
|
000200 -- cmpb 000200,000177
|
8193 |
|
|
000177 --
|
8194 |
|
|
000001 -- cmpb 000001,000177
|
8195 |
|
|
000177 --
|
8196 |
|
|
000377 -- cmpb 000377,000177
|
8197 |
|
|
000177 --
|
8198 |
|
|
000177 -- cmpb 000177,000200
|
8199 |
|
|
000200 --
|
8200 |
|
|
000200 -- cmpb 000200,000200
|
8201 |
|
|
000200 --
|
8202 |
|
|
000201 -- cmpb 000201,000200
|
8203 |
|
|
000200 --
|
8204 |
|
|
000001 -- cmpb 000001,000200
|
8205 |
|
|
000200 --
|
8206 |
|
|
000377 -- cmpb 000377,000200
|
8207 |
|
|
000200 --
|
8208 |
|
|
000000 -- cmpb 000000,000377
|
8209 |
|
|
000377 --
|
8210 |
|
|
000001 -- cmpb 000001,000377
|
8211 |
|
|
000377 --
|
8212 |
|
|
000377 -- cmpb 000377,000377
|
8213 |
|
|
000377 --
|
8214 |
|
|
wal 013246 -- setup test instructions:
|
8215 |
|
|
bwm 2
|
8216 |
|
|
000241 -- ccmov= clc
|
8217 |
|
|
120405 -- iut= cmpb r4,r5
|
8218 |
|
|
wr0 177776 -- r0=177776
|
8219 |
|
|
wr1 000023 -- r1=23 (19.)
|
8220 |
|
|
wr2 036000 -- r2=36000
|
8221 |
|
|
wr3 037000 -- r3=37000
|
8222 |
|
|
wr4 000000 -- r4=0
|
8223 |
|
|
wr5 000000 -- r5=0
|
8224 |
|
|
wsp 001400 -- sp=1400
|
8225 |
|
|
stapc 013240 -- start @ 13240 (2op reg)
|
8226 |
|
|
wtgo
|
8227 |
|
|
rpc d=013262 -- ! pc=halt
|
8228 |
|
|
rr1 d=000000 -- ! r1=0 (Note: C=1 if dst > src unsigned)
|
8229 |
|
|
wal 037000 -- check result area (Note: V=1 if s xor d and r eq d)
|
8230 |
|
|
brm 38
|
8231 |
|
|
d=000004 -- ! cmpb 000000,000000 -> n0z1v0c0; (000000)
|
8232 |
|
|
d=000000 -- !
|
8233 |
|
|
d=000000 -- ! cmpb 000001,000000 -> n0z0v0c0; (000001)
|
8234 |
|
|
d=000000 -- !
|
8235 |
|
|
d=000010 -- ! cmpb 000377,000000 -> n1z0v0c0; (000377)
|
8236 |
|
|
d=000000 -- !
|
8237 |
|
|
d=000011 -- ! cmpb 000000,000001 -> n1z0v0c1; (000377+C)
|
8238 |
|
|
d=000001 -- !
|
8239 |
|
|
d=000004 -- ! cmpb 000001,000001 -> n0z1v0c0; (000000)
|
8240 |
|
|
d=000001 -- !
|
8241 |
|
|
d=000010 -- ! cmpb 000377,000001 -> n1z0v0c0; (000376)
|
8242 |
|
|
d=000001 -- !
|
8243 |
|
|
d=000011 -- ! cmpb 000176,000177 -> n1z0v0c1; (000377+C)
|
8244 |
|
|
d=000177 -- !
|
8245 |
|
|
d=000004 -- ! cmpb 000177,000177 -> n0z1v0c0; (000000)
|
8246 |
|
|
d=000177 -- !
|
8247 |
|
|
d=000002 -- ! cmpb 000200,000177 -> n0z0v1c0; (000001)
|
8248 |
|
|
d=000177 -- !
|
8249 |
|
|
d=000011 -- ! cmpb 000001,000177 -> n1z0v0c1; (000202+C)
|
8250 |
|
|
d=000177 -- !
|
8251 |
|
|
d=000010 -- ! cmpb 000377,000177 -> n1z0v0c0; (000200)
|
8252 |
|
|
d=000177 -- !
|
8253 |
|
|
d=000013 -- ! cmpb 000177,000200 -> n1z0v1c1; (000377+C)
|
8254 |
|
|
d=000200 -- !
|
8255 |
|
|
d=000004 -- ! cmpb 000200,000200 -> n0z1v0c0; (000000)
|
8256 |
|
|
d=000200 -- !
|
8257 |
|
|
d=000000 -- ! cmpb 000201,000200 -> n0z0v0c0; (000001)
|
8258 |
|
|
d=000200 -- !
|
8259 |
|
|
d=000013 -- ! cmpb 000001,000200 -> n1z0v1c1; (000201+C)
|
8260 |
|
|
d=000200 -- !
|
8261 |
|
|
d=000000 -- ! cmpb 000377,000200 -> n0z0v0c0; (000177)
|
8262 |
|
|
d=000200 -- !
|
8263 |
|
|
d=000001 -- ! cmpb 000000,000377 -> n0z0v0c1; (000001+C)
|
8264 |
|
|
d=000377 -- !
|
8265 |
|
|
d=000001 -- ! cmpb 000001,000377 -> n0z0v0c1; (000002+C)
|
8266 |
|
|
d=000377 -- !
|
8267 |
|
|
d=000004 -- ! cmpb 000377,000377 -> n0z1v0c0; (000000)
|
8268 |
|
|
d=000377 -- !
|
8269 |
|
|
#-----------------------------------------------------------------------------
|
8270 |
|
|
C Setup code 47 [base 13400] (pipeline torture tests)
|
8271 |
|
|
#
|
8272 |
|
|
wal 013400 -- data:
|
8273 |
|
|
wmi 000077 -- marker
|
8274 |
|
|
wal 013402 -- code 1:
|
8275 |
|
|
bwm 13
|
8276 |
|
|
016727 -- mov -6(pc),(pc)+ ;
|
8277 |
|
|
177772
|
8278 |
|
|
000000 -- halt ; will be overwritten
|
8279 |
|
|
016737 -- mov -10(pc),@(pc)+ ;
|
8280 |
|
|
177770
|
8281 |
|
|
013400
|
8282 |
|
|
005200 -- inc r0 ;
|
8283 |
|
|
#13420
|
8284 |
|
|
010317 -- mov r3,(pc) ; will overwrite next instruction
|
8285 |
|
|
000000 -- halt ; will be overwritten
|
8286 |
|
|
005200 -- inc r0 ;
|
8287 |
|
|
010447 -- mov r4,-(pc) ; will overwrite itself
|
8288 |
|
|
005200 -- inc r0 ;
|
8289 |
|
|
000000 -- halt ;
|
8290 |
|
|
#
|
8291 |
|
|
wal 013440 -- code 2: (pipeline tester adapted from KDJ11A.MAC)
|
8292 |
|
|
bwm 15
|
8293 |
|
|
012717 -- mov (pc)+,(pc) ; will replace jmp (r1) with nop
|
8294 |
|
|
000240 -- nop
|
8295 |
|
|
000111 -- jmp (r1)
|
8296 |
|
|
012717 -- mov (pc)+,(pc) ; will replace jmp (r1) with nop
|
8297 |
|
|
000240 -- nop
|
8298 |
|
|
000111 -- jmp (r1)
|
8299 |
|
|
012717 -- mov (pc)+,(pc) ; will replace jmp (r1) with nop
|
8300 |
|
|
000240 -- nop
|
8301 |
|
|
#13460
|
8302 |
|
|
000111 -- jmp (r1)
|
8303 |
|
|
012717 -- mov (pc)+,(pc) ; will replace jmp (r1) with nop
|
8304 |
|
|
000240 -- nop
|
8305 |
|
|
000111 -- jmp (r1)
|
8306 |
|
|
000000 -- halt ; should halt here !
|
8307 |
|
|
000000 -- halt ;
|
8308 |
|
|
000000 -- halt ; should not jmp here !
|
8309 |
|
|
#
|
8310 |
|
|
C Exec code 47 (pipeline torture tests)
|
8311 |
|
|
C Exec test 47.1 (some self-modifying code, use (pc)+, (pc), -(pc)):
|
8312 |
|
|
#
|
8313 |
|
|
wr0 000000 -- r0=0
|
8314 |
|
|
wr1 000000 -- r1=0
|
8315 |
|
|
wr2 000000 -- r2=0
|
8316 |
|
|
wr3 005201 -- r3= inc r1
|
8317 |
|
|
wr4 005202 -- r4= inc r2
|
8318 |
|
|
stapc 013402 -- start @ 13402
|
8319 |
|
|
wtgo
|
8320 |
|
|
rpc d=013434 -- ! pc
|
8321 |
|
|
rr0 d=000003 -- ! r0
|
8322 |
|
|
rr1 d=000001 -- ! r1
|
8323 |
|
|
rr2 d=000001 -- ! r2
|
8324 |
|
|
rr3 d=005201 -- ! r3
|
8325 |
|
|
rr4 d=005202 -- ! r4
|
8326 |
|
|
#
|
8327 |
|
|
wal 013400 -- check data area:
|
8328 |
|
|
rmi d=177772 -- ! new marker ; written by mov -10(pc),@(pc)+
|
8329 |
|
|
wal 013402 -- check code area:
|
8330 |
|
|
brm 13
|
8331 |
|
|
d=016727 -- ! mov -6(pc),(pc)+ ;
|
8332 |
|
|
d=177772 -- !
|
8333 |
|
|
d=000077 -- ! ; written by mov -6(pc),(pc)+
|
8334 |
|
|
d=016737 -- ! mov -10(pc),@(pc)+;
|
8335 |
|
|
d=177770 -- !
|
8336 |
|
|
d=013400 -- !
|
8337 |
|
|
d=005200 -- ! inc r0 ;
|
8338 |
|
|
#13320
|
8339 |
|
|
d=010317 -- ! mov r3,(pc) ;
|
8340 |
|
|
d=005201 -- ! inc r1 ; written by mov r3,(pc); executed
|
8341 |
|
|
d=005200 -- ! inc r0 ;
|
8342 |
|
|
d=005202 -- ! inc r2 ; written by mov r4,-(pc); executed
|
8343 |
|
|
d=005200 -- ! inc r0 ;
|
8344 |
|
|
d=000000 -- ! halt ;
|
8345 |
|
|
#
|
8346 |
|
|
C Exec test 47.1 (pipeline tester adapted from KDJ11A.MAC, test 121, p. 70)
|
8347 |
|
|
#
|
8348 |
|
|
wr1 013474 -- r1=13474 (alternate halt)
|
8349 |
|
|
stapc 013440 -- start @ 13440
|
8350 |
|
|
wtgo
|
8351 |
|
|
rpc d=013472 -- ! pc
|
8352 |
|
|
wal 013440 -- check code area:
|
8353 |
|
|
brm 13
|
8354 |
|
|
d=012717 -- ! mov (pc)+,(pc) ;
|
8355 |
|
|
d=000240 -- ! nop
|
8356 |
|
|
d=000240 -- ! nop ; written; executed
|
8357 |
|
|
d=012717 -- ! mov (pc)+,(pc) ;
|
8358 |
|
|
d=000240 -- ! nop
|
8359 |
|
|
d=000240 -- ! nop ; written; executed
|
8360 |
|
|
d=012717 -- ! mov (pc)+,(pc) ;
|
8361 |
|
|
d=000240 -- ! nop
|
8362 |
|
|
#13360
|
8363 |
|
|
d=000240 -- ! nop ; written; executed
|
8364 |
|
|
d=012717 -- ! mov (pc)+,(pc) ;
|
8365 |
|
|
d=000240 -- ! nop
|
8366 |
|
|
d=000240 -- ! nop ; written; executed
|
8367 |
|
|
d=000000 -- ! halt ;
|
8368 |
|
|
#-----------------------------------------------------------------------------
|
8369 |
|
|
C Setup code 50 [base 13500] (check that all reserved instructions trap to 10)
|
8370 |
|
|
#
|
8371 |
|
|
wal 013500 -- code (to be single stepped...)
|
8372 |
|
|
bwm 17
|
8373 |
|
|
000007 -- 000007
|
8374 |
|
|
000010 -- 000010-000077
|
8375 |
|
|
000077 --
|
8376 |
|
|
000210 -- 000210-000227
|
8377 |
|
|
000227 --
|
8378 |
|
|
007000 -- 007000-007777
|
8379 |
|
|
007777 --
|
8380 |
|
|
075000 -- 075000-076777
|
8381 |
|
|
#13420
|
8382 |
|
|
076777 --
|
8383 |
|
|
106400 -- 106400-106477
|
8384 |
|
|
106477 --
|
8385 |
|
|
106700 -- 106700-106777
|
8386 |
|
|
106777 --
|
8387 |
|
|
107000 -- 107000-107777
|
8388 |
|
|
107777 --
|
8389 |
|
|
170000 -- 170000-177777 (no FPU)
|
8390 |
|
|
#13440
|
8391 |
|
|
177777 --
|
8392 |
|
|
#
|
8393 |
|
|
C Exec code 50 (check that all reserved instructions trap to 10)
|
8394 |
|
|
C Test odd address abort
|
8395 |
|
|
#
|
8396 |
|
|
rst -- console reset
|
8397 |
|
|
wps 000000 -- clear psw
|
8398 |
|
|
wal 001374 -- clean stack
|
8399 |
|
|
bwm 2
|
8400 |
|
|
000000 --
|
8401 |
|
|
000000 --
|
8402 |
|
|
wsp 001400 -- sp=1400
|
8403 |
|
|
wpc 013500 -- pc=13500
|
8404 |
|
|
step -- step (000007): trap 10 [[s:2]]
|
8405 |
|
|
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
|
8406 |
|
|
rsp d=001374 -- ! sp=1374
|
8407 |
|
|
#
|
8408 |
|
|
wsp 001400 -- sp=1400
|
8409 |
|
|
wpc 013502 -- pc=13502
|
8410 |
|
|
step -- step (000010): trap 10 [[s:2]]
|
8411 |
|
|
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
|
8412 |
|
|
rsp d=001374 -- ! sp=1374
|
8413 |
|
|
#
|
8414 |
|
|
wsp 001400 -- sp=1400
|
8415 |
|
|
wpc 013504 -- pc=13504
|
8416 |
|
|
step -- step (000077): trap 10 [[s:2]]
|
8417 |
|
|
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
|
8418 |
|
|
rsp d=001374 -- ! sp=1374
|
8419 |
|
|
#
|
8420 |
|
|
wsp 001400 -- sp=1400
|
8421 |
|
|
wpc 013506 -- pc=13506
|
8422 |
|
|
step -- step (000210): trap 10 [[s:2]]
|
8423 |
|
|
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
|
8424 |
|
|
rsp d=001374 -- ! sp=1374
|
8425 |
|
|
#
|
8426 |
|
|
wsp 001400 -- sp=1400
|
8427 |
|
|
wpc 013510 -- pc=13510
|
8428 |
|
|
step -- step (000227): trap 10 [[s:2]]
|
8429 |
|
|
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
|
8430 |
|
|
rsp d=001374 -- ! sp=1374
|
8431 |
|
|
#
|
8432 |
|
|
wsp 001400 -- sp=1400
|
8433 |
|
|
wpc 013512 -- pc=13512
|
8434 |
|
|
step -- step (007000): trap 10 [[s:2]]
|
8435 |
|
|
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
|
8436 |
|
|
rsp d=001374 -- ! sp=1374
|
8437 |
|
|
#
|
8438 |
|
|
wsp 001400 -- sp=1400
|
8439 |
|
|
wpc 013514 -- pc=13514
|
8440 |
|
|
step -- step (007777): trap 10 [[s:2]]
|
8441 |
|
|
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
|
8442 |
|
|
rsp d=001374 -- ! sp=1374
|
8443 |
|
|
#
|
8444 |
|
|
wsp 001400 -- sp=1400
|
8445 |
|
|
wpc 013516 -- pc=13516
|
8446 |
|
|
step -- step (075000): trap 10 [[s:2]]
|
8447 |
|
|
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
|
8448 |
|
|
rsp d=001374 -- ! sp=1374
|
8449 |
|
|
#
|
8450 |
|
|
wsp 001400 -- sp=1400
|
8451 |
|
|
wpc 013520 -- pc=13520
|
8452 |
|
|
step -- step (076777): trap 10 [[s:2]]
|
8453 |
|
|
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
|
8454 |
|
|
rsp d=001374 -- ! sp=1374
|
8455 |
|
|
#
|
8456 |
|
|
wsp 001400 -- sp=1400
|
8457 |
|
|
wpc 013522 -- pc=13522
|
8458 |
|
|
step -- step (106400): trap 10 [[s:2]]
|
8459 |
|
|
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
|
8460 |
|
|
rsp d=001374 -- ! sp=1374
|
8461 |
|
|
#
|
8462 |
|
|
wsp 001400 -- sp=1400
|
8463 |
|
|
wpc 013524 -- pc=13524
|
8464 |
|
|
step -- step (106477): trap 10 [[s:2]]
|
8465 |
|
|
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
|
8466 |
|
|
rsp d=001374 -- ! sp=1374
|
8467 |
|
|
#
|
8468 |
|
|
wsp 001400 -- sp=1400
|
8469 |
|
|
wpc 013526 -- pc=13526
|
8470 |
|
|
step -- step (106700): trap 10 [[s:2]]
|
8471 |
|
|
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
|
8472 |
|
|
rsp d=001374 -- ! sp=1374
|
8473 |
|
|
#
|
8474 |
|
|
wsp 001400 -- sp=1400
|
8475 |
|
|
wpc 013530 -- pc=13530
|
8476 |
|
|
step -- step (106777): trap 10 [[s:2]]
|
8477 |
|
|
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
|
8478 |
|
|
rsp d=001374 -- ! sp=1374
|
8479 |
|
|
#
|
8480 |
|
|
wsp 001400 -- sp=1400
|
8481 |
|
|
wpc 013532 -- pc=13532
|
8482 |
|
|
step -- step (107000): trap 10 [[s:2]]
|
8483 |
|
|
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
|
8484 |
|
|
rsp d=001374 -- ! sp=1374
|
8485 |
|
|
#
|
8486 |
|
|
wsp 001400 -- sp=1400
|
8487 |
|
|
wpc 013534 -- pc=13534
|
8488 |
|
|
step -- step (107777): trap 10 [[s:2]]
|
8489 |
|
|
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
|
8490 |
|
|
rsp d=001374 -- ! sp=1374
|
8491 |
|
|
#
|
8492 |
|
|
wsp 001400 -- sp=1400
|
8493 |
|
|
wpc 013536 -- pc=13536
|
8494 |
|
|
step -- step (170000): trap 10 [[s:2]]
|
8495 |
|
|
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
|
8496 |
|
|
rsp d=001374 -- ! sp=1374
|
8497 |
|
|
#
|
8498 |
|
|
wsp 001400 -- sp=1400
|
8499 |
|
|
wpc 013540 -- pc=13540
|
8500 |
|
|
step -- step (177777): trap 10 [[s:2]]
|
8501 |
|
|
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
|
8502 |
|
|
rsp d=001374 -- ! sp=1374
|
8503 |
|
|
#-----------------------------------------------------------------------------
|
8504 |
|
|
#
|
8505 |
|
|
C Verify trap catchers integrity
|
8506 |
|
|
#
|
8507 |
|
|
wal 000004 -- vectors: 4...34 (trap catcher)
|
8508 |
|
|
brm 14
|
8509 |
|
|
d=000006 -- ! PC:06 ; vector 4
|
8510 |
|
|
d=000000 -- ! PS:0
|
8511 |
|
|
d=000012 -- ! PC:12 ; vector 10
|
8512 |
|
|
d=000000 -- ! PS:0
|
8513 |
|
|
d=000016 -- ! PC:16 ; vector 14 (T bit; BPT)
|
8514 |
|
|
d=000000 -- ! PS:0
|
8515 |
|
|
d=000022 -- ! PC:22 ; vector 20 (IOT)
|
8516 |
|
|
d=000000 -- ! PS:0
|
8517 |
|
|
d=000026 -- ! PC:26 ; vector 24 (Power fail, not used)
|
8518 |
|
|
d=000000 -- ! PS:0
|
8519 |
|
|
d=000032 -- ! PC:32 ; vector 30 (EMT)
|
8520 |
|
|
d=000000 -- ! PS:0
|
8521 |
|
|
d=000036 -- ! PC:36 ; vector 34 (TRAP)
|
8522 |
|
|
d=000000 -- ! PS:0
|
8523 |
|
|
wal 000240 -- vectors: 240,244,250 (trap catcher)
|
8524 |
|
|
brm 6
|
8525 |
|
|
d=000242 -- ! PC:242 ; vector 240 (PIRQ)
|
8526 |
|
|
d=000000 -- ! PS:0
|
8527 |
|
|
d=000246 -- ! PC:246 ; vector 244 (FPU)
|
8528 |
|
|
d=000000 -- ! PS:0
|
8529 |
|
|
d=000252 -- ! PC:252 ; vector 250 (MMU)
|
8530 |
|
|
d=000000 -- ! PS:0
|
8531 |
|
|
#
|
8532 |
|
|
C Verify setup MMU
|
8533 |
|
|
# to avoid seeing AIB bits:
|
8534 |
|
|
# 1. check ARs; 2. re-write ARs to clear AIBs in DRs; 3. check DRs
|
8535 |
|
|
#
|
8536 |
|
|
wal 172340 -- kernel I space AR
|
8537 |
|
|
brm 8
|
8538 |
|
|
d=000000 -- ! 0
|
8539 |
|
|
d=000200 -- ! 200 020000 base
|
8540 |
|
|
d=000400 -- ! 400 040000 base
|
8541 |
|
|
d=000600 -- ! 600 060000 base
|
8542 |
|
|
d=001000 -- ! 1000 100000 base
|
8543 |
|
|
d=001200 -- ! 1200 120000 base
|
8544 |
|
|
d=001400 -- ! 1400 140000 base
|
8545 |
|
|
d=177600 -- !176000 (map to I/O page)
|
8546 |
|
|
#
|
8547 |
|
|
wal 172340 -- kernel I space AR
|
8548 |
|
|
bwm 8
|
8549 |
|
|
000000 -- 0
|
8550 |
|
|
000200 -- 200 020000 base
|
8551 |
|
|
000400 -- 400 040000 base
|
8552 |
|
|
000600 -- 600 060000 base
|
8553 |
|
|
001000 -- 1000 100000 base
|
8554 |
|
|
001200 -- 1200 120000 base
|
8555 |
|
|
001400 -- 1400 140000 base
|
8556 |
|
|
177600 -- 176000 (map to I/O page)
|
8557 |
|
|
#
|
8558 |
|
|
wal 172300 -- kernel I space DR
|
8559 |
|
|
brm 8
|
8560 |
|
|
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r)
|
8561 |
|
|
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r)
|
8562 |
|
|
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r)
|
8563 |
|
|
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r)
|
8564 |
|
|
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r)
|
8565 |
|
|
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r)
|
8566 |
|
|
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r)
|
8567 |
|
|
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r)
|
8568 |
|
|
#
|
8569 |
|
|
wal 000000 -- last cmd shouldn't be 21 or 23 ...
|