OpenCores
URL https://opencores.org/ocsvn/w11/w11/trunk

Subversion Repositories w11

[/] [w11/] [tags/] [w11a_V0.7/] [tools/] [bin/] [tbrun_tbw] - Blame information for rev 36

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 28 wfjm
#!/bin/bash
2 29 wfjm
# $Id: tbrun_tbw 641 2015-02-01 22:12:15Z mueller $
3 28 wfjm
#
4 29 wfjm
# Copyright 2014- by Walter F.J. Mueller 
5
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
6
#
7 28 wfjm
#  Revision History:
8
# Date         Rev Version  Comment
9
# 2014-12-27   622   1.0.1  add --stack, --ghw, --tbw, --pcom
10
# 2014-12-26   621   1.0    Initial version
11
#
12
 
13
docmd ()
14
{
15
  echo "$1"
16
  if [[ -z "$optdry" ]] ; then
17
    eval "$1"
18
  fi
19
}
20
 
21
optdry=""
22
optlsuf=""
23
optstack=""
24
optghw=""
25
opttbw=""
26
optpcom=""
27
 
28
# handle options
29
while (( $# > 0 )) ; do
30
  case $1 in
31
    -dry|--dry)     optdry=$1    ; shift 1 ;;
32
    -lsuf|--lsuf)   optlsuf=$2   ; shift 2 ;;
33
    -stack|--stack) optstack=$2  ; shift 2 ;;
34
    -ghw|--ghw)     optghw=$2    ; shift 2 ;;
35
    -tbw|--tbw)     opttbw=$2    ; shift 2 ;;
36
    -pcom|--pcom)   optpcom=$1   ; shift 1 ;;
37
    -*)             echo "tbrun_tbw-E: invalid option '$1'"; exit 1 ;;
38
    *)     break;;
39
  esac
40
done
41
 
42
tbench=$1
43
stimfile=$2
44
 
45
# complain if no tbench defined
46
if (( $# == 0 )) ; then
47
  echo "Usage: tbrun_tbw [opts] testbench [stimfile]"
48
  echo "  Options:"
49
  echo "  --dry             dry run, print commands, don't execute"
50
  echo "  --lsuf  suff      use '_.log' as suffix for log file"
51
  echo "  --stack nnn       use  as ghdl stack size"
52
  echo "  --ghw   fname     write ghw file with name '.ghw"
53
  echo "  --tbw   opts      append  to tbw command"
54
  exit 1
55
fi
56
 
57
# check for ISim
58
isisim=""
59
if [[ $tbench =~ _ISim ]] ; then
60
  isisim=true
61
fi
62
 
63
# check for ghdl with _ssim, _fsim, _tsim
64
isghdlxsim=""
65
if [[ "$isisim" == "" ]] && [[ $tbench =~ _[sft]sim$ ]] ; then
66
  isghdlxsim=true
67
  logsuff=""
68
fi
69
 
70
# issue makes
71
if [[ -n "$isghdlxsim" ]] ; then docmd "make ghdl_tmp_clean"; fi
72
docmd "make $tbench"
73
exitstat=$?
74
if [[ -n "$isghdlxsim" ]] ; then docmd "make ghdl_tmp_clean"; fi
75
 
76
if (( $exitstat > 0 )) ; then exit $exitstat; fi
77
 
78
# determine logfile name
79
logsuff="_dsim"
80
if [[ $tbench =~ _[sft]sim$ ]] ; then logsuff=""; fi
81
if [[ -n "$optlsuf" ]] ;      then logsuff="_$optlsuf"; fi
82
 
83
logfile="${tbench}${logsuff}.log"
84
 
85
# now build actual test command (a tbw|filter|tee|egrep pipe)
86
cmd="time tbw $tbench"
87
if [[ -n "$isisim" ]] ; then    cmd+=" -run"; fi
88
if [[ -n "$stimfile" ]] ; then  cmd+=" $stimfile"; fi
89
if [[ -n "$opttbw" ]] ; then    cmd+=" $opttbw"; fi
90
if [[ -n "$optstack" ]] ; then  cmd+=" --stack-max-size=$optstack"; fi
91
if [[ -n "$optghw" ]] ; then    cmd+=" --wave=$optghw.ghw"; fi
92
cmd+=" 2>&1"
93
if [[ -z "$isisim" ]] ; then    cmd+=" | ghdl_assert_filter"; fi
94
cmd+=" | tee $logfile"
95
 
96
pcomtag=""
97
if [[ -n "$optpcom" ]] ; then pcomtag="^C|"; fi
98
# FAIL, PASS, DONE come from tbs; ERROR comes from ISim
99
cmd+=" | egrep \"(${pcomtag}-[EFW]:|ERROR|FAIL|PASS|DONE)\""
100
docmd "$cmd"

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.