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#!/usr/bin/perl -w
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# $Id: tmuconv 676 2015-05-09 16:31:54Z mueller $
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#
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# Copyright 2008-2015 by Walter F.J. Mueller
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#
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# This program is free software; you may redistribute and/or modify it under
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# the terms of the GNU General Public License as published by the Free
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# Software Foundation, either version 2, or at your option any later version.
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#
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# This program is distributed in the hope that it will be useful, but
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# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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# for complete details.
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#
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# Revision History:
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# Date Rev Version Comment
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# 2010-10-22 334 1.0.9 adapt to ibus V2 signals: req,we,dip->aval,re,we,rmw
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# 2010-06-26 309 1.0.8 add ibimres.cacc/racc handling
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# 2010-04-26 284 1.0.7 add error check for GetOptions
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# 2009-09-19 240 1.0.6 add more VFETCH addr defs; add 2nd DL11 defs
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# 2009-06-04 223 1.0.5 add IIST and PC11 defs
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# 2009-05-03 212 1.0.4 add defs for mmu par/pdr's and some unibus dev's
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# 2008-12-14 177 1.0.3 add -t_ru; use dp_ireg_we_last; add ibus names
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# 2008-11-30 174 1.0.2 SPUSH and VFETCH tags for em cycles; psw in id lines
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# 2008-04-25 138 1.0.1 show ccc/scc for code 000257/000277 in disassembler
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# 2008-04-19 137 1.0 Initial version
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#
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# Current fields in tmu_ofile:
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# clkcycle:d
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# cpu:o
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# dp.pc:o
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# dp.psw:o
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# dp.ireg:o
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# dp.ireg_we:b
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# dp.ireg_we_last:b
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# dp.dsrc:o
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# dp.ddst:o
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# dp.dtmp:o
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# dp.dres:o
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# dp.gpr_adst:o
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# dp.gpr_mode:o
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# dp.gpr_bytop:b
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# dp.gpr_we:b
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# vm.ibmreq.aval:b
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# vm.ibmreq.re:b
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# vm.ibmreq.we:b
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# vm.ibmreq.rmw:b
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# vm.ibmreq.be0:b
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# vm.ibmreq.be1:b
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# vm.ibmreq.cacc:b
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# vm.ibmreq.racc:b
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# vm.ibmreq.addr:o
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# vm.ibmreq.din:o
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# vm.ibsres.ack:b
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# vm.ibsres.busy:b
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# vm.ibsres.dout:o
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# co.cpugo:b
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# co.cpususp:b
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# co.suspint:b
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# co.suspext:b
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# sy.emmreq.req:b
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# sy.emmreq.we:b
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# sy.emmreq.be:b
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# sy.emmreq.cancel:b
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# sy.emmreq.addr:o
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# sy.emmreq.din:o
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# sy.emsres.ack_r:b
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# sy.emsres.ack_w:b
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# sy.emsres.dout:o
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# sy.chit:b
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#
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use 5.005; # require Perl 5.005 or higher
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use strict; # require strict checking
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use FileHandle;
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use Getopt::Long;
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my %opts = ();
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GetOptions(\%opts, "help", "dump", "cdump",
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"t_id", "t_ru", "t_em", "t_ib")
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or die "bad options";
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sub print_help;
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sub do_file;
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sub code2mnemo;
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sub regmod;
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my @var_name;
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my @var_type;
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my @var_dec;
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my @var_oct;
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my %name;
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my @val_curr_text;
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my @val_curr;
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my @val_last;
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my @reg_05 = ("------","------","------","------","------","------", # set 0
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"------","------","------","------","------","------",); # set 1
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my @reg_sp = ("------","------","------","------"); # ksp,ssp,???,usp
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my $ind_dp_pc;
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my $ind_dp_psw;
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my $ind_dp_ireg;
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my $ind_dp_ireg_we;
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my $ind_dp_ireg_we_last;
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my $ind_dp_dres;
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my $ind_dp_gpr_adst;
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my $ind_dp_gpr_mode;
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my $ind_dp_gpr_bytop;
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my $ind_dp_gpr_we;
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my $ind_vm_ibmreq_aval;
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my $ind_vm_ibmreq_re;
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my $ind_vm_ibmreq_we;
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my $ind_vm_ibmreq_rmw;
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my $ind_vm_ibmreq_be0;
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my $ind_vm_ibmreq_be1;
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my $ind_vm_ibmreq_cacc;
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my $ind_vm_ibmreq_racc;
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my $ind_vm_ibmreq_addr;
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my $ind_vm_ibmreq_din;
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my $ind_vm_ibsres_ack;
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my $ind_vm_ibsres_busy;
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my $ind_vm_ibsres_dout;
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my $ind_sy_emmreq_req;
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my $ind_sy_emmreq_we;
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my $ind_sy_emmreq_be;
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my $ind_sy_emmreq_cancel;
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my $ind_sy_emmreq_addr;
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my $ind_sy_emmreq_din;
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my $ind_sy_emsres_ack_r;
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my $ind_sy_emsres_ack_w;
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my $ind_sy_emsres_dout;
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my $ind_sy_chit;
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139 |
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my @pdp11_opcode_tbl = (
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{code=>0000000, mask=>0000000, name=>"halt", type=>"0arg"},
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142 |
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{code=>0000001, mask=>0000000, name=>"wait", type=>"0arg"},
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143 |
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{code=>0000002, mask=>0000000, name=>"rti ", type=>"0arg"},
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{code=>0000003, mask=>0000000, name=>"bpt ", type=>"0arg"},
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{code=>0000004, mask=>0000000, name=>"iot ", type=>"0arg"},
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{code=>0000005, mask=>0000000, name=>"reset",type=>"0arg"},
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{code=>0000006, mask=>0000000, name=>"rtt ", type=>"0arg"},
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{code=>0000007, mask=>0000000, name=>"!!mfpt", type=>"0arg"},
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149 |
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{code=>0000100, mask=>0000077, name=>"jmp ", type=>"1arg"},
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150 |
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{code=>0000200, mask=>0000007, name=>"rts ", type=>"1reg"},
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151 |
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{code=>0000230, mask=>0000007, name=>"spl ", type=>"spl"},
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152 |
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{code=>0000240, mask=>0000017, name=>"cl", type=>"ccop"},
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153 |
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{code=>0000260, mask=>0000017, name=>"se", type=>"ccop"},
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154 |
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{code=>0000300, mask=>0000077, name=>"swap", type=>"1arg"},
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{code=>0000400, mask=>0000377, name=>"br ", type=>"br"},
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156 |
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{code=>0001000, mask=>0000377, name=>"bne ", type=>"br"},
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157 |
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{code=>0001400, mask=>0000377, name=>"beq ", type=>"br"},
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158 |
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{code=>0002000, mask=>0000377, name=>"bge ", type=>"br"},
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159 |
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{code=>0002400, mask=>0000377, name=>"blt ", type=>"br"},
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160 |
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{code=>0003000, mask=>0000377, name=>"bgt ", type=>"br"},
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161 |
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{code=>0003400, mask=>0000377, name=>"ble ", type=>"br"},
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162 |
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{code=>0004000, mask=>0000777, name=>"jsr ", type=>"jsr"},
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163 |
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{code=>0005000, mask=>0000077, name=>"clr ", type=>"1arg"},
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164 |
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{code=>0005100, mask=>0000077, name=>"com ", type=>"1arg"},
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165 |
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{code=>0005200, mask=>0000077, name=>"inc ", type=>"1arg"},
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166 |
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{code=>0005300, mask=>0000077, name=>"dec ", type=>"1arg"},
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167 |
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{code=>0005400, mask=>0000077, name=>"neg ", type=>"1arg"},
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168 |
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{code=>0005500, mask=>0000077, name=>"adc ", type=>"1arg"},
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169 |
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{code=>0005600, mask=>0000077, name=>"sbc ", type=>"1arg"},
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170 |
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{code=>0005700, mask=>0000077, name=>"tst ", type=>"1arg"},
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171 |
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{code=>0006000, mask=>0000077, name=>"ror ", type=>"1arg"},
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172 |
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{code=>0006100, mask=>0000077, name=>"rol ", type=>"1arg"},
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173 |
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{code=>0006200, mask=>0000077, name=>"asr ", type=>"1arg"},
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174 |
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{code=>0006300, mask=>0000077, name=>"asl ", type=>"1arg"},
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175 |
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{code=>0006400, mask=>0000077, name=>"mark", type=>"mark"},
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176 |
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{code=>0006500, mask=>0000077, name=>"mfpi", type=>"1arg"},
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177 |
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{code=>0006600, mask=>0000077, name=>"mtpi", type=>"1arg"},
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178 |
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{code=>0006700, mask=>0000077, name=>"sxt ", type=>"1arg"},
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179 |
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{code=>0007000, mask=>0000077, name=>"!!csm", type=>"1arg"},
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180 |
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{code=>0007200, mask=>0000077, name=>"!!tstset",type=>"1arg"},
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181 |
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{code=>0007300, mask=>0000077, name=>"!!wrtlck",type=>"1arg"},
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182 |
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{code=>0010000, mask=>0007777, name=>"mov ", type=>"2arg"},
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183 |
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{code=>0020000, mask=>0007777, name=>"cmp ", type=>"2arg"},
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184 |
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{code=>0030000, mask=>0007777, name=>"bit ", type=>"2arg"},
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185 |
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{code=>0040000, mask=>0007777, name=>"bic ", type=>"2arg"},
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186 |
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{code=>0050000, mask=>0007777, name=>"bis ", type=>"2arg"},
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187 |
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{code=>0060000, mask=>0007777, name=>"add ", type=>"2arg"},
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188 |
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{code=>0070000, mask=>0000777, name=>"mul ", type=>"rdst"},
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189 |
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{code=>0071000, mask=>0000777, name=>"div ", type=>"rdst"},
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190 |
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{code=>0072000, mask=>0000777, name=>"ash ", type=>"rdst"},
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191 |
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{code=>0073000, mask=>0000777, name=>"ashc", type=>"rdst"},
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192 |
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{code=>0074000, mask=>0000777, name=>"xor ", type=>"rdst"},
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193 |
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{code=>0077000, mask=>0000777, name=>"sob ", type=>"sob"},
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194 |
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{code=>0100000, mask=>0000377, name=>"bpl ", type=>"br"},
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195 |
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{code=>0100400, mask=>0000377, name=>"bmi ", type=>"br"},
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196 |
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{code=>0101000, mask=>0000377, name=>"bhi ", type=>"br"},
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197 |
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{code=>0101400, mask=>0000377, name=>"blos", type=>"br"},
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198 |
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{code=>0102000, mask=>0000377, name=>"bvc ", type=>"br"},
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199 |
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{code=>0102400, mask=>0000377, name=>"bvs ", type=>"br"},
|
200 |
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{code=>0103000, mask=>0000377, name=>"bcc ", type=>"br"},
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201 |
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{code=>0103400, mask=>0000377, name=>"bcs ", type=>"br"},
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202 |
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{code=>0104000, mask=>0000377, name=>"emt ", type=>"trap"},
|
203 |
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{code=>0104400, mask=>0000377, name=>"trap", type=>"trap"},
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204 |
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{code=>0105000, mask=>0000077, name=>"clrb", type=>"1arg"},
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205 |
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{code=>0105100, mask=>0000077, name=>"comb", type=>"1arg"},
|
206 |
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{code=>0105200, mask=>0000077, name=>"incb", type=>"1arg"},
|
207 |
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{code=>0105300, mask=>0000077, name=>"decb", type=>"1arg"},
|
208 |
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{code=>0105400, mask=>0000077, name=>"negb", type=>"1arg"},
|
209 |
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{code=>0105500, mask=>0000077, name=>"adcb", type=>"1arg"},
|
210 |
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{code=>0105600, mask=>0000077, name=>"sbcb", type=>"1arg"},
|
211 |
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{code=>0105700, mask=>0000077, name=>"tstb", type=>"1arg"},
|
212 |
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{code=>0106000, mask=>0000077, name=>"rorb", type=>"1arg"},
|
213 |
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{code=>0106100, mask=>0000077, name=>"rolb", type=>"1arg"},
|
214 |
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{code=>0106200, mask=>0000077, name=>"asrb", type=>"1arg"},
|
215 |
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{code=>0106300, mask=>0000077, name=>"aslb", type=>"1arg"},
|
216 |
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{code=>0106400, mask=>0000077, name=>"!!mtps", type=>"1arg"},
|
217 |
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{code=>0106500, mask=>0000077, name=>"mfpd", type=>"1arg"},
|
218 |
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{code=>0106600, mask=>0000077, name=>"mtpd", type=>"1arg"},
|
219 |
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{code=>0106700, mask=>0000077, name=>"!!mfps", type=>"1arg"},
|
220 |
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{code=>0110000, mask=>0007777, name=>"movb", type=>"2arg"},
|
221 |
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{code=>0120000, mask=>0007777, name=>"cmpb", type=>"2arg"},
|
222 |
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{code=>0130000, mask=>0007777, name=>"bitb", type=>"2arg"},
|
223 |
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{code=>0140000, mask=>0007777, name=>"bicb", type=>"2arg"},
|
224 |
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{code=>0150000, mask=>0007777, name=>"bisb", type=>"2arg"},
|
225 |
|
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{code=>0160000, mask=>0007777, name=>"sub ", type=>"2arg"},
|
226 |
|
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{code=>0170000, mask=>0000000, name=>"!!cfcc", type=>"0arg"},
|
227 |
|
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{code=>0170001, mask=>0000000, name=>"!!setf", type=>"0arg"},
|
228 |
|
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{code=>0170011, mask=>0000000, name=>"!!setd", type=>"0arg"},
|
229 |
|
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{code=>0170002, mask=>0000000, name=>"!!seti", type=>"0arg"},
|
230 |
|
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{code=>0170012, mask=>0000000, name=>"!!setl", type=>"0arg"},
|
231 |
|
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{code=>0170100, mask=>0000077, name=>"!!ldfps",type=>"1fpp"},
|
232 |
|
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{code=>0170200, mask=>0000077, name=>"!!stfps",type=>"1fpp"},
|
233 |
|
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{code=>0170300, mask=>0000077, name=>"!!stst", type=>"1fpp"},
|
234 |
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{code=>0170400, mask=>0000077, name=>"!!clrf", type=>"1fpp"},
|
235 |
|
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{code=>0170500, mask=>0000077, name=>"!!tstf", type=>"1fpp"},
|
236 |
|
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{code=>0170600, mask=>0000077, name=>"!!absf", type=>"1fpp"},
|
237 |
|
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{code=>0170700, mask=>0000077, name=>"!!negf", type=>"1fpp"},
|
238 |
|
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{code=>0171000, mask=>0000377, name=>"!!mulf", type=>"rfpp"},
|
239 |
|
|
{code=>0171400, mask=>0000377, name=>"!!modf", type=>"rfpp"},
|
240 |
|
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{code=>0172000, mask=>0000377, name=>"!!addf", type=>"rfpp"},
|
241 |
|
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{code=>0172400, mask=>0000377, name=>"!!ldf", type=>"rfpp"},
|
242 |
|
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{code=>0173000, mask=>0000377, name=>"!!subf", type=>"rfpp"},
|
243 |
|
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{code=>0173400, mask=>0000377, name=>"!!cmpf", type=>"rfpp"},
|
244 |
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{code=>0174000, mask=>0000377, name=>"!!stf", type=>"rfpp"},
|
245 |
|
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{code=>0174400, mask=>0000377, name=>"!!divf", type=>"rfpp"},
|
246 |
|
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{code=>0175000, mask=>0000377, name=>"!!stexp",type=>"rfpp"},
|
247 |
|
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{code=>0175400, mask=>0000377, name=>"!!stcif",type=>"rfpp"},
|
248 |
|
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{code=>0176000, mask=>0000377, name=>"!!stcfd",type=>"rfpp"},
|
249 |
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{code=>0176400, mask=>0000377, name=>"!!ldexp",type=>"rfpp"},
|
250 |
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{code=>0177000, mask=>0000377, name=>"!!ldcif",type=>"rfpp"},
|
251 |
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{code=>0177400, mask=>0000377, name=>"!!ldcdf",type=>"rfpp"}
|
252 |
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);
|
253 |
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254 |
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my %pdp11_regs = ( # use simh naming convention
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255 |
|
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177776=> "psw",
|
256 |
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177774=> "stklim",
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257 |
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177772=> "pirq",
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258 |
|
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177770=> "mbrk",
|
259 |
|
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177766=> "cpuerr",
|
260 |
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177764=> "sysid",
|
261 |
|
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177600=> "uipdr0",
|
262 |
|
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177602=> "uipdr1",
|
263 |
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177604=> "uipdr2",
|
264 |
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177606=> "uipdr3",
|
265 |
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177610=> "uipdr4",
|
266 |
|
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177612=> "uipdr5",
|
267 |
|
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177614=> "uipdr6",
|
268 |
|
|
177616=> "uipdr7",
|
269 |
|
|
177620=> "udpdr0",
|
270 |
|
|
177622=> "udpdr1",
|
271 |
|
|
177624=> "udpdr2",
|
272 |
|
|
177626=> "udpdr3",
|
273 |
|
|
177630=> "udpdr4",
|
274 |
|
|
177632=> "udpdr5",
|
275 |
|
|
177634=> "udpdr6",
|
276 |
|
|
177636=> "udpdr7",
|
277 |
|
|
177640=> "uipar0",
|
278 |
|
|
177642=> "uipar1",
|
279 |
|
|
177644=> "uipar2",
|
280 |
|
|
177646=> "uipar3",
|
281 |
|
|
177650=> "uipar4",
|
282 |
|
|
177652=> "uipar5",
|
283 |
|
|
177654=> "uipar6",
|
284 |
|
|
177656=> "uipar7",
|
285 |
|
|
177660=> "udpar0",
|
286 |
|
|
177662=> "udpar1",
|
287 |
|
|
177664=> "udpar2",
|
288 |
|
|
177666=> "udpar3",
|
289 |
|
|
177670=> "udpar4",
|
290 |
|
|
177672=> "udpar5",
|
291 |
|
|
177674=> "udpar6",
|
292 |
|
|
177676=> "udpar7",
|
293 |
|
|
177576=> "mmr2",
|
294 |
|
|
177574=> "mmr1",
|
295 |
|
|
177572=> "mmr0",
|
296 |
|
|
177570=> "sdreg", # not a simh name !!
|
297 |
|
|
177560=> "ti.csr",
|
298 |
|
|
177562=> "ti.buf",
|
299 |
|
|
177564=> "to.csr",
|
300 |
|
|
177566=> "to.buf",
|
301 |
|
|
177550=> "pr.csr",
|
302 |
|
|
177552=> "pr.buf",
|
303 |
|
|
177554=> "pp.csr",
|
304 |
|
|
177556=> "pp.buf",
|
305 |
|
|
177546=> "kl.csr",
|
306 |
|
|
177514=> "lp.csr",
|
307 |
|
|
177516=> "lp.buf",
|
308 |
|
|
177500=> "ii.acr",
|
309 |
|
|
177502=> "ii.adr",
|
310 |
|
|
177400=> "rk.ds ",
|
311 |
|
|
177402=> "rk.er ",
|
312 |
|
|
177404=> "rk.cs ",
|
313 |
|
|
177406=> "rk.wc ",
|
314 |
|
|
177410=> "rk.ba ",
|
315 |
|
|
177412=> "rk.da ",
|
316 |
|
|
177414=> "rk.mr ",
|
317 |
|
|
177416=> "rk.db ",
|
318 |
|
|
177060=> "xor.cs", # XOR Tester
|
319 |
30 |
wfjm |
176700=> "rpa.cs1",
|
320 |
|
|
176702=> "rpa.wc ",
|
321 |
|
|
176704=> "rpa.ba ",
|
322 |
|
|
176706=> "rpa.da ",
|
323 |
|
|
176710=> "rpa.cs2",
|
324 |
|
|
176712=> "rpa.ds ",
|
325 |
|
|
176714=> "rpa.er1",
|
326 |
|
|
176716=> "rpa.as ",
|
327 |
|
|
176720=> "rpa.la ",
|
328 |
|
|
176722=> "rpa.db ",
|
329 |
|
|
176724=> "rpa.mr1",
|
330 |
|
|
176726=> "rpa.dt ",
|
331 |
|
|
176730=> "rpa.sn ",
|
332 |
|
|
176732=> "rpa.of ",
|
333 |
|
|
176734=> "rpa.dc ",
|
334 |
|
|
176736=> "rpa.m13",
|
335 |
|
|
176740=> "rpa.m14",
|
336 |
|
|
176742=> "rpa.m15",
|
337 |
|
|
176744=> "rpa.ec1",
|
338 |
|
|
176746=> "rpa.ec2",
|
339 |
|
|
176750=> "rpa.bae",
|
340 |
|
|
176752=> "rpa.cs3",
|
341 |
2 |
wfjm |
176500=> "ti2.cs",
|
342 |
|
|
176502=> "ti2.bu",
|
343 |
|
|
176504=> "to2.cs",
|
344 |
|
|
176506=> "to2.bu",
|
345 |
|
|
174400=> "rl.cs ",
|
346 |
|
|
174402=> "rl.ba ",
|
347 |
|
|
174404=> "rl.da ",
|
348 |
|
|
174406=> "rl.mp ",
|
349 |
|
|
172540=> "kp.csr",
|
350 |
|
|
172542=> "kp.buf",
|
351 |
|
|
172544=> "kp.cnt",
|
352 |
|
|
172520=> "tm.mts",
|
353 |
|
|
172522=> "tm.mtc",
|
354 |
|
|
172524=> "tm.brc",
|
355 |
|
|
172526=> "tm.cma",
|
356 |
|
|
172530=> "tm.mtd",
|
357 |
|
|
172532=> "tm.rda",
|
358 |
|
|
172516=> "mmr3",
|
359 |
|
|
172200=> "sipdr0",
|
360 |
|
|
172202=> "sipdr1",
|
361 |
|
|
172204=> "sipdr2",
|
362 |
|
|
172206=> "sipdr3",
|
363 |
|
|
172210=> "sipdr4",
|
364 |
|
|
172212=> "sipdr5",
|
365 |
|
|
172214=> "sipdr6",
|
366 |
|
|
172216=> "sipdr7",
|
367 |
|
|
172220=> "sdpdr0",
|
368 |
|
|
172222=> "sdpdr1",
|
369 |
|
|
172224=> "sdpdr2",
|
370 |
|
|
172226=> "sdpdr3",
|
371 |
|
|
172230=> "sdpdr4",
|
372 |
|
|
172232=> "sdpdr5",
|
373 |
|
|
172234=> "sdpdr6",
|
374 |
|
|
172236=> "sdpdr7",
|
375 |
|
|
172240=> "sipar0",
|
376 |
|
|
172242=> "sipar1",
|
377 |
|
|
172244=> "sipar2",
|
378 |
|
|
172246=> "sipar3",
|
379 |
|
|
172250=> "sipar4",
|
380 |
|
|
172252=> "sipar5",
|
381 |
|
|
172254=> "sipar6",
|
382 |
|
|
172256=> "sipar7",
|
383 |
|
|
172260=> "sdpar0",
|
384 |
|
|
172262=> "sdpar1",
|
385 |
|
|
172264=> "sdpar2",
|
386 |
|
|
172266=> "sdpar3",
|
387 |
|
|
172270=> "sdpar4",
|
388 |
|
|
172272=> "sdpar5",
|
389 |
|
|
172274=> "sdpar6",
|
390 |
|
|
172276=> "sdpar7",
|
391 |
|
|
172300=> "kipdr0",
|
392 |
|
|
172302=> "kipdr1",
|
393 |
|
|
172304=> "kipdr2",
|
394 |
|
|
172306=> "kipdr3",
|
395 |
|
|
172310=> "kipdr4",
|
396 |
|
|
172312=> "kipdr5",
|
397 |
|
|
172314=> "kipdr6",
|
398 |
|
|
172316=> "kipdr7",
|
399 |
|
|
172320=> "kdpdr0",
|
400 |
|
|
172322=> "kdpdr1",
|
401 |
|
|
172324=> "kdpdr2",
|
402 |
|
|
172326=> "kdpdr3",
|
403 |
|
|
172330=> "kdpdr4",
|
404 |
|
|
172332=> "kdpdr5",
|
405 |
|
|
172334=> "kdpdr6",
|
406 |
|
|
172336=> "kdpdr7",
|
407 |
|
|
172340=> "kipar0",
|
408 |
|
|
172342=> "kipar1",
|
409 |
|
|
172344=> "kipar2",
|
410 |
|
|
172346=> "kipar3",
|
411 |
|
|
172350=> "kipar4",
|
412 |
|
|
172352=> "kipar5",
|
413 |
|
|
172354=> "kipar6",
|
414 |
|
|
172356=> "kipar7",
|
415 |
|
|
172360=> "kdpar0",
|
416 |
|
|
172362=> "kdpar1",
|
417 |
|
|
172364=> "kdpar2",
|
418 |
|
|
172366=> "kdpar3",
|
419 |
|
|
172370=> "kdpar4",
|
420 |
|
|
172372=> "kdpar5",
|
421 |
|
|
172374=> "kdpar6",
|
422 |
|
|
172376=> "kdpar7",
|
423 |
|
|
160100=> "dz.csr",
|
424 |
|
|
160102=> "dz.mp2",
|
425 |
|
|
160104=> "dz.tcr",
|
426 |
|
|
160106=> "dz.mp6"
|
427 |
|
|
);
|
428 |
|
|
|
429 |
|
|
autoflush STDOUT 1 if (-p STDOUT); # autoflush if output into pipe
|
430 |
|
|
|
431 |
|
|
if (exists $opts{help}) {
|
432 |
|
|
print_help;
|
433 |
|
|
exit 0;
|
434 |
|
|
}
|
435 |
|
|
|
436 |
|
|
foreach my $file (@ARGV) {
|
437 |
|
|
do_file($file);
|
438 |
|
|
}
|
439 |
|
|
|
440 |
|
|
|
441 |
|
|
#-------------------------------------------------------------------------------
|
442 |
|
|
|
443 |
|
|
sub do_file {
|
444 |
|
|
my ($file) = @_;
|
445 |
|
|
|
446 |
|
|
open IFILE,"<$file" or die "failed to open $file";
|
447 |
|
|
|
448 |
|
|
my $idec_cyc = 0;
|
449 |
|
|
my $change_cyc = 0;
|
450 |
|
|
my $emreq_cyc = 0;
|
451 |
|
|
my $emreq_str = "";
|
452 |
|
|
my $ibreq_cyc = 0;
|
453 |
|
|
my $ibreq_typ = "";
|
454 |
|
|
my $ibreq_str = "";
|
455 |
|
|
my $ibreq_nam = "";
|
456 |
|
|
|
457 |
|
|
my $emcurr_we = 0; # curr em write enable (or undef)
|
458 |
|
|
my $emcurr_addr = undef; # curr em address
|
459 |
|
|
my $emlast_we = 0; # prev em write enable (or undef)
|
460 |
|
|
my $emlast_addr = undef; # prev em address
|
461 |
|
|
|
462 |
|
|
while () {
|
463 |
|
|
chomp;
|
464 |
|
|
if (/^#\s+/) {
|
465 |
|
|
@var_name = ();
|
466 |
|
|
@var_type = ();
|
467 |
|
|
my $dsc_str = $';
|
468 |
|
|
my @dsc_list = split /\s+/,$dsc_str;
|
469 |
|
|
foreach my $dsc (@dsc_list) {
|
470 |
|
|
if ($dsc =~ /^(.*):([bdo])$/) {
|
471 |
|
|
my $ind = scalar(@var_name);
|
472 |
|
|
$name{$1} = {ind=>$ind,
|
473 |
|
|
typ=>$2};
|
474 |
|
|
push @var_name, $1;
|
475 |
|
|
push @var_type, $2;
|
476 |
|
|
push @var_dec, $ind if $2 eq "d";
|
477 |
|
|
push @var_oct, $ind if $2 eq "o";
|
478 |
|
|
} else {
|
479 |
|
|
print "tmuconv-E: bad descriptor $dsc\n";
|
480 |
|
|
}
|
481 |
|
|
}
|
482 |
|
|
|
483 |
|
|
$ind_dp_pc = $name{'dp.pc'}->{ind};
|
484 |
|
|
$ind_dp_psw = $name{'dp.psw'}->{ind};
|
485 |
|
|
$ind_dp_ireg = $name{'dp.ireg'}->{ind};
|
486 |
|
|
$ind_dp_ireg_we = $name{'dp.ireg_we'}->{ind};
|
487 |
|
|
$ind_dp_ireg_we_last = $name{'dp.ireg_we_last'}->{ind};
|
488 |
|
|
$ind_dp_dres = $name{'dp.dres'}->{ind};
|
489 |
|
|
$ind_dp_gpr_adst = $name{'dp.gpr_adst'}->{ind};
|
490 |
|
|
$ind_dp_gpr_mode = $name{'dp.gpr_mode'}->{ind};
|
491 |
|
|
$ind_dp_gpr_bytop = $name{'dp.gpr_bytop'}->{ind};
|
492 |
|
|
$ind_dp_gpr_we = $name{'dp.gpr_we'}->{ind};
|
493 |
|
|
|
494 |
8 |
wfjm |
$ind_vm_ibmreq_aval = $name{'vm.ibmreq.aval'}->{ind};
|
495 |
|
|
$ind_vm_ibmreq_re = $name{'vm.ibmreq.re'}->{ind};
|
496 |
2 |
wfjm |
$ind_vm_ibmreq_we = $name{'vm.ibmreq.we'}->{ind};
|
497 |
8 |
wfjm |
$ind_vm_ibmreq_rmw = $name{'vm.ibmreq.rmw'}->{ind};
|
498 |
2 |
wfjm |
$ind_vm_ibmreq_be0 = $name{'vm.ibmreq.be0'}->{ind};
|
499 |
|
|
$ind_vm_ibmreq_be1 = $name{'vm.ibmreq.be1'}->{ind};
|
500 |
|
|
$ind_vm_ibmreq_cacc = $name{'vm.ibmreq.cacc'}->{ind};
|
501 |
|
|
$ind_vm_ibmreq_racc = $name{'vm.ibmreq.racc'}->{ind};
|
502 |
|
|
$ind_vm_ibmreq_addr = $name{'vm.ibmreq.addr'}->{ind};
|
503 |
|
|
$ind_vm_ibmreq_din = $name{'vm.ibmreq.din'}->{ind};
|
504 |
|
|
$ind_vm_ibsres_ack = $name{'vm.ibsres.ack'}->{ind};
|
505 |
|
|
$ind_vm_ibsres_busy = $name{'vm.ibsres.busy'}->{ind};
|
506 |
|
|
$ind_vm_ibsres_dout = $name{'vm.ibsres.dout'}->{ind};
|
507 |
|
|
|
508 |
|
|
$ind_sy_emmreq_req = $name{'sy.emmreq.req'}->{ind};
|
509 |
|
|
$ind_sy_emmreq_we = $name{'sy.emmreq.we'}->{ind};
|
510 |
|
|
$ind_sy_emmreq_be = $name{'sy.emmreq.be'}->{ind};
|
511 |
|
|
$ind_sy_emmreq_cancel = $name{'sy.emmreq.cancel'}->{ind};
|
512 |
|
|
$ind_sy_emmreq_addr = $name{'sy.emmreq.addr'}->{ind};
|
513 |
|
|
$ind_sy_emmreq_din = $name{'sy.emmreq.din'}->{ind};
|
514 |
|
|
$ind_sy_emsres_ack_r = $name{'sy.emsres.ack_r'}->{ind};
|
515 |
|
|
$ind_sy_emsres_ack_w = $name{'sy.emsres.ack_w'}->{ind};
|
516 |
|
|
$ind_sy_emsres_dout = $name{'sy.emsres.dout'}->{ind};
|
517 |
|
|
$ind_sy_chit = $name{'sy.chit'}->{ind};
|
518 |
|
|
|
519 |
|
|
} else {
|
520 |
|
|
@val_last = @val_curr;
|
521 |
|
|
my $notfirst = scalar(@val_last) > 0;
|
522 |
|
|
|
523 |
|
|
$_ =~ s/^\s*//;
|
524 |
|
|
$_ =~ s/\s*$//;
|
525 |
|
|
@val_curr = split /\s+/,$_;
|
526 |
|
|
if (scalar(@val_curr) != scalar(@var_name)) {
|
527 |
|
|
printf "tmuconv-E: value list length mismatch, seen %d, expected %d\n",
|
528 |
|
|
scalar(@val_curr), scalar(@var_name);
|
529 |
|
|
for (my $i=0; $i
|
530 |
|
|
printf "%3d: %s\n", $i,$val_curr[$i];
|
531 |
|
|
}
|
532 |
|
|
next;
|
533 |
|
|
}
|
534 |
|
|
|
535 |
|
|
@val_curr_text = @val_curr if exists $opts{dump} || exists $opts{cdump};
|
536 |
|
|
|
537 |
|
|
my $cyc_curr = int $val_curr[0];
|
538 |
|
|
my $cyc_str = sprintf "%8d", $cyc_curr;
|
539 |
|
|
|
540 |
|
|
foreach my $ind (@var_dec) {
|
541 |
|
|
$val_curr[$ind] = int ($val_curr[$ind]);
|
542 |
|
|
}
|
543 |
|
|
foreach my $ind (@var_oct) {
|
544 |
|
|
$val_curr[$ind] = oct ($val_curr[$ind]);
|
545 |
|
|
}
|
546 |
|
|
|
547 |
|
|
my $id_str = "";
|
548 |
|
|
my $ru_str = "";
|
549 |
|
|
my $emres_str = "";
|
550 |
|
|
my $emtyp_str = "";
|
551 |
|
|
my $ibres_str = "";
|
552 |
|
|
my $ibreq_we = 0;
|
553 |
|
|
my $ibreq_act = 0;
|
554 |
|
|
|
555 |
|
|
if (exists $opts{dump} || exists $opts{cdump}) {
|
556 |
|
|
my @val_change;
|
557 |
|
|
my $any_change;
|
558 |
|
|
|
559 |
|
|
for (my $i=1; $i
|
560 |
|
|
my $change = (not $notfirst) || ($val_curr[$i] != $val_last[$i]);
|
561 |
|
|
$val_change[$i] = $change;
|
562 |
|
|
$any_change |= $change;
|
563 |
|
|
}
|
564 |
|
|
|
565 |
|
|
if (exists $opts{dump} || $any_change) {
|
566 |
|
|
printf "cycle $cyc_str %s", "-" x 32;
|
567 |
|
|
if ($notfirst && exists $opts{cdump}) {
|
568 |
|
|
printf " (%d)",$cyc_curr-$change_cyc;
|
569 |
|
|
}
|
570 |
|
|
print "\n";
|
571 |
|
|
|
572 |
|
|
for (my $i=1; $i
|
573 |
|
|
my $oper = $val_change[$i] ? "<=" : " =";
|
574 |
|
|
if (exists $opts{dump} || $val_change[$i]) {
|
575 |
|
|
printf " %-16s:%s %s %s\n", $var_name[$i], $var_type[$i],
|
576 |
|
|
$oper, $val_curr_text[$i];
|
577 |
|
|
}
|
578 |
|
|
}
|
579 |
|
|
$change_cyc = $cyc_curr;
|
580 |
|
|
}
|
581 |
|
|
}
|
582 |
|
|
#
|
583 |
|
|
# handle t_id
|
584 |
|
|
# uses cycles with dp_ireg_we = '1'
|
585 |
|
|
#
|
586 |
|
|
if (exists $opts{t_id} and $notfirst) {
|
587 |
|
|
if ($val_curr[$ind_dp_ireg_we_last]) {
|
588 |
|
|
my $pc = $val_curr[$ind_dp_pc] - 2;
|
589 |
|
|
my $psw = $val_curr[$ind_dp_psw];
|
590 |
|
|
my $ireg = $val_curr[$ind_dp_ireg];
|
591 |
|
|
my $code = code2mnemo($ireg);
|
592 |
|
|
$id_str = sprintf " %6.6o %6.6o %6.6o %s",
|
593 |
|
|
$pc, $psw, $ireg, $code;
|
594 |
|
|
$id_str .= " " x (20-length($code));
|
595 |
|
|
$id_str .= sprintf " (%d)",$cyc_curr-$idec_cyc;
|
596 |
|
|
$idec_cyc = $cyc_curr;
|
597 |
|
|
}
|
598 |
|
|
}
|
599 |
|
|
#
|
600 |
|
|
|
601 |
|
|
# 1706 ru 0 06 000002 000002 000002 000002 000002 000002 000002 ksp
|
602 |
|
|
# 1694 id 002012 000340 010036 mov r0,@(sp)+ (8)
|
603 |
|
|
|
604 |
|
|
|
605 |
|
|
# handle t_ru
|
606 |
|
|
# uses cycles with dp_gpr_we = '1'
|
607 |
|
|
#
|
608 |
|
|
if (exists $opts{t_ru}) {
|
609 |
|
|
if ($val_curr[$ind_dp_gpr_we]) {
|
610 |
|
|
my $adst = $val_curr[$ind_dp_gpr_adst];
|
611 |
|
|
my $mode = $val_curr[$ind_dp_gpr_mode];
|
612 |
|
|
my $bytop = $val_curr[$ind_dp_gpr_bytop];
|
613 |
|
|
my $psw = $val_curr[$ind_dp_psw];
|
614 |
|
|
my $dres = $val_curr[$ind_dp_dres];
|
615 |
|
|
my $rset = $psw>>11 & 01;
|
616 |
|
|
$ru_str = sprintf "%o %o%o %6.6o", $bytop, $rset, $adst, $dres;
|
617 |
|
|
$ru_str .= " ";
|
618 |
|
|
if ($adst eq "7") {
|
619 |
|
|
$ru_str .= "pc";
|
620 |
|
|
} elsif ($adst eq "6") {
|
621 |
|
|
$reg_sp[$mode] = sprintf "%6.6o",$dres;
|
622 |
|
|
$ru_str .= $reg_sp[0];
|
623 |
|
|
$ru_str .= ($mode == 0) ? "*" : " ";
|
624 |
|
|
$ru_str .= $reg_sp[1];
|
625 |
|
|
$ru_str .= ($mode == 1) ? "*" : " ";
|
626 |
|
|
$ru_str .= $reg_sp[3];
|
627 |
|
|
$ru_str .= ($mode == 3) ? "*" : " ";
|
628 |
|
|
$ru_str .= " ksp" if $mode eq "0";
|
629 |
|
|
$ru_str .= " ssp" if $mode eq "1";
|
630 |
|
|
$ru_str .= " usp" if $mode eq "3";
|
631 |
|
|
} else {
|
632 |
|
|
my $rbase = ($rset==0) ? 0 : 6;
|
633 |
|
|
$reg_05[$rbase+$adst] = sprintf "%6.6o",$dres;
|
634 |
|
|
for (my $i=0; $i<6; $i++) {
|
635 |
|
|
$ru_str .= $reg_05[$rbase+$i];
|
636 |
|
|
$ru_str .= ($adst==$i) ? "*" : " ";
|
637 |
|
|
}
|
638 |
|
|
$ru_str .= sprintf " r%o%o", $rset, $adst;
|
639 |
|
|
}
|
640 |
|
|
}
|
641 |
|
|
}
|
642 |
|
|
#
|
643 |
|
|
# handle t_em
|
644 |
|
|
# uses cycles with sy_emmreq_req = '1'
|
645 |
|
|
# sy_emsres_ack_r = '1'
|
646 |
|
|
# sy_emsres_ack_w = '1'
|
647 |
|
|
# sy_emsreq_cancel = '1'
|
648 |
|
|
#
|
649 |
|
|
if (exists $opts{t_em}) {
|
650 |
|
|
if ($val_curr[$ind_sy_emmreq_req]) {
|
651 |
|
|
$emreq_cyc = $cyc_curr;
|
652 |
|
|
$emreq_str = sprintf "%s %s %8.8o",
|
653 |
|
|
($val_curr[$ind_sy_emmreq_we] ? "w" : "r"),
|
654 |
|
|
$val_curr[$ind_sy_emmreq_be],
|
655 |
|
|
$val_curr[$ind_sy_emmreq_addr];
|
656 |
|
|
$emcurr_we = $val_curr[$ind_sy_emmreq_we];
|
657 |
|
|
$emcurr_addr = $val_curr[$ind_sy_emmreq_addr];
|
658 |
|
|
if ($emcurr_we) {
|
659 |
|
|
$emreq_str .= sprintf " %6.6o", $val_curr[$ind_sy_emmreq_din];
|
660 |
|
|
} else {
|
661 |
|
|
$emreq_str .= " " x 7;
|
662 |
|
|
}
|
663 |
|
|
}
|
664 |
|
|
if ($val_curr[$ind_sy_emsres_ack_r] ||
|
665 |
|
|
$val_curr[$ind_sy_emsres_ack_w] ||
|
666 |
|
|
$val_curr[$ind_sy_emmreq_cancel]) {
|
667 |
|
|
$emres_str = sprintf "%s%s%s%s",
|
668 |
|
|
$val_curr[$ind_sy_emmreq_cancel],
|
669 |
|
|
$val_curr[$ind_sy_emsres_ack_r],
|
670 |
|
|
$val_curr[$ind_sy_emsres_ack_w],
|
671 |
|
|
$val_curr[$ind_sy_chit];
|
672 |
|
|
if ($val_curr[$ind_sy_emmreq_cancel]) {
|
673 |
|
|
$emreq_str .= " cancel";
|
674 |
|
|
$emcurr_we = undef;
|
675 |
|
|
} else {
|
676 |
|
|
if ($val_curr[$ind_sy_emsres_ack_r]) {
|
677 |
|
|
$emreq_str .= sprintf " %6.6o", $val_curr[$ind_sy_emsres_dout];
|
678 |
|
|
} else {
|
679 |
|
|
$emreq_str .= " " x 7;
|
680 |
|
|
}
|
681 |
|
|
if (defined $emlast_we && $emcurr_we == $emlast_we) {
|
682 |
|
|
if ($emcurr_we && $emcurr_addr == $emlast_addr-2) {
|
683 |
|
|
$emtyp_str = "SPUSH";
|
684 |
|
|
} elsif ((not $emcurr_we) && $emcurr_addr == $emlast_addr+2 &&
|
685 |
|
|
$emcurr_addr < 0400 && ($emcurr_addr % 04) == 02) {
|
686 |
|
|
$emtyp_str = "VFETCH";
|
687 |
|
|
$emtyp_str .= " 004 ill.inst" if ($emlast_addr == 0004);
|
688 |
|
|
$emtyp_str .= " 010 res.inst" if ($emlast_addr == 0010);
|
689 |
|
|
$emtyp_str .= " 014 BPT" if ($emlast_addr == 0014);
|
690 |
|
|
$emtyp_str .= " 020 IOT" if ($emlast_addr == 0020);
|
691 |
|
|
$emtyp_str .= " 030 EMT" if ($emlast_addr == 0030);
|
692 |
|
|
$emtyp_str .= " 034 TRAP" if ($emlast_addr == 0034);
|
693 |
|
|
$emtyp_str .= " 060 DL11-TTI" if ($emlast_addr == 0060);
|
694 |
|
|
$emtyp_str .= " 064 DL11-TTO" if ($emlast_addr == 0064);
|
695 |
|
|
$emtyp_str .= " 070 PC11-PTR" if ($emlast_addr == 0070);
|
696 |
|
|
$emtyp_str .= " 074 PC11-PTP" if ($emlast_addr == 0074);
|
697 |
|
|
$emtyp_str .= " 100 KW11-L" if ($emlast_addr == 0100);
|
698 |
|
|
$emtyp_str .= " 104 KW11-P" if ($emlast_addr == 0104);
|
699 |
|
|
$emtyp_str .= " 160 RL11" if ($emlast_addr == 0160);
|
700 |
|
|
$emtyp_str .= " 200 LP11" if ($emlast_addr == 0200);
|
701 |
|
|
$emtyp_str .= " 220 RK11" if ($emlast_addr == 0220);
|
702 |
|
|
$emtyp_str .= " 224 TM11" if ($emlast_addr == 0224);
|
703 |
|
|
$emtyp_str .= " 240 PIRQ" if ($emlast_addr == 0240);
|
704 |
|
|
$emtyp_str .= " 244 FPP exp" if ($emlast_addr == 0244);
|
705 |
|
|
$emtyp_str .= " 250 MMU trap" if ($emlast_addr == 0250);
|
706 |
|
|
$emtyp_str .= " 260 IIST" if ($emlast_addr == 0260);
|
707 |
|
|
$emtyp_str .= " 300 DL11-2-TTI" if ($emlast_addr == 0300);
|
708 |
|
|
$emtyp_str .= " 304 DL11-2-TTO" if ($emlast_addr == 0304);
|
709 |
|
|
}
|
710 |
|
|
}
|
711 |
|
|
}
|
712 |
|
|
$emlast_we = $emcurr_we;
|
713 |
|
|
$emlast_addr = $emcurr_addr;
|
714 |
|
|
}
|
715 |
|
|
}
|
716 |
|
|
#
|
717 |
|
|
# handle t_ib
|
718 |
8 |
wfjm |
# uses cycles with sy_ibmreq_re = '1' or sy_ibmreq_we = '1'
|
719 |
2 |
wfjm |
# sy_ibsres_ack = '1'
|
720 |
|
|
# vm_ibsres_busy '1' -> '0' transition
|
721 |
|
|
#
|
722 |
|
|
if (exists $opts{t_ib}) {
|
723 |
8 |
wfjm |
if ($val_curr[$ind_vm_ibmreq_re] || $val_curr[$ind_vm_ibmreq_we]) {
|
724 |
2 |
wfjm |
my $addr_str = sprintf "%6.6o", $val_curr[$ind_vm_ibmreq_addr];
|
725 |
|
|
$ibreq_cyc = $cyc_curr;
|
726 |
|
|
$ibreq_typ = sprintf "%s%s",
|
727 |
|
|
($val_curr[$ind_vm_ibmreq_cacc] ? "c" : "-"),
|
728 |
|
|
($val_curr[$ind_vm_ibmreq_racc] ? "r" : "-");
|
729 |
8 |
wfjm |
$ibreq_str = sprintf "%s%s%s%s %s",
|
730 |
|
|
($val_curr[$ind_vm_ibmreq_we] ? "w" : "r"),
|
731 |
|
|
($val_curr[$ind_vm_ibmreq_rmw] ? "m" : " "),
|
732 |
2 |
wfjm |
$val_curr[$ind_vm_ibmreq_be1],
|
733 |
|
|
$val_curr[$ind_vm_ibmreq_be0],
|
734 |
|
|
$addr_str;
|
735 |
|
|
$ibreq_we = $val_curr[$ind_vm_ibmreq_we];
|
736 |
|
|
$ibreq_act = 1;
|
737 |
|
|
if ($ibreq_we) {
|
738 |
|
|
$ibreq_str .= sprintf " %6.6o", $val_curr[$ind_vm_ibmreq_din];
|
739 |
|
|
} else {
|
740 |
|
|
$ibreq_str .= " " x 7;
|
741 |
|
|
}
|
742 |
|
|
$ibreq_nam = $pdp11_regs{$addr_str};
|
743 |
|
|
$ibreq_nam = "" if not defined $ibreq_nam;
|
744 |
|
|
}
|
745 |
|
|
|
746 |
|
|
if ($val_curr[$ind_vm_ibsres_ack]) {
|
747 |
|
|
$ibreq_act = 0;
|
748 |
|
|
$ibres_str .= sprintf " %s", $val_curr[$ind_vm_ibsres_ack];
|
749 |
|
|
if (not $ibreq_we) {
|
750 |
|
|
$ibreq_str .= sprintf " %6.6o", $val_curr[$ind_vm_ibsres_dout];
|
751 |
|
|
} else {
|
752 |
|
|
$ibreq_str .= " " x 7;
|
753 |
|
|
}
|
754 |
|
|
}
|
755 |
|
|
|
756 |
|
|
if ($ibreq_act && $val_curr[$ind_vm_ibsres_busy]==0) {
|
757 |
|
|
$ibres_str .= "no ACK, no BUSY";
|
758 |
|
|
$ibreq_act = 0;
|
759 |
|
|
}
|
760 |
|
|
}
|
761 |
|
|
|
762 |
|
|
print "$cyc_str id $id_str\n" if $id_str;
|
763 |
|
|
print "$cyc_str ru $ru_str\n" if $ru_str;
|
764 |
|
|
if ($emres_str) {
|
765 |
|
|
printf "$cyc_str em $emreq_str $emres_str (%d) $emtyp_str\n",
|
766 |
|
|
$cyc_curr-$emreq_cyc;
|
767 |
|
|
}
|
768 |
|
|
if ($ibres_str) {
|
769 |
|
|
printf "$cyc_str ib %s $ibreq_str $ibres_str (%d) $ibreq_nam\n",
|
770 |
|
|
$ibreq_typ, $cyc_curr-$ibreq_cyc;
|
771 |
|
|
}
|
772 |
|
|
}
|
773 |
|
|
}
|
774 |
|
|
|
775 |
|
|
close IFILE;
|
776 |
|
|
}
|
777 |
|
|
|
778 |
|
|
#-------------------------------------------------------------------------------
|
779 |
|
|
|
780 |
|
|
sub code2mnemo {
|
781 |
|
|
my ($code) = @_;
|
782 |
|
|
|
783 |
|
|
foreach my $ele (@pdp11_opcode_tbl) {
|
784 |
|
|
if (($code & (~($ele->{mask})) ) == $ele->{code}) {
|
785 |
|
|
my $name = $ele->{name};
|
786 |
|
|
my $type = $ele->{type};
|
787 |
|
|
my $str = $name;
|
788 |
|
|
if ($type eq "0arg") {
|
789 |
|
|
return $name;
|
790 |
|
|
|
791 |
|
|
} elsif ($type eq "1arg" or $type eq "1fpp") {
|
792 |
|
|
my $dst = $code & 077;
|
793 |
|
|
my $dst_str = regmod($dst);
|
794 |
|
|
return "$name $dst_str";
|
795 |
|
|
|
796 |
|
|
} elsif ($type eq "2arg") {
|
797 |
|
|
my $src = ($code>>6) & 077;
|
798 |
|
|
my $dst = $code & 077;
|
799 |
|
|
my $src_str = regmod($src);
|
800 |
|
|
my $dst_str = regmod($dst);
|
801 |
|
|
return "$name $src_str,$dst_str";
|
802 |
|
|
|
803 |
|
|
} elsif ($type eq "rdst") {
|
804 |
|
|
my $reg = ($code>>6) & 07;
|
805 |
|
|
my $src = $code & 077;
|
806 |
|
|
my $src_str = regmod($src);
|
807 |
|
|
return "$name $src_str,r$reg";
|
808 |
|
|
|
809 |
|
|
} elsif ($type eq "1reg") {
|
810 |
|
|
my $reg = $code & 07;
|
811 |
|
|
my $reg_str = "r$reg";
|
812 |
|
|
$reg_str = "sp" if $reg == 6;
|
813 |
|
|
$reg_str = "pc" if $reg == 7;
|
814 |
|
|
return "$name $reg_str";
|
815 |
|
|
|
816 |
|
|
} elsif ($type eq "br") {
|
817 |
|
|
my $off = $code & 0177;
|
818 |
|
|
my $sign = "+";
|
819 |
|
|
if ($code & 0200) {
|
820 |
|
|
$off = -(((~$off) & 0177)+1);
|
821 |
|
|
$sign = "-";
|
822 |
|
|
}
|
823 |
|
|
return sprintf "$name .%s%d.", $sign, abs(2*$off);
|
824 |
30 |
wfjm |
|
825 |
2 |
wfjm |
} elsif ($type eq "sob") {
|
826 |
|
|
my $reg = ($code>>6) & 07;
|
827 |
|
|
my $off = $code & 077;
|
828 |
|
|
return sprintf "$name r%d,.-%d.", $reg, 2*$off;
|
829 |
30 |
wfjm |
|
830 |
2 |
wfjm |
} elsif ($type eq "trap") {
|
831 |
|
|
my $off = $code & 0377;
|
832 |
|
|
return sprintf "$name %3.3o", $off;
|
833 |
30 |
wfjm |
|
834 |
2 |
wfjm |
} elsif ($type eq "spl") {
|
835 |
|
|
my $off = $code & 07;
|
836 |
|
|
return sprintf "$name %d", $off;
|
837 |
30 |
wfjm |
|
838 |
2 |
wfjm |
} elsif ($type eq "ccop") {
|
839 |
|
|
my $cc = $code & 017;
|
840 |
|
|
return "nop" if ($cc == 0);
|
841 |
|
|
return "ccc" if ($code == 0257);
|
842 |
|
|
return "scc" if ($code == 0277);
|
843 |
|
|
my $str = "";
|
844 |
|
|
my $del = "";
|
845 |
|
|
if ($code & 010) { $str .= $del . $name . "n", $del = "+" }
|
846 |
|
|
if ($code & 004) { $str .= $del . $name . "z", $del = "+" }
|
847 |
|
|
if ($code & 002) { $str .= $del . $name . "v", $del = "+" }
|
848 |
|
|
if ($code & 001) { $str .= $del . $name . "c", $del = "+" }
|
849 |
|
|
return $str;
|
850 |
30 |
wfjm |
|
851 |
2 |
wfjm |
} elsif ($type eq "jsr") {
|
852 |
|
|
my $reg = ($code>>6) & 07;
|
853 |
|
|
my $dst = $code & 077;
|
854 |
|
|
my $dst_str = regmod($dst);
|
855 |
|
|
return "$name r$reg,$dst_str";
|
856 |
30 |
wfjm |
|
857 |
2 |
wfjm |
} elsif ($type eq "mark") {
|
858 |
|
|
my $off = $code & 077;
|
859 |
|
|
return sprintf "$name %3.3o", $off;
|
860 |
30 |
wfjm |
|
861 |
2 |
wfjm |
} elsif ($type eq "rfpp") {
|
862 |
|
|
my $reg = ($code>>6) & 03;
|
863 |
|
|
my $dst = $code & 077;
|
864 |
|
|
my $dst_str = regmod($dst,"f");
|
865 |
|
|
return "$name f$reg,$dst_str";
|
866 |
|
|
|
867 |
|
|
} else {
|
868 |
|
|
return "?type?";
|
869 |
|
|
}
|
870 |
|
|
}
|
871 |
|
|
}
|
872 |
|
|
return "=inval=";
|
873 |
|
|
}
|
874 |
|
|
|
875 |
|
|
#-------------------------------------------------------------------------------
|
876 |
|
|
sub regmod {
|
877 |
|
|
my ($regmod,$pref) = @_;
|
878 |
|
|
my $mod = ($regmod>>3) & 07;
|
879 |
|
|
my $reg = $regmod & 07;
|
880 |
|
|
|
881 |
|
|
$pref = "r" if not defined $pref or $reg>5;
|
882 |
|
|
|
883 |
|
|
my $reg_str = "r$reg";
|
884 |
|
|
$reg_str = "sp" if $reg == 6;
|
885 |
|
|
$reg_str = "pc" if $reg == 7;
|
886 |
|
|
|
887 |
|
|
if ($mod == 0) { # mode 0: Rx { Fx for float }
|
888 |
|
|
$reg_str = "f$reg" if defined $pref && $pref eq "f" && $reg<=5;
|
889 |
|
|
return $reg_str;
|
890 |
|
|
} elsif ($mod == 1) { # mode 1: (Rx)
|
891 |
|
|
return "($reg_str)";
|
892 |
|
|
} elsif ($mod == 2 || $mod == 3) { # mode 2/3: (Rx)+ @(Rx)+
|
893 |
|
|
my $ind = ($mod == 3) ? "@" : "";
|
894 |
|
|
if ($reg != 7) { # if reg != pc
|
895 |
|
|
return "$ind($reg_str)+";
|
896 |
|
|
} else { # if reg == pc
|
897 |
|
|
my $str = sprintf "$ind#nnn"; # 27 -> #nnn; 37 -> @#nnn
|
898 |
|
|
return $str;
|
899 |
|
|
}
|
900 |
|
|
} elsif ($mod == 4 || $mod == 5) { # mode 4/5: -(Rx) @-(Rx)
|
901 |
|
|
my $ind = ($mod == 5) ? "@" : "";
|
902 |
|
|
return "$ind-($reg_str)";
|
903 |
|
|
} elsif ($mod == 6 || $mod == 7) { # mode 6/7: nn(Rx) @nn(Rx)
|
904 |
|
|
my $ind = ($mod == 7) ? "@" : "";
|
905 |
|
|
return "${ind}nnn($reg_str)";
|
906 |
|
|
}
|
907 |
|
|
}
|
908 |
|
|
|
909 |
|
|
#-------------------------------------------------------------------------------
|
910 |
|
|
|
911 |
|
|
sub print_help {
|
912 |
|
|
print "usage: tmuconf file\n";
|
913 |
|
|
print " --help this message\n";
|
914 |
|
|
print " --dump dump all information\n";
|
915 |
|
|
print " --cdump dump only changes relative to prev cycle\n";
|
916 |
|
|
print " --t_id trace instruction decodes\n";
|
917 |
|
|
print " --t_ru trace register updates\n";
|
918 |
|
|
print " --t_em trace em transactions\n";
|
919 |
|
|
print " --t_ib trace ib transactions\n";
|
920 |
|
|
}
|