OpenCores
URL https://opencores.org/ocsvn/w11/w11/trunk

Subversion Repositories w11

[/] [w11/] [tags/] [w11a_V0.7/] [tools/] [tcl/] [rbtest/] [test_data.tcl] - Blame information for rev 36

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 30 wfjm
# $Id: test_data.tcl 661 2015-04-03 18:28:41Z mueller $
2 10 wfjm
#
3 30 wfjm
# Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4 10 wfjm
#
5
# This program is free software; you may redistribute and/or modify it under
6
# the terms of the GNU General Public License as published by the Free
7
# Software Foundation, either version 2, or at your option any later version.
8
#
9
# This program is distributed in the hope that it will be useful, but
10
# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
11
# or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
12
# for complete details.
13
#
14
#  Revision History:
15
# Date         Rev Version  Comment
16 30 wfjm
# 2015-04-03   661   2.1    drop estatdef, use estattout
17 28 wfjm
# 2014-12-21   617   2.0.1  use rbtout stat bit for timeout
18 27 wfjm
# 2014-11-09   603   2.0    use rlink v4 address layout and iface
19 10 wfjm
# 2011-03-27   374   1.0    Initial version
20
# 2011-03-13   369   0.1    First Draft
21
#
22
 
23
package provide rbtest 1.0
24
 
25
package require rutiltpp
26
package require rutil
27
package require rlink
28
 
29
namespace eval rbtest {
30
  #
31 27 wfjm
  # Basic tests with cntl, stat, data and dinc registers.
32 10 wfjm
  # All tests depend only on rbd_tester logic alone and not on how the
33
  # rbd_tester is embedded in the design (e.g. stat and attn connections)
34
  #
35
  proc test_data {} {
36
    #
37
    set errcnt 0
38
    rlc errcnt -clear
39
    #
40
    rlc log "rbtest::test_data - init: clear cntl, data, and fifo"
41
    # Note: fifo clear via init is tested later, used here 'speculatively'
42
    rlc exec -init te.cntl [regbld rbtest::INIT fifo data cntl]
43
    #
44
    #-------------------------------------------------------------------------
45 27 wfjm
    rlc log "  test 1a: cntl, stat and data are write- and read-able"
46
    foreach {addr valw valr} [list te.cntl 0xffff 0x83ff \
47 10 wfjm
                                   te.cntl 0x0000 0x0000 \
48 27 wfjm
                                   te.stat 0xffff 0x000f \
49
                                   te.stat 0x0000 0x0000 \
50 10 wfjm
                                   te.data 0xffff 0xffff \
51
                                   te.data 0x0000 0x0000 ] {
52 30 wfjm
      rlc exec -wreg $addr $valw
53
      rlc exec -rreg $addr -edata $valr
54 10 wfjm
    }
55
    #
56
    #
57 27 wfjm
    rlc log "  test 1b: as test 1a, use clists, check cntl,stat,data distinct"
58
    foreach {valc vals vald} [list 0x1 0x2 0x3 0x0 0x0 0x0] {
59 30 wfjm
      rlc exec \
60 10 wfjm
        -wreg te.cntl $valc \
61 27 wfjm
        -wreg te.stat $vals \
62 10 wfjm
        -wreg te.data $vald \
63
        -rreg te.cntl -edata $valc \
64 27 wfjm
        -rreg te.stat -edata $vals \
65 10 wfjm
        -rreg te.data -edata $vald
66
    }
67
    #
68
    #-------------------------------------------------------------------------
69 27 wfjm
    rlc log "  test 2: verify that large nbusy causes timeout"
70 30 wfjm
    rlc exec \
71 10 wfjm
      -wreg te.data 0xdead \
72
      -rreg te.data -edata 0xdead \
73
      -wreg te.cntl [regbld rbtest::CNTL {nbusy 0x3ff}] \
74 30 wfjm
      -wreg te.data 0xbeaf -estattout \
75
      -rreg te.data        -estattout \
76 10 wfjm
      -wreg te.cntl 0x0000 \
77 30 wfjm
      -rreg te.data -edata 0xdead
78 10 wfjm
    #
79
    # -------------------------------------------------------------------------
80 27 wfjm
    rlc log "  test 3a: verify that init 001 clears cntl,stat and not data"
81
    set valc [regbld rbtest::CNTL {nbusy 1}]
82 30 wfjm
    rlc exec \
83 10 wfjm
      -wreg te.cntl $valc \
84 27 wfjm
      -wreg te.stat 0x0002 \
85 10 wfjm
      -wreg te.data 0x1234 \
86
      -init te.cntl [regbld rbtest::INIT cntl] \
87
      -rreg te.cntl -edata 0x0 \
88 27 wfjm
      -rreg te.stat -edata 0x0 \
89 10 wfjm
      -wreg te.data 0x1234
90 27 wfjm
    rlc log "  test 3b: verify that init 010 clears data and not cntl,stat"
91
    set valc [regbld rbtest::CNTL {nbusy 2}]
92 30 wfjm
    rlc exec \
93 10 wfjm
      -wreg te.cntl $valc \
94 27 wfjm
      -wreg te.stat 0x0003 \
95 10 wfjm
      -wreg te.data 0x4321 \
96
      -init te.cntl [regbld rbtest::INIT data] \
97
      -rreg te.cntl -edata $valc \
98 27 wfjm
      -rreg te.stat -edata 0x0003 \
99 10 wfjm
      -wreg te.data 0x0
100 27 wfjm
    rlc log "  test 3c: verify that init 011 clears data and cntl,stat"
101 30 wfjm
    rlc exec \
102 27 wfjm
      -wreg te.cntl [regbld rbtest::CNTL {nbusy 3}] \
103
      -wreg te.stat 0x0004 \
104 10 wfjm
      -wreg te.data 0xabcd \
105
      -init te.cntl [regbld rbtest::INIT data cntl] \
106
      -rreg te.cntl -edata 0x0 \
107 27 wfjm
      -rreg te.stat -edata 0x0 \
108 10 wfjm
      -wreg te.data 0x0
109
    #
110
    # -------------------------------------------------------------------------
111 27 wfjm
    rlc log "  test 4: test that te.ncyc returns # of cycles for te.data w&r"
112 10 wfjm
    foreach nbusy {0x03 0x07 0x0f 0x1f 0x00} {
113
      set valc [regbld rbtest::CNTL [list nbusy $nbusy]]
114 30 wfjm
      rlc exec \
115 10 wfjm
        -wreg te.cntl $valc \
116 21 wfjm
        -wreg te.data [expr {$nbusy | ( $nbusy << 8 ) }] \
117 27 wfjm
        -rreg te.ncyc -edata [expr {$nbusy + 1 }] \
118 21 wfjm
        -rreg te.data -edata [expr {$nbusy | ( $nbusy << 8 ) }] \
119 27 wfjm
        -rreg te.ncyc -edata [expr {$nbusy + 1 }]
120 10 wfjm
    }
121
    #
122
    #-------------------------------------------------------------------------
123
    rlc log "rbtest::test_data - cleanup: clear cntl and data"
124
    rlc exec -init te.cntl [regbld rbtest::INIT data cntl]
125
    #
126
    incr errcnt [rlc errcnt -clear]
127
    return $errcnt
128
  }
129
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.