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-- $Id: rlink_sp1c_fx2.vhd 672 2015-05-02 21:58:28Z mueller $
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--
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-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: rlink_sp1c_fx2 - syn
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-- Description: rlink_core8 + serport_1clock + fx2 combo
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--
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-- Dependencies: rlinklib/rlink_core8
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-- serport/serport_1clock
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-- rlinklib/rlink_rlbmux
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-- fx2lib/fx2_2fifoctl_ic
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-- rbus/rbd_rbmon
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-- rbus/rb_sres_or_2
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--
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-- Test bench: -
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--
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-- Target Devices: generic
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-- Tool versions: xst 13.1-14.7; viv 2014.4; ghdl 0.29-0.31
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--
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri ifa ofa
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-- 2015-05-02 672 14.7 131013 xc6slx16-2 618 875 90 340 s 7.2 - -
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-- 2013-04-20 509 13.3 O76d xc3s1200e-4 441 903 128 637 s 8.7 - -
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2015-05-02 672 1.3 add rbd_rbmon (optional via generics)
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-- 2015-04-11 666 1.2 drop ENAESC, rearrange XON handling
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-- 2014-08-28 588 1.1 use new rlink v4 iface generics and 4 bit STAT
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-- 2013-04-20 509 1.0 Initial version (derived from rlink_sp1c)
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.rblib.all;
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use work.rbdlib.all;
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use work.rlinklib.all;
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use work.serportlib.all;
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use work.fx2lib.all;
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entity rlink_sp1c_fx2 is -- rlink_core8+serport_1clk+fx2_ic combo
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generic (
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BTOWIDTH : positive := 5; -- rbus timeout counter width
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RTAWIDTH : positive := 12; -- retransmit buffer address width
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SYSID : slv32 := (others=>'0'); -- rlink system id
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IFAWIDTH : natural := 5; -- ser input fifo addr width (0=none)
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OFAWIDTH : natural := 5; -- ser output fifo addr width (0=none)
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PETOWIDTH : positive := 10; -- fx2 packet end time-out counter width
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CCWIDTH : positive := 5; -- fx2 chunk counter width
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ENAPIN_RLMON : integer := -1; -- SB_CNTL for rlmon (-1=none)
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ENAPIN_RLBMON: integer := -1; -- SB_CNTL for rlbmon (-1=none)
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ENAPIN_RBMON : integer := -1; -- SB_CNTL for rbmon (-1=none)
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CDWIDTH : positive := 13; -- clk divider width
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CDINIT : natural := 15; -- clk divider initial/reset setting
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RBMON_AWIDTH : natural := 0; -- rbmon: buffer size, (0=none)
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RBMON_RBADDR : slv16 := slv(to_unsigned(16#ffe8#,16))); -- rbmon: base addr
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port (
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CLK : in slbit; -- clock
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CE_USEC : in slbit; -- 1 usec clock enable
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CE_MSEC : in slbit; -- 1 msec clock enable
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CE_INT : in slbit := '0'; -- rri ato time unit clock enable
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RESET : in slbit; -- reset
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ENAXON : in slbit; -- enable xon/xoff handling
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ENAFX2 : in slbit; -- enable fx2 usage
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RXSD : in slbit; -- receive serial data (board view)
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TXSD : out slbit; -- transmit serial data (board view)
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CTS_N : in slbit := '0'; -- clear to send (act.low, board view)
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RTS_N : out slbit; -- request to send (act.low, board view)
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RB_MREQ : out rb_mreq_type; -- rbus: request
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RB_SRES : in rb_sres_type; -- rbus: response
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RB_LAM : in slv16; -- rbus: look at me
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RB_STAT : in slv4; -- rbus: status flags
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RL_MONI : out rl_moni_type; -- rlink_core: monitor port
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RLB_MONI : out rlb_moni_type; -- rlink 8b: monitor port
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SER_MONI : out serport_moni_type; -- ser: monitor port
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FX2_MONI : out fx2ctl_moni_type; -- fx2: monitor port
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I_FX2_IFCLK : in slbit; -- fx2: interface clock
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O_FX2_FIFO : out slv2; -- fx2: fifo address
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I_FX2_FLAG : in slv4; -- fx2: fifo flags
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O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
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O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
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O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
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O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
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IO_FX2_DATA : inout slv8 -- fx2: data lines
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);
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end entity rlink_sp1c_fx2;
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architecture syn of rlink_sp1c_fx2 is
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signal RLB_DI : slv8 := (others=>'0');
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signal RLB_ENA : slbit := '0';
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signal RLB_BUSY : slbit := '0';
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signal RLB_DO : slv8 := (others=>'0');
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signal RLB_VAL : slbit := '0';
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signal RLB_HOLD : slbit := '0';
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signal SER_RXDATA : slv8 := (others=>'0');
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signal SER_RXVAL : slbit := '0';
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signal SER_RXHOLD : slbit := '0';
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signal SER_TXDATA : slv8 := (others=>'0');
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signal SER_TXENA : slbit := '0';
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signal SER_TXBUSY : slbit := '0';
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signal FX2_RXDATA : slv8 := (others=>'0');
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signal FX2_RXVAL : slbit := '0';
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signal FX2_RXHOLD : slbit := '0';
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signal FX2_RXAEMPTY : slbit := '0';
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signal FX2_TXDATA : slv8 := (others=>'0');
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signal FX2_TXENA : slbit := '0';
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signal FX2_TXBUSY : slbit := '0';
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signal FX2_TXAFULL : slbit := '0';
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signal RB_MREQ_M : rb_mreq_type := rb_mreq_init;
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signal RB_SRES_M : rb_sres_type := rb_sres_init;
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signal RB_SRES_RBMON : rb_sres_type := rb_sres_init;
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begin
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CORE : rlink_core8 -- rlink master ----------------------
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generic map (
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BTOWIDTH => BTOWIDTH,
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RTAWIDTH => RTAWIDTH,
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SYSID => SYSID,
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ENAPIN_RLMON => ENAPIN_RLMON,
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ENAPIN_RLBMON=> ENAPIN_RLBMON,
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ENAPIN_RBMON => ENAPIN_RBMON)
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port map (
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CLK => CLK,
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CE_INT => CE_INT,
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RESET => RESET,
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ESCXON => ENAXON,
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ESCFILL => '0', -- not used in FX2 enabled boards
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RLB_DI => RLB_DI,
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RLB_ENA => RLB_ENA,
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RLB_BUSY => RLB_BUSY,
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RLB_DO => RLB_DO,
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RLB_VAL => RLB_VAL,
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RLB_HOLD => RLB_HOLD,
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RL_MONI => RL_MONI,
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RB_MREQ => RB_MREQ_M,
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RB_SRES => RB_SRES_M,
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RB_LAM => RB_LAM,
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RB_STAT => RB_STAT
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);
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SERPORT : serport_1clock -- serport interface -----------------
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generic map (
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CDWIDTH => CDWIDTH,
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CDINIT => CDINIT,
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RXFAWIDTH => IFAWIDTH,
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TXFAWIDTH => OFAWIDTH)
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port map (
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CLK => CLK,
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CE_MSEC => CE_MSEC,
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RESET => RESET,
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ENAXON => ENAXON,
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ENAESC => '0', -- escaping now in rlink_core8
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RXDATA => SER_RXDATA,
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RXVAL => SER_RXVAL,
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RXHOLD => SER_RXHOLD,
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TXDATA => SER_TXDATA,
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TXENA => SER_TXENA,
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TXBUSY => SER_TXBUSY,
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MONI => SER_MONI,
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RXSD => RXSD,
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TXSD => TXSD,
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RXRTS_N => RTS_N,
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TXCTS_N => CTS_N
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);
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RLBMUX : rlink_rlbmux -- rlink control mux -----------------
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port map (
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SEL => ENAFX2,
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RLB_DI => RLB_DI,
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RLB_ENA => RLB_ENA,
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RLB_BUSY => RLB_BUSY,
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RLB_DO => RLB_DO,
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RLB_VAL => RLB_VAL,
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RLB_HOLD => RLB_HOLD,
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P0_RXDATA => SER_RXDATA,
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P0_RXVAL => SER_RXVAL,
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P0_RXHOLD => SER_RXHOLD,
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P0_TXDATA => SER_TXDATA,
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P0_TXENA => SER_TXENA,
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P0_TXBUSY => SER_TXBUSY,
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P1_RXDATA => FX2_RXDATA,
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P1_RXVAL => FX2_RXVAL,
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P1_RXHOLD => FX2_RXHOLD,
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P1_TXDATA => FX2_TXDATA,
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P1_TXENA => FX2_TXENA,
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P1_TXBUSY => FX2_TXBUSY
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);
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RLB_MONI.rxval <= RLB_VAL;
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RLB_MONI.rxhold <= RLB_HOLD;
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RLB_MONI.txena <= RLB_ENA;
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RLB_MONI.txbusy <= RLB_BUSY;
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FX2CNTL : fx2_2fifoctl_ic -- FX2 interface ---------------------
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generic map (
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RXFAWIDTH => 5,
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TXFAWIDTH => 5,
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PETOWIDTH => PETOWIDTH,
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CCWIDTH => CCWIDTH,
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RXAEMPTY_THRES => 1,
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TXAFULL_THRES => 1)
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port map (
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CLK => CLK,
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RESET => RESET,
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RXDATA => FX2_RXDATA,
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RXVAL => FX2_RXVAL,
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RXHOLD => FX2_RXHOLD,
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RXAEMPTY => FX2_RXAEMPTY,
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TXDATA => FX2_TXDATA,
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TXENA => FX2_TXENA,
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TXBUSY => FX2_TXBUSY,
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TXAFULL => FX2_TXAFULL,
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MONI => FX2_MONI,
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I_FX2_IFCLK => I_FX2_IFCLK,
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O_FX2_FIFO => O_FX2_FIFO,
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I_FX2_FLAG => I_FX2_FLAG,
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O_FX2_SLRD_N => O_FX2_SLRD_N,
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O_FX2_SLWR_N => O_FX2_SLWR_N,
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O_FX2_SLOE_N => O_FX2_SLOE_N,
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O_FX2_PKTEND_N => O_FX2_PKTEND_N,
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IO_FX2_DATA => IO_FX2_DATA
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);
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RBMON : if RBMON_AWIDTH > 0 generate -- rbus monitor --------------
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begin
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I0 : rbd_rbmon
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generic map (
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RB_ADDR => RBMON_RBADDR,
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AWIDTH => RBMON_AWIDTH)
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port map (
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CLK => CLK,
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RESET => RESET,
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RB_MREQ => RB_MREQ_M,
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RB_SRES => RB_SRES_RBMON,
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RB_SRES_SUM => RB_SRES_M
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);
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end generate RBMON;
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RB_SRES_OR : rb_sres_or_2 -- rbus or ---------------------------
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port map (
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RB_SRES_1 => RB_SRES,
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RB_SRES_2 => RB_SRES_RBMON,
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RB_SRES_OR => RB_SRES_M
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);
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RB_MREQ <= RB_MREQ_M; -- setup output signals
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end syn;
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