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[/] [w11/] [tags/] [w11a_V0.74/] [rtl/] [bplib/] [nexys2/] [nexys2lib.vhd] - Blame information for rev 8

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-- $Id: nexys2lib.vhd 338 2010-11-13 22:19:25Z mueller $
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--
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-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Package Name:   nexys2lib
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-- Description:    Nexys 2 components
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--
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-- Dependencies:   -
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-- Tool versions:  xst 11.4, 12.1; ghdl 0.26-0.29
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--
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-- Revision History:
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-- Date         Rev Version  Comment
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-- 2010-11-13   338   1.0.2  add O_CLKSYS to aif's (DCM derived system clock)
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-- 2010-11-06   336   1.0.4  rename input pin CLK -> I_CLK50
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-- 2010-05-28   295   1.0.3  use _ADV_N also for n2_cram_dummy
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-- 2010-05-23   294   1.0.2  add n2_cram_dummy;
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-- 2010-05-23   293   1.0.1  use _ADV_N rather _ADV; add generic for memctl
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-- 2010-05-21   292   1.0    Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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package nexys2lib is
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component nexys2_aif is                 -- NEXYS 2, abstract iface, base
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  port (
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    I_CLK50 : in slbit;                 -- 50 MHz board clock
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    O_CLKSYS : out slbit;               -- DCM derived system clock
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    I_RXD : in slbit;                   -- receive data (board view)
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    O_TXD : out slbit;                  -- transmit data (board view)
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    I_SWI : in slv8;                    -- s3 switches
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    I_BTN : in slv4;                    -- s3 buttons
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    O_LED : out slv8;                   -- s3 leds
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    O_ANO_N : out slv4;                 -- 7 segment disp: anodes   (act.low)
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    O_SEG_N : out slv8;                 -- 7 segment disp: segments (act.low)
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    O_MEM_CE_N : out slbit;             -- cram: chip enable   (act.low)
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    O_MEM_BE_N : out slv2;              -- cram: byte enables  (act.low)
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    O_MEM_WE_N : out slbit;             -- cram: write enable  (act.low)
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    O_MEM_OE_N : out slbit;             -- cram: output enable (act.low)
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    O_MEM_ADV_N  : out slbit;           -- cram: address valid (act.low)
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    O_MEM_CLK : out slbit;              -- cram: clock
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    O_MEM_CRE : out slbit;              -- cram: command register enable
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    I_MEM_WAIT : in slbit;              -- cram: mem wait
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    O_FLA_CE_N : out slbit;               -- flash ce..        (act.low)
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    O_MEM_ADDR  : out slv23;            -- cram: address lines
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    IO_MEM_DATA : inout slv16           -- cram: data lines
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  );
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end component;
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component nexys2_fusp_aif is           -- NEXYS 2, abstract iface, base+fusp
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  port (
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    I_CLK50 : in slbit;                 -- 50 MHz board clock
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    O_CLKSYS : out slbit;               -- DCM derived system clock
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    I_RXD : in slbit;                   -- receive data (board view)
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    O_TXD : out slbit;                  -- transmit data (board view)
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    I_SWI : in slv8;                    -- s3 switches
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    I_BTN : in slv4;                    -- s3 buttons
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    O_LED : out slv8;                   -- s3 leds
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    O_ANO_N : out slv4;                 -- 7 segment disp: anodes   (act.low)
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    O_SEG_N : out slv8;                 -- 7 segment disp: segments (act.low)
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    O_MEM_CE_N : out slbit;             -- cram: chip enable   (act.low)
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    O_MEM_BE_N : out slv2;              -- cram: byte enables  (act.low)
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    O_MEM_WE_N : out slbit;             -- cram: write enable  (act.low)
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    O_MEM_OE_N : out slbit;             -- cram: output enable (act.low)
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    O_MEM_ADV_N  : out slbit;           -- cram: address valid (act.low)
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    O_MEM_CLK : out slbit;              -- cram: clock
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    O_MEM_CRE : out slbit;              -- cram: command register enable
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    I_MEM_WAIT : in slbit;              -- cram: mem wait
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    O_FLA_CE_N : out slbit;             -- flash ce..          (act.low)
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    O_MEM_ADDR  : out slv23;            -- cram: address lines
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    IO_MEM_DATA : inout slv16;          -- cram: data lines
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    O_FUSP_RTS_N : out slbit;           -- fusp: rs232 rts_n
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    I_FUSP_CTS_N : in slbit;            -- fusp: rs232 cts_n
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    I_FUSP_RXD : in slbit;              -- fusp: rs232 rx
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    O_FUSP_TXD : out slbit              -- fusp: rs232 tx
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  );
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end component;
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component n2_cram_dummy is              -- CRAM protection dummy
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  port (
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    O_MEM_CE_N : out slbit;             -- cram: chip enable   (act.low)
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    O_MEM_BE_N : out slv2;              -- cram: byte enables  (act.low)
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    O_MEM_WE_N : out slbit;             -- cram: write enable  (act.low)
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    O_MEM_OE_N : out slbit;             -- cram: output enable (act.low)
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    O_MEM_ADV_N  : out slbit;           -- cram: address valid (act.low)
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    O_MEM_CLK : out slbit;              -- cram: clock
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    O_MEM_CRE : out slbit;              -- cram: command register enable
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    I_MEM_WAIT : in slbit;              -- cram: mem wait
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    O_FLA_CE_N : out slbit;             -- flash ce..          (act.low)
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    O_MEM_ADDR  : out slv23;            -- cram: address lines
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    IO_MEM_DATA : inout slv16           -- cram: data lines
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  );
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end component;
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component n2_cram_memctl_as is          -- CRAM driver (async+page mode)
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  generic (
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    READ0DELAY : positive := 2;         -- read word 0 delay in clock cycles
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    READ1DELAY : positive := 2;         -- read word 1 delay in clock cycles
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    WRITEDELAY : positive := 3);        -- write delay in clock cycles
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  port (
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    CLK : in slbit;                     -- clock
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    RESET : in slbit;                   -- reset
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    REQ   : in slbit;                   -- request
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    WE    : in slbit;                   -- write enable
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    BUSY : out slbit;                   -- controller busy
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    ACK_R : out slbit;                  -- acknowledge read
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    ACK_W : out slbit;                  -- acknowledge write
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    ACT_R : out slbit;                  -- signal active read
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    ACT_W : out slbit;                  -- signal active write
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    ADDR : in slv22;                    -- address (32 bit word address)
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    BE : in slv4;                       -- byte enable
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    DI : in slv32;                      -- data in  (memory view)
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    DO : out slv32;                     -- data out (memory view)
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    O_MEM_CE_N : out slbit;             -- cram: chip enable   (act.low)
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    O_MEM_BE_N : out slv2;              -- cram: byte enables  (act.low)
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    O_MEM_WE_N : out slbit;             -- cram: write enable  (act.low)
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    O_MEM_OE_N : out slbit;             -- cram: output enable (act.low)
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    O_MEM_ADV_N : out slbit;            -- cram: address valid (act.low)
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    O_MEM_CLK : out slbit;              -- cram: clock
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    O_MEM_CRE : out slbit;              -- cram: command register enable
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    I_MEM_WAIT : in slbit;              -- cram: mem wait
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    O_FLA_CE_N : out slbit;             -- flash ce..          (act.low)
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    O_MEM_ADDR  : out slv23;            -- cram: address lines
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    IO_MEM_DATA : inout slv16           -- cram: data lines
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  );
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end component;
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end nexys2lib;

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