1 |
29 |
wfjm |
-- $Id: nexys4lib.vhd 643 2015-02-07 17:41:53Z mueller $
|
2 |
|
|
--
|
3 |
|
|
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
4 |
|
|
--
|
5 |
|
|
-- This program is free software; you may redistribute and/or modify it under
|
6 |
|
|
-- the terms of the GNU General Public License as published by the Free
|
7 |
|
|
-- Software Foundation, either version 2, or at your option any later version.
|
8 |
|
|
--
|
9 |
|
|
-- This program is distributed in the hope that it will be useful, but
|
10 |
|
|
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
|
11 |
|
|
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
12 |
|
|
-- for complete details.
|
13 |
|
|
--
|
14 |
|
|
------------------------------------------------------------------------------
|
15 |
|
|
-- Package Name: nexys4lib
|
16 |
|
|
-- Description: Nexys 4 components
|
17 |
|
|
--
|
18 |
|
|
-- Dependencies: -
|
19 |
|
|
-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31
|
20 |
|
|
--
|
21 |
|
|
-- Revision History:
|
22 |
|
|
-- Date Rev Version Comment
|
23 |
|
|
-- 2015-02-06 643 1.2 factor out memory, add nexys4_cram_aif
|
24 |
|
|
-- 2015-02-01 641 1.1 drop nexys4_fusp_aif; separate I_BTNRST_N
|
25 |
|
|
-- 2013-09-21 534 1.0 Initial version
|
26 |
|
|
------------------------------------------------------------------------------
|
27 |
|
|
|
28 |
|
|
library ieee;
|
29 |
|
|
use ieee.std_logic_1164.all;
|
30 |
|
|
|
31 |
|
|
use work.slvtypes.all;
|
32 |
|
|
|
33 |
|
|
package nexys4lib is
|
34 |
|
|
|
35 |
|
|
component nexys4_aif is -- NEXYS 4, abstract iface, base
|
36 |
|
|
port (
|
37 |
|
|
I_CLK100 : in slbit; -- 100 MHz clock
|
38 |
|
|
I_RXD : in slbit; -- receive data (board view)
|
39 |
|
|
O_TXD : out slbit; -- transmit data (board view)
|
40 |
|
|
O_RTS_N : out slbit; -- rx rts (board view; act.low)
|
41 |
|
|
I_CTS_N : in slbit; -- tx cts (board view; act.low)
|
42 |
|
|
I_SWI : in slv16; -- n4 switches
|
43 |
|
|
I_BTN : in slv5; -- n4 buttons
|
44 |
|
|
I_BTNRST_N : in slbit; -- n4 reset button
|
45 |
|
|
O_LED : out slv16; -- n4 leds
|
46 |
|
|
O_RGBLED0 : out slv3; -- n4 rgb-led 0
|
47 |
|
|
O_RGBLED1 : out slv3; -- n4 rgb-led 1
|
48 |
|
|
O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
|
49 |
|
|
O_SEG_N : out slv8 -- 7 segment disp: segments (act.low)
|
50 |
|
|
);
|
51 |
|
|
end component;
|
52 |
|
|
|
53 |
|
|
component nexys4_cram_aif is -- NEXYS 4, abstract iface, base+cram
|
54 |
|
|
port (
|
55 |
|
|
I_CLK100 : in slbit; -- 100 MHz clock
|
56 |
|
|
I_RXD : in slbit; -- receive data (board view)
|
57 |
|
|
O_TXD : out slbit; -- transmit data (board view)
|
58 |
|
|
O_RTS_N : out slbit; -- rx rts (board view; act.low)
|
59 |
|
|
I_CTS_N : in slbit; -- tx cts (board view; act.low)
|
60 |
|
|
I_SWI : in slv16; -- n4 switches
|
61 |
|
|
I_BTN : in slv5; -- n4 buttons
|
62 |
|
|
I_BTNRST_N : in slbit; -- n4 reset button
|
63 |
|
|
O_LED : out slv16; -- n4 leds
|
64 |
|
|
O_RGBLED0 : out slv3; -- n4 rgb-led 0
|
65 |
|
|
O_RGBLED1 : out slv3; -- n4 rgb-led 1
|
66 |
|
|
O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
|
67 |
|
|
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
|
68 |
|
|
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
|
69 |
|
|
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
|
70 |
|
|
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
|
71 |
|
|
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
|
72 |
|
|
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
|
73 |
|
|
O_MEM_CLK : out slbit; -- cram: clock
|
74 |
|
|
O_MEM_CRE : out slbit; -- cram: command register enable
|
75 |
|
|
I_MEM_WAIT : in slbit; -- cram: mem wait
|
76 |
|
|
O_MEM_ADDR : out slv23; -- cram: address lines
|
77 |
|
|
IO_MEM_DATA : inout slv16 -- cram: data lines
|
78 |
|
|
);
|
79 |
|
|
end component;
|
80 |
|
|
|
81 |
|
|
end package nexys4lib;
|