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-- $Id: ibdr_rhrp.vhd 680 2015-05-14 13:29:46Z mueller $
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--
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-- Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: ibdr_rhrp - syn
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-- Description: ibus dev(rem): RHRP
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--
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-- Dependencies: ram_1swar_gen
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-- Test bench: -
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-- Target Devices: generic
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-- Tool versions: ise 14.7; viv 2014.4; ghdl 0.31
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--
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2015-05-14 680 14.7 131013 xc6slx16-2 211 408 8 131 s 8.8
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-- 2015-04-06 664 14.7 131013 xc6slx16-2 177 331 8 112 s 8.7
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2015-05-14 680 1.0 Initial version
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-- 2015-03-15 658 0.1 First draft
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.memlib.all;
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use work.iblib.all;
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-- ----------------------------------------------------------------------------
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entity ibdr_rhrp is -- ibus dev(rem): RH+RP
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-- fixed address: 176700
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port (
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CLK : in slbit; -- clock
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CE_USEC : in slbit; -- usec pulse
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BRESET : in slbit; -- ibus reset
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ITIMER : in slbit; -- instruction timer
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RB_LAM : out slbit; -- remote attention
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_SRES : out ib_sres_type; -- ibus response
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EI_REQ : out slbit; -- interrupt request
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EI_ACK : in slbit -- interrupt acknowledge
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);
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-- by default xst uses a binary encoding for the main fsm.
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-- that give quite sub-optimal results, so force one-hot
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attribute fsm_encoding : string;
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attribute fsm_encoding of ibdr_rhrp : entity is "one-hot";
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end entity ibdr_rhrp;
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architecture syn of ibdr_rhrp is
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constant ibaddr_rhrp : slv16 := slv(to_unsigned(8#176700#,16));
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-- nam rw mb rp rm storage
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constant ibaddr_cs1 : slv5 := "00000"; -- cs1 rw 0 rpcs1 rmcs1 m d,6+r
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constant ibaddr_wc : slv5 := "00001"; -- wc rw - rpwc rmwc m 0,7
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constant ibaddr_ba : slv5 := "00010"; -- ba rw - rpba rmba m 1,7
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constant ibaddr_da : slv5 := "00011"; -- da rw 5 rpda rmda m d,0
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constant ibaddr_cs2 : slv5 := "00100"; -- cs2 rw - rpcs2 rmcs2 r cs2*
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constant ibaddr_ds : slv5 := "00101"; -- ds r- 1 rpds rmds r ds*
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constant ibaddr_er1 : slv5 := "00110"; -- er1 rw 2 rper1 rmer1 r er1*
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constant ibaddr_as : slv5 := "00111"; -- as rw 4 rpas rmas r as*
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constant ibaddr_la : slv5 := "01000"; -- la r- 7 rpla rmla r sc
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constant ibaddr_db : slv5 := "01001"; -- db r? - rpdb rmdb m 2,7
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constant ibaddr_mr1 : slv5 := "01010"; -- mr1 rw 3 rpmr1 rmmr1 m d,3
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constant ibaddr_dt : slv5 := "01011"; -- dt r- 6 rpdt rmdt r dt*+map
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constant ibaddr_sn : slv5 := "01100"; -- sn r- 10 rpsn rmsn <map>
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constant ibaddr_of : slv5 := "01101"; -- of rw 11 rpof rmof m d,1
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constant ibaddr_dc : slv5 := "01110"; -- dc rw 12 rpdc rmdc m d,2
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constant ibaddr_m13 : slv5 := "01111"; -- m13 rw 13 rpcc m =dc!
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-- rw 13 rmhr m d,4
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constant ibaddr_m14 : slv5 := "10000"; -- m14 rw 14 rper2 =0
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-- rw 14 rmmr2 m d,5
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constant ibaddr_m15 : slv5 := "10001"; -- m15 rw 15 rper3 =0
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-- rw 15 rmer2 =0
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constant ibaddr_ec1 : slv5 := "10010"; -- ec1 r- 16 rpec1 rmec1 =0
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constant ibaddr_ec2 : slv5 := "10011"; -- ec1 r- 17 rpec2 rmec2 =0
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constant ibaddr_bae : slv5 := "10100"; -- bae rw - rpbae rmbae r bae
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constant ibaddr_cs3 : slv5 := "10101"; -- cs3 rw - rpcs3 rmcs3 r cs3*
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constant omux_cs1 : slv4 := "0000";
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constant omux_cs2 : slv4 := "0001";
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constant omux_ds : slv4 := "0010";
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constant omux_er1 : slv4 := "0011";
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constant omux_as : slv4 := "0100";
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constant omux_la : slv4 := "0101";
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constant omux_dt : slv4 := "0110";
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constant omux_sn : slv4 := "0111";
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constant omux_bae : slv4 := "1000";
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constant omux_cs3 : slv4 := "1001";
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constant omux_mem : slv4 := "1010";
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constant omux_zero : slv4 := "1111";
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constant amapc_da : slv3 := "000";
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constant amapc_mr1 : slv3 := "011";
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constant amapc_of : slv3 := "001";
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constant amapc_dc : slv3 := "010";
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constant amapc_hr : slv3 := "100";
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constant amapc_mr2 : slv3 := "101";
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constant amapc_cs1 : slv3 := "110";
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constant amapc_ext : slv3 := "111";
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constant amapr_wc : slv2 := "00";
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constant amapr_ba : slv2 := "01";
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constant amapr_db : slv2 := "10";
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subtype amap_f_unit is integer range 4 downto 3; -- unit part
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subtype amap_f_reg is integer range 2 downto 0; -- reg part
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constant clrmode_breset : slv2 := "00";
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constant clrmode_cs2clr : slv2 := "01";
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constant clrmode_fdclr : slv2 := "10";
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constant clrmode_fpres : slv2 := "11";
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constant cs1_ibf_sc : integer := 15; -- special condition
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constant cs1_ibf_tre : integer := 14; -- transfer error
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constant cs1_ibf_dva : integer := 11; -- drive available
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subtype cs1_ibf_bae is integer range 9 downto 8; -- bus addr ext (1:0)
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constant cs1_ibf_rdy : integer := 7; -- controller ready
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constant cs1_ibf_ie : integer := 6; -- interrupt enable
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subtype cs1_ibf_func is integer range 5 downto 1; -- function code
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constant cs1_ibf_go : integer := 0; -- interrupt enable
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constant func_noop : slv5 := "00000"; -- func: noop
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constant func_unl : slv5 := "00001"; -- func: unload
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constant func_seek : slv5 := "00010"; -- func: seek
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constant func_recal : slv5 := "00011"; -- func: recalibrate
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constant func_dclr : slv5 := "00100"; -- func: drive clear
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constant func_pore : slv5 := "00101"; -- func: port release
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constant func_offs : slv5 := "00110"; -- func: offset
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constant func_retc : slv5 := "00111"; -- func: return to center
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constant func_pres : slv5 := "01000"; -- func: readin preset
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constant func_pack : slv5 := "01001"; -- func: pack acknowledge
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constant func_sear : slv5 := "01100"; -- func: search
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constant func_wcd : slv5 := "10100"; -- func: write check data
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constant func_wchd : slv5 := "10101"; -- func: write check header&data
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constant func_write : slv5 := "11000"; -- func: write
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constant func_whd : slv5 := "11001"; -- func: write header&data
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constant func_read : slv5 := "11100"; -- func: read
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constant func_rhd : slv5 := "11101"; -- func: read header&data
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constant rfunc_wunit : slv5 := "00001"; -- rem func: write runit
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constant rfunc_cunit : slv5 := "00010"; -- rem func: copy funit->runit
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constant rfunc_done : slv5 := "00011"; -- rem func: done (set rdy)
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constant rfunc_widly : slv5 := "00100"; -- rem func: write idly
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-- cs1 usage for rem functions
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subtype cs1_ibf_runit is integer range 9 downto 8; -- new runit (_wunit)
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constant cs1_ibf_rata : integer := 8; -- use ata (_done)
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subtype cs1_ibf_ridly is integer range 15 downto 8; -- new idly (_widly)
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subtype da_ibf_ta is integer range 12 downto 8; -- track addr
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subtype da_ibf_sa is integer range 5 downto 0; -- sector addr
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constant cs2_ibf_rwco : integer := 15; -- rem: write check odd word
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constant cs2_ibf_wce : integer := 14; -- write check error
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constant cs2_ibf_ned : integer := 12; -- non-existant drive
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constant cs2_ibf_nem : integer := 11; -- non-existant memory
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constant cs2_ibf_pge : integer := 10; -- programming error
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constant cs2_ibf_mxf : integer := 9; -- missed transfer
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constant cs2_ibf_or : integer := 7; -- output ready
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constant cs2_ibf_ir : integer := 6; -- input ready
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constant cs2_ibf_clr : integer := 5; -- clear controller
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constant cs2_ibf_pat : integer := 4; -- parity test
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constant cs2_ibf_bai : integer := 3; -- bus address inhibit
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constant cs2_ibf_unit2 : integer := 2; -- unit select msb
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subtype cs2_ibf_unit is integer range 1 downto 0; -- unit select
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constant ds_ibf_ata : integer := 15; -- attention
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constant ds_ibf_erp : integer := 14; -- any errors in er1 or er2
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constant ds_ibf_pip : integer := 13; -- positioning in progress
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constant ds_ibf_mol : integer := 12; -- medium online (ATTACHED)
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constant ds_ibf_wrl : integer := 11; -- write locked
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constant ds_ibf_lbt : integer := 10; -- last block transfered
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constant ds_ibf_dpr : integer := 8; -- drive present (ENABLED)
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constant ds_ibf_dry : integer := 7; -- drive ready
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constant ds_ibf_vv : integer := 6; -- volume valid
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constant ds_ibf_om : integer := 0; -- offset mode
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constant er1_ibf_uns : integer := 14; -- drive unsafe
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constant er1_ibf_wle : integer := 11; -- write lock error
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constant er1_ibf_iae : integer := 10; -- invalid address error
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constant er1_ibf_aoe : integer := 9; -- address overflow error
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constant er1_ibf_rmr : integer := 2; -- register modification refused
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constant er1_ibf_ilf : integer := 0; -- illegal function
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subtype la_ibf_sc is integer range 11 downto 6; -- current sector
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constant dt_ibf_rm : integer := 2; -- rm cntl
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constant dt_ibf_e1 : integer := 1; -- encoded type bit 1
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constant dt_ibf_e0 : integer := 0; -- encoded type bit 0
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constant dte_rp04 : slv3 := "000"; -- encoded dt for rp04 rm=0
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constant dte_rp06 : slv3 := "001"; -- encoded dt for rp06 rm=0
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constant dte_rm03 : slv3 := "100"; -- encoded dt for rm03 rm=1
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constant dte_rm80 : slv3 := "101"; -- encoded dt for rm80 rm=1
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constant dte_rm05 : slv3 := "110"; -- encoded dt for rm05 rm=1
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constant dte_rp07 : slv3 := "111"; -- encoded dt for rp07 rm=1
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subtype dc_ibf_ca is integer range 9 downto 0; -- cyclinder addr
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subtype bae_ibf_bae is integer range 5 downto 0; -- bus addr ext.
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constant cs3_ibf_wco : integer := 12; -- write check odd
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constant cs3_ibf_wce : integer := 11; -- write check even
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constant cs3_ibf_ie : integer := 6; -- interrupt enable
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constant cs3_ibf_rseardone : integer := 3; -- rem: sear done flag
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constant cs3_ibf_rpackdone : integer := 2; -- rem: pack done flag
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constant cs3_ibf_rporedone : integer := 1; -- rem: pore done flag
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constant cs3_ibf_rseekdone : integer := 0; -- rem: seek done flag
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-- RP controller type disks
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constant rp04_dtyp : slv6 := slv(to_unsigned( 8#20#, 6));
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constant rp04_camax : slv10 := slv(to_unsigned( 411-1, 10));
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constant rp04_tamax : slv5 := slv(to_unsigned( 19-1, 5));
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constant rp04_samax : slv6 := slv(to_unsigned( 22-1, 6));
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constant rp06_dtyp : slv6 := slv(to_unsigned( 8#22#, 6));
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constant rp06_camax : slv10 := slv(to_unsigned( 815-1, 10));
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constant rp06_tamax : slv5 := slv(to_unsigned( 19-1, 5));
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constant rp06_samax : slv6 := slv(to_unsigned( 22-1, 6));
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-- RM controller type disks (Note: rp07 has a RM stype controller!)
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constant rm03_dtyp : slv6 := slv(to_unsigned( 8#24#, 6));
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constant rm03_camax : slv10 := slv(to_unsigned( 823-1, 10));
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constant rm03_tamax : slv5 := slv(to_unsigned( 5-1, 5));
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constant rm03_samax : slv6 := slv(to_unsigned( 32-1, 6));
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constant rm80_dtyp : slv6 := slv(to_unsigned( 8#26#, 6));
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constant rm80_camax : slv10 := slv(to_unsigned( 559-1, 10));
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constant rm80_tamax : slv5 := slv(to_unsigned( 14-1, 5));
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constant rm80_samax : slv6 := slv(to_unsigned( 31-1, 6));
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constant rm05_dtyp : slv6 := slv(to_unsigned( 8#27#, 6));
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constant rm05_camax : slv10 := slv(to_unsigned( 823-1, 10));
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constant rm05_tamax : slv5 := slv(to_unsigned( 19-1, 5));
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constant rm05_samax : slv6 := slv(to_unsigned( 32-1, 6));
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constant rp07_dtyp : slv6 := slv(to_unsigned( 8#42#, 6));
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constant rp07_camax : slv10 := slv(to_unsigned( 630-1, 10));
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constant rp07_tamax : slv5 := slv(to_unsigned( 32-1, 5));
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constant rp07_samax : slv6 := slv(to_unsigned( 50-1, 6));
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type state_type is (
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s_idle, -- idle: handle ibus
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s_wcs1, -- wcs1: write cs1
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s_wcs2, -- wcs2: write cs2
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s_wcs3, -- wcs3: write cs3
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s_wer1, -- wer1: write er1 (rem only)
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s_was, -- was: write as
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|
|
s_wdt, -- wdt: write dt (rem only)
|
| 266 |
|
|
s_wds, -- wdt: write ds (rem only)
|
| 267 |
|
|
s_wbae, -- wbae: write bae
|
| 268 |
|
|
s_wmem, -- wmem: write mem (DA,MR1,OF,DC,MR2)
|
| 269 |
|
|
s_wmembe, -- wmem: write mem with be (WC,BA,DB)
|
| 270 |
|
|
s_whr, -- whr: write hr (holding reg only)
|
| 271 |
|
|
s_funcgo, -- funcgo: handle function go
|
| 272 |
|
|
s_chkdc, -- chkdc: handle dc check
|
| 273 |
|
|
s_chkda, -- chksa: handle da check
|
| 274 |
|
|
s_chkdo, -- chkdo: execute function
|
| 275 |
|
|
s_read, -- read: all register reads
|
| 276 |
|
|
s_setrmr, -- set rmr flag
|
| 277 |
|
|
s_oot_clr0, -- OOT clr0: state 0
|
| 278 |
|
|
s_oot_clr1, -- OOT clr1: state 1
|
| 279 |
|
|
s_oot_clr2 -- OOT clr2: state 2
|
| 280 |
|
|
);
|
| 281 |
|
|
|
| 282 |
|
|
type regs_type is record -- state registers
|
| 283 |
|
|
ibsel : slbit; -- ibus select
|
| 284 |
|
|
state : state_type; -- state
|
| 285 |
|
|
amap : slv5; -- mem mapped address
|
| 286 |
|
|
omux : slv4; -- omux select
|
| 287 |
|
|
dinmsk : slv16; -- mbreq.din masked
|
| 288 |
|
|
dtrm : slv4; -- dt: drive rm controller
|
| 289 |
|
|
dte1 : slv4; -- dt: drive type bit 1
|
| 290 |
|
|
dte0 : slv4; -- dt: drive type bit 0
|
| 291 |
|
|
bae : slv6; -- bae: bus addr extension (in cs1&bae)
|
| 292 |
|
|
cs1sc : slbit; -- cs1: special condition
|
| 293 |
|
|
cs1tre : slbit; -- cs1: transfer error
|
| 294 |
|
|
cs1rdy : slbit; -- cs1: controller ready
|
| 295 |
|
|
cs1ie : slbit; -- cs1: interrupt enable
|
| 296 |
|
|
ffunc : slv5; -- func code (frozen on ext func go)
|
| 297 |
|
|
fxfer : slbit; -- func is xfer
|
| 298 |
|
|
cs2wce : slbit; -- cs2: write check error
|
| 299 |
|
|
cs2ned : slbit; -- cs2: non-existant drive
|
| 300 |
|
|
cs2nem : slbit; -- cs2: non-existant memory
|
| 301 |
|
|
cs2pge : slbit; -- cs2: programming error
|
| 302 |
|
|
cs2mxf : slbit; -- cs2: missed transfer
|
| 303 |
|
|
cs2pat : slbit; -- cs2: parity test
|
| 304 |
|
|
cs2bai : slbit; -- cs2: bus address inhibit
|
| 305 |
|
|
cs2unit2: slbit; -- cs2: unit lsb
|
| 306 |
|
|
cs2unit : slv2; -- unit (ibus view)
|
| 307 |
|
|
funit : slv2; -- unit (frozen on ext func go)
|
| 308 |
|
|
runit : slv2; -- unit (remote view)
|
| 309 |
|
|
eunit : slv2; -- unit (effective)
|
| 310 |
|
|
dsata : slv4; -- ds: attention
|
| 311 |
|
|
dserp : slv4; -- ds: error summary (or of er1+er2)
|
| 312 |
|
|
dspip : slv4; -- ds: positioning in progress
|
| 313 |
|
|
dsmol : slv4; -- ds: medium online (ATTACHED)
|
| 314 |
|
|
dswrl : slv4; -- ds: write locked
|
| 315 |
|
|
dslbt : slv4; -- ds: last block transfered
|
| 316 |
|
|
dsdpr : slv4; -- ds: drive present (ENABLED)
|
| 317 |
|
|
dsvv : slv4; -- ds: volume valid
|
| 318 |
|
|
dsom : slv4; -- ds: offset mode
|
| 319 |
|
|
er1uns : slv4; -- er1: dive unsafe
|
| 320 |
|
|
er1wle : slv4; -- er1: write lock error
|
| 321 |
|
|
er1iae : slv4; -- er1: invalid address error
|
| 322 |
|
|
er1aoe : slv4; -- er1: address overflow error
|
| 323 |
|
|
er1rmr : slv4; -- er1: register modificaton refused
|
| 324 |
|
|
er1ilf : slv4; -- er1: illegal function
|
| 325 |
|
|
cs3wco : slbit; -- cs3: write check odd word
|
| 326 |
|
|
idlyval : slv8; -- int delay value
|
| 327 |
|
|
idlycnt : slv8; -- int delay counter
|
| 328 |
|
|
seekdone: slbit; -- cs3 rem: seek done
|
| 329 |
|
|
poredone: slbit; -- cs3 rem: port rel done
|
| 330 |
|
|
packdone: slbit; -- cs3 rem: pack ack done
|
| 331 |
|
|
seardone: slbit; -- cs3 rem: search done
|
| 332 |
|
|
ned : slbit; -- current drive non-existant
|
| 333 |
|
|
cerm : slbit; -- current eff. drive rm controller
|
| 334 |
|
|
dtyp : slv6; -- current drive type (5:0)
|
| 335 |
|
|
camax : slv10; -- current max cylinder address
|
| 336 |
|
|
tamax : slv5; -- current max track address
|
| 337 |
|
|
samax : slv6; -- current max sector address
|
| 338 |
|
|
uscnt : slv7; -- usec counter
|
| 339 |
|
|
sc : slv6; -- current sector counter
|
| 340 |
|
|
clrmode : slv2; -- clear: mode
|
| 341 |
|
|
clrreg : slv3; -- clear: register counter
|
| 342 |
|
|
ireq : slbit; -- interrupt request flag
|
| 343 |
|
|
end record regs_type;
|
| 344 |
|
|
|
| 345 |
|
|
constant regs_init : regs_type := (
|
| 346 |
|
|
'0', -- ibsel
|
| 347 |
|
|
s_idle, -- state
|
| 348 |
|
|
(others=>'0'), -- amap,
|
| 349 |
|
|
(others=>'0'), -- omux,
|
| 350 |
|
|
(others=>'0'), -- dinmsk,
|
| 351 |
|
|
(others=>'0'), -- dtrm
|
| 352 |
|
|
(others=>'0'), -- dte1
|
| 353 |
|
|
(others=>'0'), -- dte0
|
| 354 |
|
|
(others=>'0'), -- bae,
|
| 355 |
|
|
'0','0','1','0', -- cs1sc,cs1tre,cs1rdy,cs1ie
|
| 356 |
|
|
(others=>'0'), -- ffunc
|
| 357 |
|
|
'0', -- fxfer
|
| 358 |
|
|
'0','0','0','0', -- cs2wce,cs2ned,cs2nem,cs2pge
|
| 359 |
|
|
'0','0','0', -- cs2mxf,cs2pat,cs2bai
|
| 360 |
|
|
'0', -- cs2unit2
|
| 361 |
|
|
(others=>'0'), -- cs2unit
|
| 362 |
|
|
(others=>'0'), -- funit
|
| 363 |
|
|
(others=>'0'), -- runit
|
| 364 |
|
|
(others=>'0'), -- eunit
|
| 365 |
|
|
(others=>'0'), -- dsata
|
| 366 |
|
|
(others=>'0'), -- dserp
|
| 367 |
|
|
(others=>'0'), -- dspip
|
| 368 |
|
|
(others=>'0'), -- dsmol
|
| 369 |
|
|
(others=>'0'), -- dswrl
|
| 370 |
|
|
(others=>'0'), -- dslbt
|
| 371 |
|
|
(others=>'0'), -- dsdpr
|
| 372 |
|
|
(others=>'0'), -- dsvv
|
| 373 |
|
|
(others=>'0'), -- dsom
|
| 374 |
|
|
(others=>'0'), -- er1uns
|
| 375 |
|
|
(others=>'0'), -- er1wle
|
| 376 |
|
|
(others=>'0'), -- er1iae
|
| 377 |
|
|
(others=>'0'), -- er1aoe
|
| 378 |
|
|
(others=>'0'), -- er1rmr
|
| 379 |
|
|
(others=>'0'), -- er1ilf
|
| 380 |
|
|
'0', -- cs3wco
|
| 381 |
|
|
x"0a", -- idlyval (default delay=10)
|
| 382 |
|
|
(others=>'0'), -- idlycnt
|
| 383 |
|
|
'0','0','0','0', -- seekdone,poredone,packdone,seardone
|
| 384 |
|
|
'0','0', -- ned,cerm
|
| 385 |
|
|
(others=>'0'), -- dtyp
|
| 386 |
|
|
(others=>'0'), -- camax
|
| 387 |
|
|
(others=>'0'), -- tamax
|
| 388 |
|
|
(others=>'0'), -- samax
|
| 389 |
|
|
(others=>'0'), -- uscnt
|
| 390 |
|
|
(others=>'0'), -- sc
|
| 391 |
|
|
(others=>'0'), -- clrmode
|
| 392 |
|
|
(others=>'0'), -- clrreg
|
| 393 |
|
|
'0' -- ireq
|
| 394 |
|
|
);
|
| 395 |
|
|
|
| 396 |
|
|
signal R_REGS : regs_type := regs_init;
|
| 397 |
|
|
signal N_REGS : regs_type := regs_init;
|
| 398 |
|
|
|
| 399 |
|
|
signal MEM_1_WE : slbit := '0';
|
| 400 |
|
|
signal MEM_0_WE : slbit := '0';
|
| 401 |
|
|
signal MEM_ADDR : slv5 := (others=>'0');
|
| 402 |
|
|
signal MEM_DIN : slv16 := (others=>'0');
|
| 403 |
|
|
signal MEM_DOUT : slv16 := (others=>'0');
|
| 404 |
|
|
|
| 405 |
|
|
-- the following is unfortunately not accepted by xst:
|
| 406 |
|
|
-- attribute fsm_encoding : string;
|
| 407 |
|
|
-- attribute fsm_encoding of R_REGS.state : signal is "one-hot";
|
| 408 |
|
|
|
| 409 |
|
|
begin
|
| 410 |
|
|
|
| 411 |
|
|
MEM_1 : ram_1swar_gen
|
| 412 |
|
|
generic map (
|
| 413 |
|
|
AWIDTH => 5,
|
| 414 |
|
|
DWIDTH => 8)
|
| 415 |
|
|
port map (
|
| 416 |
|
|
CLK => CLK,
|
| 417 |
|
|
WE => MEM_1_WE,
|
| 418 |
|
|
ADDR => MEM_ADDR,
|
| 419 |
|
|
DI => MEM_DIN(ibf_byte1),
|
| 420 |
|
|
DO => MEM_DOUT(ibf_byte1));
|
| 421 |
|
|
|
| 422 |
|
|
MEM_0 : ram_1swar_gen
|
| 423 |
|
|
generic map (
|
| 424 |
|
|
AWIDTH => 5,
|
| 425 |
|
|
DWIDTH => 8)
|
| 426 |
|
|
port map (
|
| 427 |
|
|
CLK => CLK,
|
| 428 |
|
|
WE => MEM_0_WE,
|
| 429 |
|
|
ADDR => MEM_ADDR,
|
| 430 |
|
|
DI => MEM_DIN(ibf_byte0),
|
| 431 |
|
|
DO => MEM_DOUT(ibf_byte0));
|
| 432 |
|
|
|
| 433 |
|
|
proc_regs: process (CLK)
|
| 434 |
|
|
begin
|
| 435 |
|
|
-- BRESET handled in main fsm, not here !!
|
| 436 |
|
|
if rising_edge(CLK) then
|
| 437 |
|
|
R_REGS <= N_REGS;
|
| 438 |
|
|
end if;
|
| 439 |
|
|
end process proc_regs;
|
| 440 |
|
|
|
| 441 |
|
|
proc_next : process (R_REGS, CE_USEC, BRESET, ITIMER, IB_MREQ, MEM_DOUT,
|
| 442 |
|
|
EI_ACK)
|
| 443 |
|
|
variable r : regs_type := regs_init;
|
| 444 |
|
|
variable n : regs_type := regs_init;
|
| 445 |
|
|
variable ibhold : slbit := '0';
|
| 446 |
|
|
variable idout : slv16 := (others=>'0');
|
| 447 |
|
|
variable ibrem : slbit := '0';
|
| 448 |
|
|
variable ibreq : slbit := '0';
|
| 449 |
|
|
variable ibrd : slbit := '0';
|
| 450 |
|
|
variable ibw0 : slbit := '0';
|
| 451 |
|
|
variable ibw1 : slbit := '0';
|
| 452 |
|
|
variable ibwrem : slbit := '0';
|
| 453 |
|
|
variable ilam : slbit := '0';
|
| 454 |
|
|
variable iei_req : slbit := '0';
|
| 455 |
|
|
|
| 456 |
|
|
variable imem_we0 : slbit := '0';
|
| 457 |
|
|
variable imem_we1 : slbit := '0';
|
| 458 |
|
|
variable imem_addr : slv5 := (others=>'0');
|
| 459 |
|
|
variable imem_din : slv16 := (others=>'0');
|
| 460 |
|
|
|
| 461 |
|
|
variable ieunit : slv2 := (others=>'0');
|
| 462 |
|
|
|
| 463 |
|
|
variable iomux : slv4 := (others=>'0'); -- omux select
|
| 464 |
|
|
variable iamap : slv5 := (others=>'0'); -- mem mapped address
|
| 465 |
|
|
variable imask : slv16 := (others=>'0'); -- implemented bits mask
|
| 466 |
|
|
variable inxr : slbit := '0'; -- non-existent register
|
| 467 |
|
|
variable imbreg : slbit := '0'; -- massbus register
|
| 468 |
|
|
variable inormr : slbit := '0'; -- inhibit rmr protect
|
| 469 |
|
|
|
| 470 |
|
|
variable idte : slv3 := (others=>'0'); -- encoded drive type
|
| 471 |
|
|
variable idtyp : slv6 := (others=>'0'); -- drive type (5:0)
|
| 472 |
|
|
variable icamax : slv10 := (others=>'0'); -- max cylinder address
|
| 473 |
|
|
variable itamax : slv5 := (others=>'0'); -- max track address
|
| 474 |
|
|
variable isamax : slv6 := (others=>'0'); -- max sector address
|
| 475 |
|
|
|
| 476 |
|
|
variable ined : slbit := '0'; -- non-existanrt drive
|
| 477 |
|
|
variable icerm : slbit := '0'; -- effectiv drive is rm
|
| 478 |
|
|
|
| 479 |
|
|
variable iclrreg : slbit := '0'; -- clr enable
|
| 480 |
|
|
|
| 481 |
|
|
variable iscinc : slbit := '0'; -- increment r.sc enable
|
| 482 |
|
|
|
| 483 |
|
|
begin
|
| 484 |
|
|
|
| 485 |
|
|
r := R_REGS;
|
| 486 |
|
|
n := R_REGS;
|
| 487 |
|
|
|
| 488 |
|
|
ibhold := '0';
|
| 489 |
|
|
idout := (others=>'0');
|
| 490 |
|
|
ibrem := IB_MREQ.racc;
|
| 491 |
|
|
ibreq := IB_MREQ.re or IB_MREQ.we;
|
| 492 |
|
|
ibrd := IB_MREQ.re;
|
| 493 |
|
|
ibw0 := IB_MREQ.we and IB_MREQ.be0;
|
| 494 |
|
|
ibw1 := IB_MREQ.we and IB_MREQ.be1;
|
| 495 |
|
|
ibwrem := IB_MREQ.we and ibrem;
|
| 496 |
|
|
ilam := '0';
|
| 497 |
|
|
iei_req := '0';
|
| 498 |
|
|
|
| 499 |
|
|
imem_we0 := '0';
|
| 500 |
|
|
imem_we1 := '0';
|
| 501 |
|
|
imem_addr := r.amap; -- default address (from mapper)
|
| 502 |
|
|
imem_din := r.dinmsk; -- default input (from masker)
|
| 503 |
|
|
|
| 504 |
|
|
ieunit := (others=>'0');
|
| 505 |
|
|
|
| 506 |
|
|
iomux := (others=>'0');
|
| 507 |
|
|
iamap := (others=>'0');
|
| 508 |
|
|
imask := (others=>'1'); -- default: all bits ok
|
| 509 |
|
|
inxr := '0';
|
| 510 |
|
|
imbreg := '0';
|
| 511 |
|
|
inormr := '0';
|
| 512 |
|
|
|
| 513 |
|
|
idte := (others=>'0');
|
| 514 |
|
|
idtyp := (others=>'0');
|
| 515 |
|
|
icamax := (others=>'0');
|
| 516 |
|
|
itamax := (others=>'0');
|
| 517 |
|
|
isamax := (others=>'0');
|
| 518 |
|
|
|
| 519 |
|
|
ined := '0';
|
| 520 |
|
|
icerm := '0';
|
| 521 |
|
|
|
| 522 |
|
|
iclrreg := '0';
|
| 523 |
|
|
|
| 524 |
|
|
iscinc := '0';
|
| 525 |
|
|
|
| 526 |
|
|
-- ibus address decoder, accept only offsets 0 to ibaddr_cs3
|
| 527 |
|
|
n.ibsel := '0';
|
| 528 |
|
|
if IB_MREQ.aval = '1' and
|
| 529 |
|
|
IB_MREQ.addr(12 downto 6) = ibaddr_rhrp(12 downto 6) and
|
| 530 |
|
|
unsigned(ibaddr_rhrp(5 downto 0)) <= unsigned(ibaddr_cs3) then
|
| 531 |
|
|
n.ibsel := '1';
|
| 532 |
|
|
end if;
|
| 533 |
|
|
|
| 534 |
|
|
-- internal state machine
|
| 535 |
|
|
case r.state is
|
| 536 |
|
|
when s_idle => -- idle: handle ibus -----------------
|
| 537 |
|
|
|
| 538 |
|
|
if r.ibsel='1' then -- selected
|
| 539 |
|
|
|
| 540 |
|
|
-- determine effective unit number
|
| 541 |
|
|
if ibrem = '1' then
|
| 542 |
|
|
ieunit := r.runit;
|
| 543 |
|
|
else
|
| 544 |
|
|
ieunit := r.cs2unit;
|
| 545 |
|
|
end if;
|
| 546 |
|
|
n.eunit := ieunit;
|
| 547 |
|
|
|
| 548 |
|
|
-- determine drive properties (always via iunit) FIXME: correct ??
|
| 549 |
|
|
idte(2) := r.dtrm(to_integer(unsigned(r.cs2unit)));
|
| 550 |
|
|
idte(1) := r.dte1(to_integer(unsigned(r.cs2unit)));
|
| 551 |
|
|
idte(0) := r.dte0(to_integer(unsigned(r.cs2unit)));
|
| 552 |
|
|
case idte is
|
| 553 |
|
|
when dte_rp04 => -- RP04
|
| 554 |
|
|
idtyp := rp04_dtyp;
|
| 555 |
|
|
icamax := rp04_camax;
|
| 556 |
|
|
itamax := rp04_tamax;
|
| 557 |
|
|
isamax := rp04_samax;
|
| 558 |
|
|
when dte_rp06 => -- RP06
|
| 559 |
|
|
idtyp := rp06_dtyp;
|
| 560 |
|
|
icamax := rp06_camax;
|
| 561 |
|
|
itamax := rp06_tamax;
|
| 562 |
|
|
isamax := rp06_samax;
|
| 563 |
|
|
when dte_rm03 => -- RM03
|
| 564 |
|
|
idtyp := rm03_dtyp;
|
| 565 |
|
|
icamax := rm03_camax;
|
| 566 |
|
|
itamax := rm03_tamax;
|
| 567 |
|
|
isamax := rm03_samax;
|
| 568 |
|
|
when dte_rm80 => -- RM80
|
| 569 |
|
|
idtyp := rm80_dtyp;
|
| 570 |
|
|
icamax := rm80_camax;
|
| 571 |
|
|
itamax := rm80_tamax;
|
| 572 |
|
|
isamax := rm80_samax;
|
| 573 |
|
|
when dte_rm05 => -- RM05
|
| 574 |
|
|
idtyp := rm05_dtyp;
|
| 575 |
|
|
icamax := rm05_camax;
|
| 576 |
|
|
itamax := rm05_tamax;
|
| 577 |
|
|
isamax := rm05_samax;
|
| 578 |
|
|
when dte_rp07 => -- RP07
|
| 579 |
|
|
idtyp := rp07_dtyp;
|
| 580 |
|
|
icamax := rp07_camax;
|
| 581 |
|
|
itamax := rp07_tamax;
|
| 582 |
|
|
isamax := rp07_samax;
|
| 583 |
|
|
when others =>
|
| 584 |
|
|
idtyp := (others=>'0');
|
| 585 |
|
|
icamax := (others=>'0');
|
| 586 |
|
|
itamax := (others=>'0');
|
| 587 |
|
|
isamax := (others=>'0');
|
| 588 |
|
|
end case; -- case idte
|
| 589 |
|
|
n.dtyp := idtyp;
|
| 590 |
|
|
n.camax := icamax;
|
| 591 |
|
|
n.tamax := itamax;
|
| 592 |
|
|
n.samax := isamax;
|
| 593 |
|
|
|
| 594 |
|
|
-- consider drive non-existant if not 'DPR' or unit>=4 selected
|
| 595 |
|
|
if r.dsdpr(to_integer(unsigned(r.cs2unit))) = '0' or
|
| 596 |
|
|
r.cs2unit2 = '1' then
|
| 597 |
|
|
ined := '1';
|
| 598 |
|
|
end if;
|
| 599 |
|
|
n.ned := ined;
|
| 600 |
|
|
|
| 601 |
|
|
icerm := r.dtrm(to_integer(unsigned(ieunit)));
|
| 602 |
|
|
n.cerm := icerm;
|
| 603 |
|
|
|
| 604 |
|
|
-- setup mapper
|
| 605 |
|
|
case IB_MREQ.addr(5 downto 1) is
|
| 606 |
|
|
|
| 607 |
|
|
when ibaddr_cs1 => -- RxCS1 control reg 1
|
| 608 |
|
|
-- cs1 not flagged mbreg !! ned handling done explicitely
|
| 609 |
|
|
iamap := ieunit & amapc_cs1;
|
| 610 |
|
|
iomux := omux_cs1;
|
| 611 |
|
|
|
| 612 |
|
|
when ibaddr_wc => -- RxWC word count
|
| 613 |
|
|
iamap := amapr_wc & amapc_ext;
|
| 614 |
|
|
iomux := omux_mem;
|
| 615 |
|
|
|
| 616 |
|
|
when ibaddr_ba => -- RxBA bus address
|
| 617 |
|
|
imask := "1111111111111110"; -- lsb ignored
|
| 618 |
|
|
iamap := amapr_ba & amapc_ext;
|
| 619 |
|
|
iomux := omux_mem;
|
| 620 |
|
|
|
| 621 |
|
|
when ibaddr_da => -- RxDA disk address
|
| 622 |
|
|
imask := "0001111100111111"; -- 000t tttt 00ss ssss
|
| 623 |
|
|
iamap := ieunit & amapc_da;
|
| 624 |
|
|
iomux := omux_mem;
|
| 625 |
|
|
imbreg := '1'; -- mb 5
|
| 626 |
|
|
|
| 627 |
|
|
when ibaddr_cs2 => -- RxCS2 control reg 2
|
| 628 |
|
|
iomux := omux_cs2;
|
| 629 |
|
|
|
| 630 |
|
|
when ibaddr_ds => -- RxDS drive status
|
| 631 |
|
|
iomux := omux_ds;
|
| 632 |
|
|
imbreg := '1'; -- mb 1
|
| 633 |
|
|
|
| 634 |
|
|
when ibaddr_er1 => -- RxER1 error status 1
|
| 635 |
|
|
iomux := omux_er1;
|
| 636 |
|
|
imbreg := '1'; -- mb 2
|
| 637 |
|
|
|
| 638 |
|
|
when ibaddr_as => -- RxAS attention summary
|
| 639 |
|
|
iomux := omux_as;
|
| 640 |
|
|
imbreg := '1'; -- mb 4
|
| 641 |
|
|
inormr := '1'; -- AS writes allowed when RDY=0
|
| 642 |
|
|
|
| 643 |
|
|
when ibaddr_la => -- RxLA look ahead
|
| 644 |
|
|
iomux := omux_la;
|
| 645 |
|
|
imbreg := '1'; -- mb 7
|
| 646 |
|
|
|
| 647 |
|
|
when ibaddr_db => -- RxDB data buffer
|
| 648 |
|
|
iamap := amapr_db & amapc_ext;
|
| 649 |
|
|
iomux := omux_mem;
|
| 650 |
|
|
|
| 651 |
|
|
when ibaddr_mr1 => -- RxMR1 maintenance reg 1
|
| 652 |
|
|
iamap := ieunit & amapc_mr1;
|
| 653 |
|
|
iomux := omux_mem;
|
| 654 |
|
|
imbreg := '1'; -- mb 3
|
| 655 |
|
|
inormr := '1'; -- MR1 writes allowed when RDY=0
|
| 656 |
|
|
|
| 657 |
|
|
when ibaddr_dt => -- RxDT drive type
|
| 658 |
|
|
iomux := omux_dt;
|
| 659 |
|
|
imbreg := '1'; -- mb 6
|
| 660 |
|
|
|
| 661 |
|
|
when ibaddr_sn => -- RxSN serial number
|
| 662 |
|
|
iomux := omux_sn;
|
| 663 |
|
|
imbreg := '1'; -- mb 10
|
| 664 |
|
|
|
| 665 |
|
|
when ibaddr_of => -- RxOF offset reg
|
| 666 |
|
|
imask := "0001110011111111"; -- 000f eh00 d??? ????
|
| 667 |
|
|
iamap := ieunit & amapc_of;
|
| 668 |
|
|
iomux := omux_mem;
|
| 669 |
|
|
imbreg := '1'; -- mb 11
|
| 670 |
|
|
|
| 671 |
|
|
when ibaddr_dc => -- RxDC desired cylinder
|
| 672 |
|
|
imask := "0000001111111111"; -- 0000 00cc cccc cccc
|
| 673 |
|
|
iamap := ieunit & amapc_dc;
|
| 674 |
|
|
iomux := omux_mem;
|
| 675 |
|
|
imbreg := '1'; -- mb 12
|
| 676 |
|
|
|
| 677 |
|
|
when ibaddr_m13 =>
|
| 678 |
|
|
if icerm = '1' then
|
| 679 |
|
|
iamap := ieunit & amapc_hr; -- RMHR holding reg
|
| 680 |
|
|
else
|
| 681 |
|
|
iamap := ieunit & amapc_dc; -- RPDC current cylinder
|
| 682 |
|
|
end if;
|
| 683 |
|
|
iomux := omux_mem;
|
| 684 |
|
|
imbreg := '1'; -- mb 13
|
| 685 |
|
|
|
| 686 |
|
|
when ibaddr_m14 =>
|
| 687 |
|
|
if icerm = '1' then
|
| 688 |
|
|
iamap := ieunit & amapc_mr2; -- RMMR2 maintenance reg 2
|
| 689 |
|
|
iomux := omux_mem;
|
| 690 |
|
|
else
|
| 691 |
|
|
iomux := omux_zero; -- RPER2 error status 2
|
| 692 |
|
|
end if;
|
| 693 |
|
|
imbreg := '1'; -- mb 14
|
| 694 |
|
|
|
| 695 |
|
|
when ibaddr_m15 => -- RxER3 error status 3/2
|
| 696 |
|
|
iomux := omux_zero;
|
| 697 |
|
|
imbreg := '1'; -- mb 15
|
| 698 |
|
|
|
| 699 |
|
|
when ibaddr_ec1 => -- RxEC1 ecc status 1
|
| 700 |
|
|
iomux := omux_zero;
|
| 701 |
|
|
imbreg := '1'; -- mb 16
|
| 702 |
|
|
|
| 703 |
|
|
when ibaddr_ec2 => -- RxEC2 ecc status 2
|
| 704 |
|
|
iomux := omux_zero;
|
| 705 |
|
|
imbreg := '1'; -- mb 17
|
| 706 |
|
|
|
| 707 |
|
|
when ibaddr_bae => -- RxBAE bus addr extension
|
| 708 |
|
|
iomux := omux_bae;
|
| 709 |
|
|
|
| 710 |
|
|
when ibaddr_cs3 => -- RxCS3 control reg 3
|
| 711 |
|
|
iomux := omux_cs3;
|
| 712 |
|
|
|
| 713 |
|
|
when others => -- unknown register
|
| 714 |
|
|
inxr := '1';
|
| 715 |
|
|
|
| 716 |
|
|
end case; -- case IB_MREQ.addr
|
| 717 |
|
|
n.amap := iamap;
|
| 718 |
|
|
n.omux := iomux;
|
| 719 |
|
|
n.dinmsk := imask and IB_MREQ.din;
|
| 720 |
|
|
|
| 721 |
|
|
if IB_MREQ.we = '1' then -- write request
|
| 722 |
|
|
ibhold := '1'; -- assume follow-up state taken
|
| 723 |
|
|
case IB_MREQ.addr(5 downto 1) is
|
| 724 |
|
|
|
| 725 |
|
|
when ibaddr_cs1 => n.state := s_wcs1; -- RxCS1
|
| 726 |
|
|
when ibaddr_wc => n.state := s_wmembe; -- RxWC
|
| 727 |
|
|
when ibaddr_ba => n.state := s_wmembe; -- RxBA
|
| 728 |
|
|
when ibaddr_da => n.state := s_wmem; -- RxDA
|
| 729 |
|
|
when ibaddr_cs2 => n.state := s_wcs2; -- RxCS2
|
| 730 |
|
|
when ibaddr_ds => n.state := s_wds; -- RxDS (read-only)
|
| 731 |
|
|
when ibaddr_er1 => n.state := s_wer1; -- RxER1 (read-only)
|
| 732 |
|
|
when ibaddr_as => n.state := s_was; -- RxAS
|
| 733 |
|
|
when ibaddr_la => n.state := s_whr; -- RxLA (read-only)
|
| 734 |
|
|
when ibaddr_db => n.state := s_wmembe; -- RxDB
|
| 735 |
|
|
when ibaddr_mr1 => n.state := s_wmem; -- RxMR1
|
| 736 |
|
|
when ibaddr_dt => n.state := s_wdt; -- RxDT (read-only)
|
| 737 |
|
|
when ibaddr_sn => n.state := s_whr; -- RxSN (read-only)
|
| 738 |
|
|
when ibaddr_of => n.state := s_wmem; -- RxOF
|
| 739 |
|
|
when ibaddr_dc => n.state := s_wmem; -- RxDC
|
| 740 |
|
|
when ibaddr_m13 => n.state := s_whr; -- RPCC|RMHR (fits both)
|
| 741 |
|
|
when ibaddr_m14 =>
|
| 742 |
|
|
if icerm = '1' then
|
| 743 |
|
|
n.state := s_wmem; -- RMMR2
|
| 744 |
|
|
else
|
| 745 |
|
|
n.state := s_whr; -- RPER2
|
| 746 |
|
|
end if;
|
| 747 |
|
|
when ibaddr_m15 => n.state := s_whr; -- RPER3|RMER2 (fits both)
|
| 748 |
|
|
when ibaddr_ec1 => n.state := s_whr; -- RxEC1
|
| 749 |
|
|
when ibaddr_ec2 => n.state := s_whr; -- RxEC2
|
| 750 |
|
|
when ibaddr_bae => n.state := s_wbae; -- RxBAE
|
| 751 |
|
|
when ibaddr_cs3 => n.state := s_wcs3; -- RxCS3
|
| 752 |
|
|
|
| 753 |
|
|
when others => null; -- doesn't happen, ibsel only for
|
| 754 |
|
|
-- subrange up to cs3, and all
|
| 755 |
|
|
-- 22 regs are decoded above
|
| 756 |
|
|
|
| 757 |
|
|
end case; -- case IB_MREQ.addr
|
| 758 |
|
|
|
| 759 |
|
|
-- some general error catchers
|
| 760 |
|
|
if ibrem = '0' and imbreg='1' then -- local massbus write
|
| 761 |
|
|
-- for cs1: imbreg=0 !!
|
| 762 |
|
|
if ined = '1' then
|
| 763 |
|
|
n.cs2ned := '1';
|
| 764 |
|
|
elsif inormr='0' and r.cs1rdy='0' then -- rmr prot reg and RDY=0
|
| 765 |
|
|
n.state := s_setrmr;
|
| 766 |
|
|
end if;
|
| 767 |
|
|
end if;
|
| 768 |
|
|
|
| 769 |
|
|
elsif IB_MREQ.re = '1' then -- read request
|
| 770 |
|
|
if inxr = '1' then -- unknown register
|
| 771 |
|
|
ibreq := '0'; -- suppress ack & hold --> ibus err
|
| 772 |
|
|
else
|
| 773 |
|
|
if ibrem='0' and imbreg='1' and ined='1' then
|
| 774 |
|
|
n.cs2ned := '1'; -- signal error
|
| 775 |
|
|
else
|
| 776 |
|
|
ibhold := '1';
|
| 777 |
|
|
n.state := s_read;
|
| 778 |
|
|
end if;
|
| 779 |
|
|
end if;
|
| 780 |
|
|
|
| 781 |
|
|
end if; -- if IB_MREQ.we .. elsif IB_MREQ.re
|
| 782 |
|
|
|
| 783 |
|
|
-- BRESET and ITIMER can be handled in the 'else' because both can
|
| 784 |
|
|
-- never come during an ibus transaction. Done here to keep logic
|
| 785 |
|
|
-- path in the 'if' short.
|
| 786 |
|
|
else -- if r.ibsel='1'
|
| 787 |
|
|
if BRESET = '1' then
|
| 788 |
|
|
n.eunit := "00";
|
| 789 |
|
|
n.clrmode := clrmode_breset;
|
| 790 |
|
|
n.state := s_oot_clr0; -- OOT state, no hold!
|
| 791 |
|
|
end if;
|
| 792 |
|
|
|
| 793 |
|
|
if unsigned(r.idlycnt) = 0 then -- interrupt delay expired
|
| 794 |
|
|
n.dsata := r.dsata or r.dspip; -- convert pip's to ata's
|
| 795 |
|
|
n.dspip := (others=>'0'); -- and mark them done
|
| 796 |
|
|
else
|
| 797 |
|
|
if ITIMER = '1' then -- not expired and ITIMER
|
| 798 |
|
|
n.idlycnt := slv(unsigned(r.idlycnt) - 1); -- count down
|
| 799 |
|
|
end if;
|
| 800 |
|
|
end if;
|
| 801 |
|
|
|
| 802 |
|
|
end if; -- if r.ibsel='1'
|
| 803 |
|
|
|
| 804 |
|
|
-- s_idle goes up to here !!
|
| 805 |
|
|
|
| 806 |
|
|
when s_wcs1 => -- wcs1: write cs1 -------------------
|
| 807 |
|
|
n.state := s_idle; -- in general return to s_idle
|
| 808 |
|
|
imem_addr := r.amap; -- use mapped address
|
| 809 |
|
|
imem_din := r.dinmsk; -- use masked input
|
| 810 |
|
|
|
| 811 |
|
|
if ibrem = '0' then -- loc write access
|
| 812 |
|
|
|
| 813 |
|
|
if IB_MREQ.be1 = '1' then
|
| 814 |
|
|
if IB_MREQ.din(cs1_ibf_tre) = '1' then -- TRE=1 -> clear errors
|
| 815 |
|
|
n.cs2wce := '0';
|
| 816 |
|
|
n.cs2ned := '0';
|
| 817 |
|
|
n.cs2nem := '0';
|
| 818 |
|
|
n.cs2pge := '0';
|
| 819 |
|
|
n.cs2mxf := '0';
|
| 820 |
|
|
end if;
|
| 821 |
|
|
if r.cs1rdy = '1' then -- only if RDY
|
| 822 |
|
|
n.bae(1 downto 0) := IB_MREQ.din(cs1_ibf_bae); -- update bae
|
| 823 |
|
|
end if;
|
| 824 |
|
|
end if; -- IB_MREQ.be1 = '1'
|
| 825 |
|
|
|
| 826 |
|
|
if IB_MREQ.be0 = '1' then
|
| 827 |
|
|
n.cs1ie := IB_MREQ.din(cs1_ibf_ie);
|
| 828 |
|
|
if IB_MREQ.din(cs1_ibf_ie) = '1' and -- if IE and RDY both 1
|
| 829 |
|
|
IB_MREQ.din(cs1_ibf_rdy) = '1'then
|
| 830 |
|
|
n.ireq := '1'; -- issue software interrupt
|
| 831 |
|
|
end if;
|
| 832 |
|
|
|
| 833 |
|
|
if r.cs1rdy = '1' then -- controller ready
|
| 834 |
|
|
if r.ned = '0' and -- drive on
|
| 835 |
|
|
IB_MREQ.din(cs1_ibf_go) = '1' then -- GO bit set
|
| 836 |
|
|
ibhold := '1';
|
| 837 |
|
|
n.state := s_funcgo;
|
| 838 |
|
|
end if;
|
| 839 |
|
|
else -- cntl not rdy
|
| 840 |
|
|
n.cs2pge := '1'; -- issue program error
|
| 841 |
|
|
end if;
|
| 842 |
|
|
|
| 843 |
|
|
imem_we0 := IB_MREQ.be0; -- remember func field per unit
|
| 844 |
|
|
if r.ned = '1' then -- loc access and drive off
|
| 845 |
|
|
n.cs2ned := '1'; -- signal error
|
| 846 |
|
|
end if;
|
| 847 |
|
|
|
| 848 |
|
|
end if; -- IB_MREQ.be0 = '1'
|
| 849 |
|
|
|
| 850 |
|
|
else -- rem write access. GO not checked
|
| 851 |
|
|
-- always treated as remote function
|
| 852 |
|
|
case IB_MREQ.din(cs1_ibf_func) is
|
| 853 |
|
|
|
| 854 |
|
|
when rfunc_wunit => -- rfunc: wunit ---------------
|
| 855 |
|
|
n.runit := IB_MREQ.din(cs1_ibf_runit);
|
| 856 |
|
|
|
| 857 |
|
|
when rfunc_cunit => -- rfunc: cunit ---------------
|
| 858 |
|
|
n.runit := r.funit; -- use unit from last ext func go
|
| 859 |
|
|
|
| 860 |
|
|
when rfunc_done => -- rfunc: done ----------------
|
| 861 |
|
|
n.cs1rdy := '1';
|
| 862 |
|
|
if IB_MREQ.din(cs1_ibf_rata) = '0' then
|
| 863 |
|
|
n.ireq := r.cs1ie; -- yes, ireq is set from ie !!
|
| 864 |
|
|
else
|
| 865 |
|
|
n.dsata(to_integer(unsigned(r.funit))) := '1';
|
| 866 |
|
|
end if;
|
| 867 |
|
|
|
| 868 |
|
|
when rfunc_widly => -- rfunc: widly ---------------
|
| 869 |
|
|
n.idlyval := IB_MREQ.din(cs1_ibf_ridly);
|
| 870 |
|
|
|
| 871 |
|
|
when others => null;
|
| 872 |
|
|
|
| 873 |
|
|
end case;
|
| 874 |
|
|
end if;
|
| 875 |
|
|
|
| 876 |
|
|
when s_wcs2 => -- wcs2: write cs2 -------------------
|
| 877 |
|
|
n.state := s_idle; -- in general return to s_idle
|
| 878 |
|
|
if ibrem = '1' then -- rem access
|
| 879 |
|
|
n.cs3wco := IB_MREQ.din(cs2_ibf_rwco); -- cs3.wco rem set via cs2 !!
|
| 880 |
|
|
n.cs2wce := IB_MREQ.din(cs2_ibf_wce);
|
| 881 |
|
|
n.cs2nem := IB_MREQ.din(cs2_ibf_nem);
|
| 882 |
|
|
n.cs2mxf := IB_MREQ.din(cs2_ibf_mxf); -- FIXME: really used ???
|
| 883 |
|
|
else
|
| 884 |
|
|
if IB_MREQ.be0 = '1' then
|
| 885 |
|
|
n.cs2pat := IB_MREQ.din(cs2_ibf_pat);
|
| 886 |
|
|
n.cs2bai := IB_MREQ.din(cs2_ibf_bai);
|
| 887 |
|
|
n.cs2unit2 := IB_MREQ.din(cs2_ibf_unit2);
|
| 888 |
|
|
n.cs2unit := IB_MREQ.din(cs2_ibf_unit);
|
| 889 |
|
|
if IB_MREQ.din(cs2_ibf_clr) = '1' then
|
| 890 |
|
|
n.eunit := "00";
|
| 891 |
|
|
n.clrmode := clrmode_cs2clr;
|
| 892 |
|
|
n.state := s_oot_clr0; -- OOT state, no hold!
|
| 893 |
|
|
end if;
|
| 894 |
|
|
end if;
|
| 895 |
|
|
end if;
|
| 896 |
|
|
|
| 897 |
|
|
when s_wcs3 => -- wcs3: write cs3 -------------------
|
| 898 |
|
|
n.state := s_idle; -- in general return to s_idle
|
| 899 |
|
|
if ibrem = '0' then -- loc access
|
| 900 |
|
|
if IB_MREQ.be0 = '1' then
|
| 901 |
|
|
n.cs1ie := IB_MREQ.din(cs3_ibf_ie);
|
| 902 |
|
|
end if;
|
| 903 |
|
|
end if;
|
| 904 |
|
|
|
| 905 |
|
|
when s_wer1 => -- wer1: write er1 (rem only) --------
|
| 906 |
|
|
n.state := s_idle; -- in general return to s_idle
|
| 907 |
|
|
if ibrem = '1' then -- rem access
|
| 908 |
|
|
if IB_MREQ.din(er1_ibf_uns) = '1' then
|
| 909 |
|
|
n.er1uns(to_integer(unsigned(r.eunit))) := '1';
|
| 910 |
|
|
end if;
|
| 911 |
|
|
if IB_MREQ.din(er1_ibf_wle) = '1' then
|
| 912 |
|
|
n.er1wle(to_integer(unsigned(r.eunit))) := '1';
|
| 913 |
|
|
end if;
|
| 914 |
|
|
if IB_MREQ.din(er1_ibf_iae) = '1' then
|
| 915 |
|
|
n.er1iae(to_integer(unsigned(r.eunit))) := '1';
|
| 916 |
|
|
end if;
|
| 917 |
|
|
if IB_MREQ.din(er1_ibf_aoe) = '1' then
|
| 918 |
|
|
n.er1aoe(to_integer(unsigned(r.eunit))) := '1';
|
| 919 |
|
|
end if;
|
| 920 |
|
|
if IB_MREQ.din(er1_ibf_ilf) = '1' then
|
| 921 |
|
|
n.er1ilf(to_integer(unsigned(r.eunit))) := '1';
|
| 922 |
|
|
end if;
|
| 923 |
|
|
else -- loc access
|
| 924 |
|
|
ibhold := '1';
|
| 925 |
|
|
n.state := s_whr;
|
| 926 |
|
|
end if;
|
| 927 |
|
|
|
| 928 |
|
|
when s_was => -- was: write as ---------------------
|
| 929 |
|
|
n.state := s_idle; -- in general return to s_idle
|
| 930 |
|
|
-- clear the attention bits marked as '1' in data word (loc and rem !!)
|
| 931 |
|
|
n.dsata := r.dsata and not IB_MREQ.din(r.dsata'range);
|
| 932 |
|
|
if ibrem = '0' then -- loc access
|
| 933 |
|
|
ibhold := '1';
|
| 934 |
|
|
n.state := s_whr;
|
| 935 |
|
|
end if;
|
| 936 |
|
|
|
| 937 |
|
|
when s_wdt => -- wdt: write dt ---------------------
|
| 938 |
|
|
n.state := s_idle; -- in general return to s_idle
|
| 939 |
|
|
if ibrem = '1' then -- rem access
|
| 940 |
|
|
n.dtrm(to_integer(unsigned(r.runit))) := IB_MREQ.din(dt_ibf_rm);
|
| 941 |
|
|
n.dte1(to_integer(unsigned(r.runit))) := IB_MREQ.din(dt_ibf_e1);
|
| 942 |
|
|
n.dte0(to_integer(unsigned(r.runit))) := IB_MREQ.din(dt_ibf_e0);
|
| 943 |
|
|
n.state := s_idle;
|
| 944 |
|
|
else -- loc access
|
| 945 |
|
|
ibhold := '1';
|
| 946 |
|
|
n.state := s_whr;
|
| 947 |
|
|
end if;
|
| 948 |
|
|
|
| 949 |
|
|
when s_wds => -- wdt: write ds ---------------------
|
| 950 |
|
|
n.state := s_idle; -- in general return to s_idle
|
| 951 |
|
|
if ibrem = '1' then -- rem access
|
| 952 |
|
|
n.dsmol(to_integer(unsigned(r.runit))) := IB_MREQ.din(ds_ibf_mol);
|
| 953 |
|
|
n.dswrl(to_integer(unsigned(r.runit))) := IB_MREQ.din(ds_ibf_wrl);
|
| 954 |
|
|
n.dslbt(to_integer(unsigned(r.runit))) := IB_MREQ.din(ds_ibf_lbt);
|
| 955 |
|
|
n.dsdpr(to_integer(unsigned(r.runit))) := IB_MREQ.din(ds_ibf_dpr);
|
| 956 |
|
|
if IB_MREQ.din(ds_ibf_ata) = '1' then -- set ata on demand
|
| 957 |
|
|
n.dsata(to_integer(unsigned(r.runit))) := '1';
|
| 958 |
|
|
end if;
|
| 959 |
|
|
if IB_MREQ.din(ds_ibf_vv) = '1' then -- clr vv on demand
|
| 960 |
|
|
n.dsvv(to_integer(unsigned(r.runit))) := '0';
|
| 961 |
|
|
end if;
|
| 962 |
|
|
if IB_MREQ.din(ds_ibf_erp) = '1' then -- clr er1 on demand
|
| 963 |
|
|
n.er1uns(to_integer(unsigned(r.eunit))) := '0'; -- clr all er1
|
| 964 |
|
|
n.er1wle(to_integer(unsigned(r.eunit))) := '0'; -- "
|
| 965 |
|
|
n.er1iae(to_integer(unsigned(r.eunit))) := '0'; -- "
|
| 966 |
|
|
n.er1aoe(to_integer(unsigned(r.eunit))) := '0'; -- "
|
| 967 |
|
|
n.er1rmr(to_integer(unsigned(r.eunit))) := '0'; -- "
|
| 968 |
|
|
n.er1ilf(to_integer(unsigned(r.eunit))) := '0'; -- "
|
| 969 |
|
|
end if;
|
| 970 |
|
|
n.state := s_idle;
|
| 971 |
|
|
else -- loc access
|
| 972 |
|
|
ibhold := '1'; -- read-only reg, thus noop
|
| 973 |
|
|
n.state := s_whr;
|
| 974 |
|
|
end if;
|
| 975 |
|
|
|
| 976 |
|
|
when s_wbae => -- wbae: write bae -------------------
|
| 977 |
|
|
n.state := s_idle; -- in general return to s_idle
|
| 978 |
|
|
if IB_MREQ.be0 = '1' then
|
| 979 |
|
|
n.bae := IB_MREQ.din(bae_ibf_bae);
|
| 980 |
|
|
end if;
|
| 981 |
|
|
|
| 982 |
|
|
when s_wmem => -- wmem: write mem (DA,MR1,OF,DC,MR2)-
|
| 983 |
|
|
-- this state only handles massbus registers
|
| 984 |
|
|
n.state := s_idle; -- in general return to s_idle
|
| 985 |
|
|
imem_addr := r.amap; -- use mapped address
|
| 986 |
|
|
imem_din := r.dinmsk; -- use masked input
|
| 987 |
|
|
|
| 988 |
|
|
if ibrem = '0' then -- loc access
|
| 989 |
|
|
imem_we0 := '1'; -- write memory
|
| 990 |
|
|
imem_we1 := '1';
|
| 991 |
|
|
ibhold := '1';
|
| 992 |
|
|
n.state := s_whr;
|
| 993 |
|
|
else -- rem access
|
| 994 |
|
|
imem_we0 := '1'; -- write memory
|
| 995 |
|
|
imem_we1 := '1';
|
| 996 |
|
|
end if;
|
| 997 |
|
|
|
| 998 |
|
|
when s_wmembe => -- wmem: write mem with be (WC,BA,DB)-
|
| 999 |
|
|
-- this state only handles controller registers --> no ned checking
|
| 1000 |
|
|
n.state := s_idle; -- in general return to s_idle
|
| 1001 |
|
|
imem_we0 := IB_MREQ.be0;
|
| 1002 |
|
|
imem_we1 := IB_MREQ.be1;
|
| 1003 |
|
|
imem_addr := r.amap;
|
| 1004 |
|
|
imem_din := r.dinmsk;
|
| 1005 |
|
|
|
| 1006 |
|
|
when s_whr => -- whr: write hr ---------------------
|
| 1007 |
|
|
n.state := s_idle; -- in general return to s_idle
|
| 1008 |
|
|
imem_addr := r.cs2unit & amapc_hr; -- mem address of holding reg
|
| 1009 |
|
|
imem_din := not IB_MREQ.din;
|
| 1010 |
|
|
if ibrem = '0' then -- loc access
|
| 1011 |
|
|
imem_we0 := '1'; -- keep state
|
| 1012 |
|
|
imem_we1 := '1';
|
| 1013 |
|
|
end if;
|
| 1014 |
|
|
|
| 1015 |
|
|
when s_funcgo => -- funcgo: handle function go --------
|
| 1016 |
|
|
n.state := s_idle; -- in general return to s_idle
|
| 1017 |
|
|
n.dsata(to_integer(unsigned(r.cs2unit))) := '0';
|
| 1018 |
|
|
|
| 1019 |
|
|
case IB_MREQ.din(cs1_ibf_func) is
|
| 1020 |
|
|
when func_noop => -- func: noop --------------
|
| 1021 |
|
|
null; -- nothing done...
|
| 1022 |
|
|
|
| 1023 |
|
|
when func_pore => -- func: port release-------
|
| 1024 |
|
|
n.poredone := '1'; -- take note in done flag
|
| 1025 |
|
|
|
| 1026 |
|
|
when func_unl => -- func: unload ------------
|
| 1027 |
|
|
-- only for RP, simply clears MOL
|
| 1028 |
|
|
if r.dtrm(to_integer(unsigned(r.cs2unit))) = '0' then
|
| 1029 |
|
|
n.dsmol(to_integer(unsigned(r.cs2unit))) := '0';
|
| 1030 |
|
|
n.dswrl(to_integer(unsigned(r.cs2unit))) := '0';
|
| 1031 |
|
|
n.dsvv(to_integer(unsigned(r.cs2unit))) := '0';
|
| 1032 |
|
|
n.dsom(to_integer(unsigned(r.cs2unit))) := '0';
|
| 1033 |
|
|
else
|
| 1034 |
|
|
n.er1ilf(to_integer(unsigned(r.cs2unit))) := '1';
|
| 1035 |
|
|
end if;
|
| 1036 |
|
|
n.dsata(to_integer(unsigned(r.cs2unit))) := '1';
|
| 1037 |
|
|
|
| 1038 |
|
|
when func_dclr => -- func: drive clear -------
|
| 1039 |
|
|
n.eunit := r.cs2unit; -- for follow-up states
|
| 1040 |
|
|
n.clrmode := clrmode_fdclr;
|
| 1041 |
|
|
n.state := s_oot_clr0; -- OOT state, no hold!
|
| 1042 |
|
|
|
| 1043 |
|
|
when func_offs | -- func: offset ------------
|
| 1044 |
|
|
func_retc => -- func: return to center --
|
| 1045 |
|
|
|
| 1046 |
|
|
-- currently always immediate completion, so ata set here
|
| 1047 |
|
|
n.dsata(to_integer(unsigned(r.cs2unit))) := '1';
|
| 1048 |
|
|
|
| 1049 |
|
|
if r.dsmol(to_integer(unsigned(r.cs2unit))) = '0' then
|
| 1050 |
|
|
n.er1uns(to_integer(unsigned(r.cs2unit))) := '1';
|
| 1051 |
|
|
else
|
| 1052 |
|
|
if IB_MREQ.din(cs1_ibf_func) = func_offs then
|
| 1053 |
|
|
n.dsom(to_integer(unsigned(r.cs2unit))) := '1';
|
| 1054 |
|
|
else
|
| 1055 |
|
|
n.dsom(to_integer(unsigned(r.cs2unit))) := '0';
|
| 1056 |
|
|
end if;
|
| 1057 |
|
|
end if;
|
| 1058 |
|
|
|
| 1059 |
|
|
when func_pres => -- func: readin preset -----
|
| 1060 |
|
|
n.dsvv(to_integer(unsigned(r.cs2unit))) := '1';
|
| 1061 |
|
|
n.eunit := r.cs2unit; -- for follow-up states
|
| 1062 |
|
|
n.clrmode := clrmode_fpres;
|
| 1063 |
|
|
n.state := s_oot_clr0; -- OOT state, no hold!
|
| 1064 |
|
|
|
| 1065 |
|
|
when func_pack => -- func: pack acknowledge --
|
| 1066 |
|
|
n.dsvv(to_integer(unsigned(r.cs2unit))) := '1';
|
| 1067 |
|
|
n.packdone := '1'; -- take note in done flag
|
| 1068 |
|
|
|
| 1069 |
|
|
-- seek like and data transfer functions
|
| 1070 |
|
|
when func_seek | -- func: seek --------------
|
| 1071 |
|
|
func_recal | -- func: recalibrate -------
|
| 1072 |
|
|
func_sear | -- func: search ------------
|
| 1073 |
|
|
func_wcd | -- func: write check data --
|
| 1074 |
|
|
func_wchd | -- func: write check h&d ---
|
| 1075 |
|
|
func_write | -- func: write ------------
|
| 1076 |
|
|
func_whd | -- func: write header&data -
|
| 1077 |
|
|
func_read | -- func: read --------------
|
| 1078 |
|
|
func_rhd => -- func: read header&data --
|
| 1079 |
|
|
|
| 1080 |
|
|
if IB_MREQ.din(cs1_ibf_func) = func_seek then
|
| 1081 |
|
|
n.seekdone := '1'; -- take note in done flag
|
| 1082 |
|
|
end if;
|
| 1083 |
|
|
if IB_MREQ.din(cs1_ibf_func) = func_sear then
|
| 1084 |
|
|
n.seardone := '1'; -- take note in done flag
|
| 1085 |
|
|
end if;
|
| 1086 |
|
|
|
| 1087 |
|
|
-- check for transfer functions
|
| 1088 |
|
|
n.fxfer := '0';
|
| 1089 |
|
|
if unsigned(IB_MREQ.din(cs1_ibf_func)) >= unsigned(func_wcd) then
|
| 1090 |
|
|
n.fxfer := '1';
|
| 1091 |
|
|
-- in case of write, check for write lock
|
| 1092 |
|
|
if IB_MREQ.din(cs1_ibf_func) = func_write or
|
| 1093 |
|
|
IB_MREQ.din(cs1_ibf_func) = func_whd then
|
| 1094 |
|
|
if r.dswrl(to_integer(unsigned(r.cs2unit))) = '1' then
|
| 1095 |
|
|
n.er1wle(to_integer(unsigned(r.cs2unit))) := '1';
|
| 1096 |
|
|
end if;
|
| 1097 |
|
|
end if;
|
| 1098 |
|
|
end if;
|
| 1099 |
|
|
|
| 1100 |
|
|
if r.dsmol(to_integer(unsigned(r.cs2unit))) = '0' then
|
| 1101 |
|
|
n.er1uns(to_integer(unsigned(r.cs2unit))) := '1';
|
| 1102 |
|
|
n.dsata(to_integer(unsigned(r.cs2unit))) := '1';
|
| 1103 |
|
|
else
|
| 1104 |
|
|
ibhold := '1';
|
| 1105 |
|
|
n.state := s_chkdc;
|
| 1106 |
|
|
end if;
|
| 1107 |
|
|
|
| 1108 |
|
|
-- illegal function codes
|
| 1109 |
|
|
when others =>
|
| 1110 |
|
|
n.er1ilf(to_integer(unsigned(r.cs2unit))) := '1';
|
| 1111 |
|
|
n.dsata(to_integer(unsigned(r.cs2unit))) := '1';
|
| 1112 |
|
|
|
| 1113 |
|
|
end case; -- IB_MREQ.din(cs1_ibf_func)
|
| 1114 |
|
|
|
| 1115 |
|
|
when s_chkdc => -- chkdc: handle dc check ------------
|
| 1116 |
|
|
imem_addr := r.cs2unit & amapc_dc; -- mem address of dc reg
|
| 1117 |
|
|
if unsigned(MEM_DOUT(dc_ibf_ca)) > unsigned(r.camax) then
|
| 1118 |
|
|
n.er1iae(to_integer(unsigned(r.cs2unit))) := '1';
|
| 1119 |
|
|
end if;
|
| 1120 |
|
|
ibhold := '1';
|
| 1121 |
|
|
n.state := s_chkda;
|
| 1122 |
|
|
|
| 1123 |
|
|
when s_chkda => -- chkda: handle da check ------------
|
| 1124 |
|
|
imem_addr := r.cs2unit & amapc_da; -- mem address of da reg
|
| 1125 |
|
|
if unsigned(MEM_DOUT(da_ibf_sa)) > unsigned(r.samax) or
|
| 1126 |
|
|
unsigned(MEM_DOUT(da_ibf_ta)) > unsigned(r.tamax) then
|
| 1127 |
|
|
n.er1iae(to_integer(unsigned(r.cs2unit))) := '1';
|
| 1128 |
|
|
end if;
|
| 1129 |
|
|
ibhold := '1';
|
| 1130 |
|
|
n.state := s_chkdo;
|
| 1131 |
|
|
|
| 1132 |
|
|
when s_chkdo => -- chkdo: execute function -----------
|
| 1133 |
|
|
if r.er1iae(to_integer(unsigned(r.cs2unit))) = '1' or
|
| 1134 |
|
|
r.er1wle(to_integer(unsigned(r.cs2unit))) = '1' then
|
| 1135 |
|
|
n.dsata(to_integer(unsigned(r.cs2unit))) := '1'; -- ata and done
|
| 1136 |
|
|
else
|
| 1137 |
|
|
if r.fxfer = '0' then -- must be seek like function
|
| 1138 |
|
|
n.dspip(to_integer(unsigned(r.cs2unit))) := '1'; -- pip
|
| 1139 |
|
|
n.idlycnt := r.idlyval; -- start delay
|
| 1140 |
|
|
else -- must be transfer function
|
| 1141 |
|
|
n.ffunc := IB_MREQ.din(cs1_ibf_func); -- latch func
|
| 1142 |
|
|
n.funit := r.cs2unit; -- latch unit
|
| 1143 |
|
|
n.cs1rdy := '0'; -- controller busy
|
| 1144 |
|
|
n.cs2wce := '0'; -- clear errors
|
| 1145 |
|
|
n.cs2ned := '0';
|
| 1146 |
|
|
n.cs2nem := '0';
|
| 1147 |
|
|
n.cs2pge := '0';
|
| 1148 |
|
|
n.cs2mxf := '0';
|
| 1149 |
|
|
ilam := '1'; -- issue lam
|
| 1150 |
|
|
end if;
|
| 1151 |
|
|
end if;
|
| 1152 |
|
|
n.state := s_idle;
|
| 1153 |
|
|
|
| 1154 |
|
|
when s_read => -- read: all register reads ----------
|
| 1155 |
|
|
n.state := s_idle; -- in general return to s_idle
|
| 1156 |
|
|
imem_addr := r.amap;
|
| 1157 |
|
|
|
| 1158 |
|
|
case r.omux is
|
| 1159 |
|
|
|
| 1160 |
|
|
when omux_cs1 => -- omux: cs1 reg ---------------
|
| 1161 |
|
|
idout(cs1_ibf_sc) := r.cs1sc;
|
| 1162 |
|
|
idout(cs1_ibf_tre) := r.cs1tre;
|
| 1163 |
|
|
idout(cs1_ibf_dva) := '1';
|
| 1164 |
|
|
idout(cs1_ibf_bae) := r.bae(1 downto 0);
|
| 1165 |
|
|
idout(cs1_ibf_rdy) := r.cs1rdy;
|
| 1166 |
|
|
idout(cs1_ibf_ie) := r.cs1ie;
|
| 1167 |
|
|
if ibrem = '0' then -- loc access
|
| 1168 |
|
|
idout(cs1_ibf_func) := MEM_DOUT(cs1_ibf_func); --func per unit
|
| 1169 |
|
|
if r.ned = '1' then -- drive off
|
| 1170 |
|
|
n.cs2ned := '1'; -- signal error
|
| 1171 |
|
|
end if;
|
| 1172 |
|
|
else -- rem access
|
| 1173 |
|
|
idout(cs1_ibf_func) := r.ffunc;
|
| 1174 |
|
|
end if;
|
| 1175 |
|
|
|
| 1176 |
|
|
when omux_cs2 => -- omux: cs2 reg ---------------
|
| 1177 |
|
|
idout(cs2_ibf_wce) := r.cs2wce;
|
| 1178 |
|
|
idout(cs2_ibf_ned) := r.cs2ned;
|
| 1179 |
|
|
idout(cs2_ibf_nem) := r.cs2nem;
|
| 1180 |
|
|
idout(cs2_ibf_pge) := r.cs2pge;
|
| 1181 |
|
|
idout(cs2_ibf_mxf) := r.cs2mxf;
|
| 1182 |
|
|
idout(cs2_ibf_or) := '1';
|
| 1183 |
|
|
idout(cs2_ibf_ir) := '1';
|
| 1184 |
|
|
idout(cs2_ibf_pat) := r.cs2pat;
|
| 1185 |
|
|
idout(cs2_ibf_bai) := r.cs2bai;
|
| 1186 |
|
|
idout(cs2_ibf_unit2) := r.cs2unit2;
|
| 1187 |
|
|
if ibrem = '0' then -- loc access
|
| 1188 |
|
|
idout(cs2_ibf_unit) := r.cs2unit;
|
| 1189 |
|
|
else -- rem access
|
| 1190 |
|
|
idout(cs2_ibf_unit) := r.funit;
|
| 1191 |
|
|
end if;
|
| 1192 |
|
|
|
| 1193 |
|
|
when omux_ds => -- omux: ds reg ---------------
|
| 1194 |
|
|
idout(ds_ibf_ata) := r.dsata(to_integer(unsigned(r.eunit)));
|
| 1195 |
|
|
idout(ds_ibf_erp) := r.dserp(to_integer(unsigned(r.eunit)));
|
| 1196 |
|
|
idout(ds_ibf_pip) := r.dspip(to_integer(unsigned(r.eunit)));
|
| 1197 |
|
|
idout(ds_ibf_mol) := r.dsmol(to_integer(unsigned(r.eunit)));
|
| 1198 |
|
|
idout(ds_ibf_wrl) := r.dswrl(to_integer(unsigned(r.eunit)));
|
| 1199 |
|
|
idout(ds_ibf_lbt) := r.dslbt(to_integer(unsigned(r.eunit)));
|
| 1200 |
|
|
idout(ds_ibf_dpr) := r.dsdpr(to_integer(unsigned(r.eunit)));
|
| 1201 |
|
|
|
| 1202 |
|
|
-- ds.dry is 0 if mol=0 or if transfer or seek is active on unit
|
| 1203 |
|
|
-- the logic below checks for the complement ...
|
| 1204 |
|
|
if r.dsmol(to_integer(unsigned(r.eunit))) = '1' then
|
| 1205 |
|
|
if (r.cs1rdy = '1' or r.funit /= r.eunit) and
|
| 1206 |
|
|
r.dspip(to_integer(unsigned(r.eunit))) = '0' then
|
| 1207 |
|
|
idout(ds_ibf_dry) := '1';
|
| 1208 |
|
|
end if;
|
| 1209 |
|
|
end if;
|
| 1210 |
|
|
|
| 1211 |
|
|
idout(ds_ibf_vv) := r.dsvv (to_integer(unsigned(r.eunit)));
|
| 1212 |
|
|
idout(ds_ibf_om) := r.dsom (to_integer(unsigned(r.eunit)));
|
| 1213 |
|
|
|
| 1214 |
|
|
when omux_er1 => -- omux: er1 reg ---------------
|
| 1215 |
|
|
idout(er1_ibf_uns) := r.er1uns(to_integer(unsigned(r.eunit)));
|
| 1216 |
|
|
idout(er1_ibf_wle) := r.er1wle(to_integer(unsigned(r.eunit)));
|
| 1217 |
|
|
idout(er1_ibf_iae) := r.er1iae(to_integer(unsigned(r.eunit)));
|
| 1218 |
|
|
idout(er1_ibf_aoe) := r.er1aoe(to_integer(unsigned(r.eunit)));
|
| 1219 |
|
|
idout(er1_ibf_rmr) := r.er1rmr(to_integer(unsigned(r.eunit)));
|
| 1220 |
|
|
idout(er1_ibf_ilf) := r.er1ilf(to_integer(unsigned(r.eunit)));
|
| 1221 |
|
|
|
| 1222 |
|
|
when omux_as => -- omux: as reg ---------------
|
| 1223 |
|
|
idout(r.dsata'range) := r.dsata;
|
| 1224 |
|
|
|
| 1225 |
|
|
when omux_la => -- omux: la reg ---------------
|
| 1226 |
|
|
idout(la_ibf_sc) := r.sc;
|
| 1227 |
|
|
|
| 1228 |
|
|
when omux_dt => -- omux: dt reg ---------------
|
| 1229 |
|
|
if ibrem = '0' then -- loc access
|
| 1230 |
|
|
idout(13) := '1'; -- set bit 020000 (movable head)
|
| 1231 |
|
|
idout(r.dtyp'range) := r.dtyp;
|
| 1232 |
|
|
else -- rem access (read back rem side)
|
| 1233 |
|
|
idout(dt_ibf_rm) := r.dtrm(to_integer(unsigned(r.runit)));
|
| 1234 |
|
|
idout(dt_ibf_e1) := r.dte1(to_integer(unsigned(r.runit)));
|
| 1235 |
|
|
idout(dt_ibf_e0) := r.dte0(to_integer(unsigned(r.runit)));
|
| 1236 |
|
|
end if;
|
| 1237 |
|
|
|
| 1238 |
|
|
when omux_sn => -- omux: sn reg ---------------
|
| 1239 |
|
|
-- the serial number is encoded as 4 digit BCD
|
| 1240 |
|
|
-- digit 3: always 1
|
| 1241 |
|
|
-- digit 2: 1 if RM type; 0 if RP type
|
| 1242 |
|
|
-- digit 1: 0-3 based on encoded drive type
|
| 1243 |
|
|
-- digit 0: 0-3 taken from unit
|
| 1244 |
|
|
idout(12) := '1';
|
| 1245 |
|
|
idout(8) := r.dtrm(to_integer(unsigned(r.eunit)));
|
| 1246 |
|
|
idout(5) := r.dte1(to_integer(unsigned(r.eunit)));
|
| 1247 |
|
|
idout(4) := r.dte0(to_integer(unsigned(r.eunit)));
|
| 1248 |
|
|
idout(1) := r.eunit(1);
|
| 1249 |
|
|
idout(0) := r.eunit(0);
|
| 1250 |
|
|
|
| 1251 |
|
|
when omux_bae => -- omux: bae reg ---------------
|
| 1252 |
|
|
idout(bae_ibf_bae) := r.bae;
|
| 1253 |
|
|
|
| 1254 |
|
|
when omux_cs3 => -- omux: cs3 reg ---------------
|
| 1255 |
|
|
idout(cs3_ibf_wco) := r.cs2wce and r.cs3wco;
|
| 1256 |
|
|
idout(cs3_ibf_wce) := r.cs2wce and not r.cs3wco;
|
| 1257 |
|
|
idout(cs3_ibf_ie) := r.cs1ie;
|
| 1258 |
|
|
if ibrem = '1' then -- rem access
|
| 1259 |
|
|
idout(cs3_ibf_rseardone) := r.seardone;
|
| 1260 |
|
|
idout(cs3_ibf_rpackdone) := r.packdone;
|
| 1261 |
|
|
idout(cs3_ibf_rporedone) := r.poredone;
|
| 1262 |
|
|
idout(cs3_ibf_rseekdone) := r.seekdone;
|
| 1263 |
|
|
if IB_MREQ.re = '1' then -- if read, do read & clear
|
| 1264 |
|
|
n.seardone := '0';
|
| 1265 |
|
|
n.packdone := '0';
|
| 1266 |
|
|
n.poredone := '0';
|
| 1267 |
|
|
n.seekdone := '0';
|
| 1268 |
|
|
end if;
|
| 1269 |
|
|
end if;
|
| 1270 |
|
|
|
| 1271 |
|
|
when omux_mem => -- omux: mem output ------------
|
| 1272 |
|
|
idout := MEM_DOUT;
|
| 1273 |
|
|
|
| 1274 |
|
|
when omux_zero => -- omux: zero ------------------
|
| 1275 |
|
|
idout := (others=>'0');
|
| 1276 |
|
|
|
| 1277 |
|
|
when others => null; -- nxr caught before in mapper !
|
| 1278 |
|
|
end case; -- case r.omux
|
| 1279 |
|
|
|
| 1280 |
|
|
when s_setrmr => -- set rmr flag ----------------------
|
| 1281 |
|
|
n.er1rmr(to_integer(unsigned(r.cs2unit))) := '1';
|
| 1282 |
|
|
n.state := s_idle;
|
| 1283 |
|
|
|
| 1284 |
|
|
when s_oot_clr0 => -- OOT clr0: state 0 -----------------
|
| 1285 |
|
|
if r.clrmode=clrmode_breset or r.clrmode=clrmode_cs2clr then
|
| 1286 |
|
|
n.cs1rdy := '1'; -- clear cs1
|
| 1287 |
|
|
n.cs1ie := '0';
|
| 1288 |
|
|
n.cs2wce := '0'; -- clear cs2
|
| 1289 |
|
|
n.cs2ned := '0';
|
| 1290 |
|
|
n.cs2nem := '0';
|
| 1291 |
|
|
n.cs2pge := '0';
|
| 1292 |
|
|
n.cs2mxf := '0';
|
| 1293 |
|
|
n.cs2pat := '0';
|
| 1294 |
|
|
n.cs2bai := '0';
|
| 1295 |
|
|
n.cs2unit2 := '0';
|
| 1296 |
|
|
n.cs2unit := (others=>'0');
|
| 1297 |
|
|
n.bae := (others=>'0'); -- clear bae
|
| 1298 |
|
|
n.ireq := '0'; -- clear iff
|
| 1299 |
|
|
end if;
|
| 1300 |
|
|
|
| 1301 |
|
|
if r.clrmode=clrmode_breset or r.clrmode=clrmode_fdclr then
|
| 1302 |
|
|
n.er1uns(to_integer(unsigned(r.eunit))) := '0'; -- clr all er1
|
| 1303 |
|
|
n.er1wle(to_integer(unsigned(r.eunit))) := '0'; -- "
|
| 1304 |
|
|
n.er1iae(to_integer(unsigned(r.eunit))) := '0'; -- "
|
| 1305 |
|
|
n.er1aoe(to_integer(unsigned(r.eunit))) := '0'; -- "
|
| 1306 |
|
|
n.er1rmr(to_integer(unsigned(r.eunit))) := '0'; -- "
|
| 1307 |
|
|
n.er1ilf(to_integer(unsigned(r.eunit))) := '0'; -- "
|
| 1308 |
|
|
end if;
|
| 1309 |
|
|
|
| 1310 |
|
|
n.cerm := r.dtrm(to_integer(unsigned(ieunit)));
|
| 1311 |
|
|
|
| 1312 |
|
|
n.clrreg := "000";
|
| 1313 |
|
|
ibhold := r.ibsel; -- delay pending request
|
| 1314 |
|
|
n.state := s_oot_clr1;
|
| 1315 |
|
|
|
| 1316 |
|
|
when s_oot_clr1 => -- OOT clr1: state 1 ----------------
|
| 1317 |
|
|
imem_addr := r.eunit & r.clrreg;
|
| 1318 |
|
|
imem_din := (others=>'0');
|
| 1319 |
|
|
|
| 1320 |
|
|
iclrreg := '0';
|
| 1321 |
|
|
case r.clrmode is
|
| 1322 |
|
|
|
| 1323 |
|
|
when clrmode_breset => -- BRESET -------------------------
|
| 1324 |
|
|
iclrreg := '1'; -- simply clear all (cntl+drives)
|
| 1325 |
|
|
|
| 1326 |
|
|
when clrmode_cs2clr => -- CS2.CLR (controller clr) -------
|
| 1327 |
|
|
case r.clrreg is
|
| 1328 |
|
|
when amapc_ext => iclrreg := '1';
|
| 1329 |
|
|
when amapc_mr1 => iclrreg := r.cerm;
|
| 1330 |
|
|
when others => null;
|
| 1331 |
|
|
end case;
|
| 1332 |
|
|
|
| 1333 |
|
|
when clrmode_fdclr => -- func=DCLR (drive clr) ----------
|
| 1334 |
|
|
case r.clrreg is
|
| 1335 |
|
|
when amapc_mr1 => iclrreg := r.cerm;
|
| 1336 |
|
|
when others => null;
|
| 1337 |
|
|
end case;
|
| 1338 |
|
|
|
| 1339 |
|
|
when clrmode_fpres => -- func=PRESET --------------------
|
| 1340 |
|
|
case r.clrreg is
|
| 1341 |
|
|
when amapc_da => iclrreg := '1';
|
| 1342 |
|
|
when amapc_of => iclrreg := '1';
|
| 1343 |
|
|
when amapc_dc => iclrreg := '1';
|
| 1344 |
|
|
when others => null;
|
| 1345 |
|
|
end case;
|
| 1346 |
|
|
|
| 1347 |
|
|
when others => null;
|
| 1348 |
|
|
end case;
|
| 1349 |
|
|
if iclrreg = '1' then
|
| 1350 |
|
|
imem_we0 := IB_MREQ.be0;
|
| 1351 |
|
|
imem_we1 := IB_MREQ.be1;
|
| 1352 |
|
|
end if;
|
| 1353 |
|
|
n.clrreg := slv(unsigned(r.clrreg) + 1);
|
| 1354 |
|
|
|
| 1355 |
|
|
ibhold := r.ibsel; -- delay pending request
|
| 1356 |
|
|
if r.clrreg = "111" then -- if last register done
|
| 1357 |
|
|
n.state := s_oot_clr2; -- proceed with clr2
|
| 1358 |
|
|
end if;
|
| 1359 |
|
|
|
| 1360 |
|
|
when s_oot_clr2 => -- OOT clr2: state 2 ----------------
|
| 1361 |
|
|
n.eunit := slv(unsigned(r.eunit) + 1);
|
| 1362 |
|
|
|
| 1363 |
|
|
ibhold := r.ibsel; -- delay pending request, so that
|
| 1364 |
|
|
-- s_idle can finally process it
|
| 1365 |
|
|
if (r.clrmode=clrmode_breset or r.clrmode=clrmode_cs2clr) and
|
| 1366 |
|
|
r.eunit /= "11" then
|
| 1367 |
|
|
n.state := s_oot_clr0;
|
| 1368 |
|
|
else
|
| 1369 |
|
|
n.state := s_idle;
|
| 1370 |
|
|
end if;
|
| 1371 |
|
|
|
| 1372 |
|
|
when others => null; -- <> ------------------------------
|
| 1373 |
|
|
end case; -- case r.state
|
| 1374 |
|
|
|
| 1375 |
|
|
-- update cs1tre and cs1sc
|
| 1376 |
|
|
n.cs1tre := r.cs2wce or r.cs2ned or r.cs2nem or r.cs2pge or r.cs2mxf;
|
| 1377 |
|
|
n.cs1sc := n.cs1tre or r.dsata(0) or r.dsata(1) or r.dsata(2) or r.dsata(3);
|
| 1378 |
|
|
-- update dserp
|
| 1379 |
|
|
n.dserp := r.er1uns or -- or all er1
|
| 1380 |
|
|
r.er1wle or -- "
|
| 1381 |
|
|
r.er1iae or -- "
|
| 1382 |
|
|
r.er1aoe or -- "
|
| 1383 |
|
|
r.er1rmr or -- "
|
| 1384 |
|
|
r.er1ilf; -- "
|
| 1385 |
|
|
|
| 1386 |
|
|
-- handle current sector counter (for RxLA emulation)
|
| 1387 |
|
|
-- advance every 128 usec, so generate a pulse every 128 usec
|
| 1388 |
|
|
if CE_USEC = '1' then
|
| 1389 |
|
|
n.uscnt := slv(unsigned(r.uscnt) + 1);
|
| 1390 |
|
|
if unsigned(r.uscnt) = 0 then
|
| 1391 |
|
|
iscinc := '1';
|
| 1392 |
|
|
end if;
|
| 1393 |
|
|
end if;
|
| 1394 |
|
|
|
| 1395 |
|
|
-- if current sector larger or equal highest sector wrap to zero
|
| 1396 |
|
|
-- note: iscinc is also '1' when unit changes, this ensures that
|
| 1397 |
|
|
-- the sector counter is always in range when read to ibus.
|
| 1398 |
|
|
if iscinc = '1' then
|
| 1399 |
|
|
if unsigned(r.sc) >= unsigned(r.samax) then
|
| 1400 |
|
|
n.sc := (others=>'0');
|
| 1401 |
|
|
else
|
| 1402 |
|
|
n.sc := slv(unsigned(r.sc) + 1);
|
| 1403 |
|
|
end if;
|
| 1404 |
|
|
end if;
|
| 1405 |
|
|
|
| 1406 |
|
|
-- the RH70 interrupt logic is very unusual
|
| 1407 |
|
|
-- 1. done interrupts (rdy 0->1) are edge sensitive (via r.ireq)
|
| 1408 |
|
|
-- 2. done interrupts are not canceled when IE is cleared
|
| 1409 |
|
|
-- 3. attention interrupts are level sensitive (via r.cs1sc)
|
| 1410 |
|
|
-- 4. IE is disabled on interrupt acknowledge
|
| 1411 |
|
|
|
| 1412 |
|
|
iei_req := r.ireq or (r.cs1sc and r.cs1ie and r.cs1rdy);
|
| 1413 |
|
|
|
| 1414 |
|
|
if EI_ACK = '1' then -- interrupt executed
|
| 1415 |
|
|
n.ireq := '0'; -- cancel request
|
| 1416 |
|
|
n.cs1ie := '0'; -- disable interrupts
|
| 1417 |
|
|
end if;
|
| 1418 |
|
|
|
| 1419 |
|
|
N_REGS <= n;
|
| 1420 |
|
|
|
| 1421 |
|
|
MEM_0_WE <= imem_we0;
|
| 1422 |
|
|
MEM_1_WE <= imem_we1;
|
| 1423 |
|
|
MEM_ADDR <= imem_addr;
|
| 1424 |
|
|
MEM_DIN <= imem_din;
|
| 1425 |
|
|
|
| 1426 |
|
|
IB_SRES.dout <= idout;
|
| 1427 |
|
|
IB_SRES.ack <= r.ibsel and ibreq;
|
| 1428 |
|
|
IB_SRES.busy <= ibhold and ibreq;
|
| 1429 |
|
|
|
| 1430 |
|
|
RB_LAM <= ilam;
|
| 1431 |
|
|
EI_REQ <= iei_req;
|
| 1432 |
|
|
|
| 1433 |
|
|
end process proc_next;
|
| 1434 |
|
|
|
| 1435 |
|
|
|
| 1436 |
|
|
end syn;
|
