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-- $Id: sys_tst_rlink_n3.vhd 748 2016-03-20 15:18:50Z mueller $

--

-- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>

--

-- This program is free software; you may redistribute and/or modify it under

-- the terms of the GNU General Public License as published by the Free

-- Software Foundation, either version 2, or at your option any later version.

--

-- This program is distributed in the hope that it will be useful, but

-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY

-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

-- for complete details.

--

------------------------------------------------------------------------------

-- Module Name:    sys_tst_rlink_n3 - syn

-- Description:    rlink tester design for nexys3

--

-- Dependencies:   vlib/xlib/s6_cmt_sfs

--                 vlib/genlib/clkdivce

--                 bplib/bpgen/bp_rs232_2l4l_iob

--                 bplib/bpgen/sn_humanio_rbus

--                 vlib/rlink/rlink_sp1c

--                 rbd_tst_rlink

--                 vlib/rbus/rb_sres_or_2

--                 vlib/nxcramlib/nx_cram_dummy

--

-- Test bench:     tb/tb_tst_rlink_n3

--

-- Target Devices: generic

-- Tool versions:  xst 13.1-14.7; ghdl 0.29-0.33

--

-- Synthesized (xst):

-- Date         Rev  ise         Target      flop lutl lutm slic t peri

-- 2016-03-13   743 14.7  131013 xc6slx16-2   950 1380   70  504

-- 2014-12-20   614 14.7  131013 xc6slx16-2   917 1379   64  513 t  8.9

-- 2011-12-18   440 13.1    O40d xc6slx16-2   752 1258   48  439 t  7.9

-- 2011-11-26   433 13.1    O40d xc6slx16-2   722 1199   36  423 t  9.7

--

-- Revision History: 

-- Date         Rev Version  Comment

-- 2016-03-19   748   1.4.2  define rlink SYSID

-- 2015-04-11   666   1.4.1  rearrange XON handling

-- 2014-11-09   603   1.4    use new rlink v4 iface and 4 bit STAT

-- 2014-08-15   583   1.3    rb_mreq addr now 16 bit

-- 2013-10-06   538   1.2    pll support, use clksys_vcodivide ect

-- 2011-12-18   440   1.1.1  use [rt]xok for DSP_DP

-- 2011-12-11   438   1.1    use now rbd_tst_rlink and rlink_sp1c

-- 2011-11-26   433   1.0    Initial version (derived from sys_tst_rlink_n2)

------------------------------------------------------------------------------

-- Usage of Nexys 3 Switches, Buttons, LEDs:

--

--    SWI(7:2): no function (only connected to sn_humanio_rbus)

--    SWI(1):   1 enable XON

--    SWI(0):   0 -> main board RS232 port  - implemented in bp_rs232_2l4l_iob

--              1 -> Pmod B/top RS232 port  /

--

--    LED(7):   SER_MONI.abact

--    LED(6:2): no function (only connected to sn_humanio_rbus)

--    LED(1):   timer 1 busy 

--    LED(0):   timer 0 busy 

--

--    DSP:      SER_MONI.clkdiv         (from auto bauder)

--    DP(3):    not SER_MONI.txok       (shows tx back preasure)

--    DP(2):    SER_MONI.txact          (shows tx activity)

--    DP(1):    not SER_MONI.rxok       (shows rx back preasure)

--    DP(0):    SER_MONI.rxact          (shows rx activity)

--

library ieee;

use ieee.std_logic_1164.all;

use work.slvtypes.all;

use work.xlib.all;

use work.genlib.all;

use work.serportlib.all;

use work.rblib.all;

use work.rlinklib.all;

use work.bpgenlib.all;

use work.bpgenrbuslib.all;

use work.nxcramlib.all;

use work.sys_conf.all;

-- ----------------------------------------------------------------------------

entity sys_tst_rlink_n3 is              -- top level

                                        -- implements nexys3_fusp_aif

  port (

    I_CLK100 : in slbit;                -- 100 MHz clock

    I_RXD : in slbit;                   -- receive data (board view)

    O_TXD : out slbit;                  -- transmit data (board view)

    I_SWI : in slv8;                    -- n3 switches

    I_BTN : in slv5;                    -- n3 buttons

    O_LED : out slv8;                   -- n3 leds

    O_ANO_N : out slv4;                 -- 7 segment disp: anodes   (act.low)

    O_SEG_N : out slv8;                 -- 7 segment disp: segments (act.low)

    O_MEM_CE_N : out slbit;             -- cram: chip enable   (act.low)

    O_MEM_BE_N : out slv2;              -- cram: byte enables  (act.low)

    O_MEM_WE_N : out slbit;             -- cram: write enable  (act.low)

    O_MEM_OE_N : out slbit;             -- cram: output enable (act.low)

    O_MEM_ADV_N  : out slbit;           -- cram: address valid (act.low)

    O_MEM_CLK : out slbit;              -- cram: clock

    O_MEM_CRE : out slbit;              -- cram: command register enable

    I_MEM_WAIT : in slbit;              -- cram: mem wait

    O_MEM_ADDR  : out slv23;            -- cram: address lines

    IO_MEM_DATA : inout slv16;          -- cram: data lines

    O_PPCM_CE_N : out slbit;            -- ppcm: ...

    O_PPCM_RST_N : out slbit;           -- ppcm: ...

    O_FUSP_RTS_N : out slbit;           -- fusp: rs232 rts_n

    I_FUSP_CTS_N : in slbit;            -- fusp: rs232 cts_n

    I_FUSP_RXD : in slbit;              -- fusp: rs232 rx

    O_FUSP_TXD : out slbit              -- fusp: rs232 tx

  );

end sys_tst_rlink_n3;

architecture syn of sys_tst_rlink_n3 is

  signal CLK :   slbit := '0';

  signal RXD :   slbit := '1';

  signal TXD :   slbit := '0';

  signal RTS_N : slbit := '0';

  signal CTS_N : slbit := '0';

  signal SWI     : slv8  := (others=>'0');

  signal BTN     : slv5  := (others=>'0');

  signal LED     : slv8  := (others=>'0');

  signal DSP_DAT : slv16 := (others=>'0');

  signal DSP_DP  : slv4  := (others=>'0');

  signal RESET   : slbit := '0';

  signal CE_USEC : slbit := '0';

  signal CE_MSEC : slbit := '0';

  signal RB_MREQ : rb_mreq_type := rb_mreq_init;

  signal RB_SRES : rb_sres_type := rb_sres_init;

  signal RB_SRES_HIO : rb_sres_type := rb_sres_init;

  signal RB_SRES_TST : rb_sres_type := rb_sres_init;

  signal RB_LAM  : slv16 := (others=>'0');

  signal RB_STAT : slv4  := (others=>'0');

  signal SER_MONI : serport_moni_type := serport_moni_init;

  signal STAT    : slv8  := (others=>'0');

  constant rbaddr_hio   : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx

  constant sysid_proj  : slv16 := x"0101";   -- tst_rlink

  constant sysid_board : slv8  := x"03";     -- nexys3

  constant sysid_vers  : slv8  := x"00";

begin

  assert (sys_conf_clksys mod 1000000) = 0

    report "assert sys_conf_clksys on MHz grid"

    severity failure;

  RESET <= '0';                         -- so far not used

  GEN_CLKSYS : s6_cmt_sfs

    generic map (

      VCO_DIVIDE     => sys_conf_clksys_vcodivide,

      VCO_MULTIPLY   => sys_conf_clksys_vcomultiply,

      OUT_DIVIDE     => sys_conf_clksys_outdivide,

      CLKIN_PERIOD   => 10.0,

      CLKIN_JITTER   => 0.01,

      STARTUP_WAIT   => false,

      GEN_TYPE       => sys_conf_clksys_gentype)

    port map (

      CLKIN   => I_CLK100,

      CLKFX   => CLK,

      LOCKED  => open

    );

  CLKDIV : clkdivce

    generic map (

      CDUWIDTH => 7,

      USECDIV  => sys_conf_clksys_mhz,

      MSECDIV  => 1000)

    port map (

      CLK     => CLK,

      CE_USEC => CE_USEC,

      CE_MSEC => CE_MSEC

    );

  IOB_RS232 : bp_rs232_2l4l_iob

    port map (

      CLK      => CLK,

      RESET    => '0',

      SEL      => SWI(0),

      RXD      => RXD,

      TXD      => TXD,

      CTS_N    => CTS_N,

      RTS_N    => RTS_N,

      I_RXD0   => I_RXD,

      O_TXD0   => O_TXD,

      I_RXD1   => I_FUSP_RXD,

      O_TXD1   => O_FUSP_TXD,

      I_CTS1_N => I_FUSP_CTS_N,

      O_RTS1_N => O_FUSP_RTS_N

    );

  HIO : sn_humanio_rbus

    generic map (

      BWIDTH   => 5,

      DEBOUNCE => sys_conf_hio_debounce,

      RB_ADDR  => rbaddr_hio)

    port map (

      CLK     => CLK,

      RESET   => RESET,

      CE_MSEC => CE_MSEC,

      RB_MREQ => RB_MREQ,

      RB_SRES => RB_SRES_HIO,

      SWI     => SWI,

      BTN     => BTN,

      LED     => LED,

      DSP_DAT => DSP_DAT,

      DSP_DP  => DSP_DP,

      I_SWI   => I_SWI,

      I_BTN   => I_BTN,

      O_LED   => O_LED,

      O_ANO_N => O_ANO_N,

      O_SEG_N => O_SEG_N

    );

  RLINK : rlink_sp1c

    generic map (

      BTOWIDTH     => 6,

      RTAWIDTH     => 12,

      SYSID        => sysid_proj & sysid_board & sysid_vers,

      IFAWIDTH     => 5,

      OFAWIDTH     => 5,

      ENAPIN_RLMON => sbcntl_sbf_rlmon,

      ENAPIN_RBMON => sbcntl_sbf_rbmon,

      CDWIDTH      => 15,

      CDINIT       => sys_conf_ser2rri_cdinit,

      RBMON_AWIDTH => 0,                -- must be 0, rbmon in rbd_tst_rlink

      RBMON_RBADDR => (others=>'0'))

    port map (

      CLK      => CLK,

      CE_USEC  => CE_USEC,

      CE_MSEC  => CE_MSEC,

      CE_INT   => CE_MSEC,

      RESET    => RESET,

      ENAXON   => SWI(1),

      ESCFILL  => '0',

      RXSD     => RXD,

      TXSD     => TXD,

      CTS_N    => CTS_N,

      RTS_N    => RTS_N,

      RB_MREQ  => RB_MREQ,

      RB_SRES  => RB_SRES,

      RB_LAM   => RB_LAM,

      RB_STAT  => RB_STAT,

      RL_MONI  => open,

      SER_MONI => SER_MONI

    );

  RBDTST : entity work.rbd_tst_rlink

    port map (

      CLK         => CLK,

      RESET       => RESET,

      CE_USEC     => CE_USEC,

      RB_MREQ     => RB_MREQ,

      RB_SRES     => RB_SRES_TST,

      RB_LAM      => RB_LAM,

      RB_STAT     => RB_STAT,

      RB_SRES_TOP => RB_SRES,

      RXSD        => RXD,

      RXACT       => SER_MONI.rxact,

      STAT        => STAT

    );

  RB_SRES_OR1 : rb_sres_or_2

    port map (

      RB_SRES_1  => RB_SRES_HIO,

      RB_SRES_2  => RB_SRES_TST,

      RB_SRES_OR => RB_SRES

    );

  SRAM_PROT : nx_cram_dummy            -- connect CRAM to protection dummy

    port map (

      O_MEM_CE_N  => O_MEM_CE_N,

      O_MEM_BE_N  => O_MEM_BE_N,

      O_MEM_WE_N  => O_MEM_WE_N,

      O_MEM_OE_N  => O_MEM_OE_N,

      O_MEM_ADV_N => O_MEM_ADV_N,

      O_MEM_CLK   => O_MEM_CLK,

      O_MEM_CRE   => O_MEM_CRE,

      I_MEM_WAIT  => I_MEM_WAIT,

      O_MEM_ADDR  => O_MEM_ADDR,

      IO_MEM_DATA => IO_MEM_DATA

    );

  O_PPCM_CE_N  <= '1';                  -- keep parallel PCM memory disabled

  O_PPCM_RST_N <= '1';                  --

  DSP_DAT   <= SER_MONI.abclkdiv;

  DSP_DP(3) <= not SER_MONI.txok;

  DSP_DP(2) <= SER_MONI.txact;

  DSP_DP(1) <= not SER_MONI.rxok;

  DSP_DP(0) <= SER_MONI.rxact;

  LED(7) <= SER_MONI.abact;

  LED(6 downto 2) <= (others=>'0');

  LED(1) <= STAT(1);

  LED(0) <= STAT(0);

end syn;