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-- $Id: sys_tst_rlink_cuff_atlys.vhd 734 2016-02-20 22:43:20Z mueller $
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--
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-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: sys_tst_rlink_cuff_atlys - syn
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-- Description: rlink tester design for atlys with fx2 interface
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--
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-- Dependencies: vlib/xlib/dcm_sfs
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-- vlib/genlib/clkdivce
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-- bplib/bpgen/bp_rs232_2l4l_iob
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-- bplib/bpgen/sn_humanio_demu_rbus
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-- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"]
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-- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"]
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-- tst_rlink_cuff
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--
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-- Test bench: -
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--
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-- Target Devices: generic
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-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
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--
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz
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-- 2013-01-06 472 13.3 O76d xc6slx45 ??? ???? ??? ???? p ??.? ic2/100
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2015-01-25 638 1.1.2 retire fx2_2fifoctl_as
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-- 2014-12-24 620 1.1.1 relocate hio rbus address
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-- 2014-08-15 583 1.1 rb_mreq addr now 16 bit
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-- 2013-01-06 472 1.0 Initial version; derived from sys_tst_rlink_cuff_n3
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-- and sys_tst_fx2loop_atlys
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------------------------------------------------------------------------------
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-- Usage of Atlys Switches, Buttons, LEDs:
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--
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-- SWI(7:3) no function (only connected to sn_humanio_demu_rbus)
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-- (2) 0 -> int/ext RS242 port for rlink
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-- 1 -> use USB interface for rlink
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-- (1) 1 enable XON
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-- (0) 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob
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-- 1 -> Pmod B/top RS232 port /
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--
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-- LED(7) SER_MONI.abact
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-- (6:2) no function (only connected to sn_humanio_demu_rbus)
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-- (1) timer 1 busy
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-- (0) timer 0 busy
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--
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-- DSP: SER_MONI.clkdiv (from auto bauder)
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-- for SWI(2)='0' (serport)
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-- DP(3) not SER_MONI.txok (shows tx back preasure)
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-- (2) SER_MONI.txact (shows tx activity)
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-- (1) not SER_MONI.rxok (shows rx back preasure)
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-- (0) SER_MONI.rxact (shows rx activity)
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-- for SWI(2)='1' (fx2)
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-- DP(3) FX2_TX2BUSY (shows tx2 back preasure)
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-- (2) FX2_TX2ENA(stretched) (shows tx2 activity)
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-- (1) FX2_TXENA(streched) (shows tx activity)
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-- (0) FX2_RXVAL(stretched) (shows rx activity)
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.xlib.all;
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use work.genlib.all;
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use work.bpgenlib.all;
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use work.bpgenrbuslib.all;
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use work.rblib.all;
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use work.fx2lib.all;
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use work.sys_conf.all;
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-- ----------------------------------------------------------------------------
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entity sys_tst_rlink_cuff_atlys is -- top level
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-- implements atlys_fusp_cuff_aif
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port (
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I_CLK100 : in slbit; -- 100 MHz clock
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I_USB_RXD : in slbit; -- USB UART receive data (board view)
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O_USB_TXD : out slbit; -- USB UART transmit data (board view)
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I_HIO_SWI : in slv8; -- atlys hio switches
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I_HIO_BTN : in slv6; -- atlys hio buttons
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O_HIO_LED: out slv8; -- atlys hio leds
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O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
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I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
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I_FUSP_RXD : in slbit; -- fusp: rs232 rx
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O_FUSP_TXD : out slbit; -- fusp: rs232 tx
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I_FX2_IFCLK : in slbit; -- fx2: interface clock
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O_FX2_FIFO : out slv2; -- fx2: fifo address
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I_FX2_FLAG : in slv4; -- fx2: fifo flags
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O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
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O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
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O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
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O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
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IO_FX2_DATA : inout slv8 -- fx2: data lines
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);
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end sys_tst_rlink_cuff_atlys;
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architecture syn of sys_tst_rlink_cuff_atlys is
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signal CLK : slbit := '0';
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signal RESET : slbit := '0';
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signal CE_USEC : slbit := '0';
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signal CE_MSEC : slbit := '0';
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signal RXSD : slbit := '0';
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signal TXSD : slbit := '0';
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signal CTS_N : slbit := '0';
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signal RTS_N : slbit := '0';
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signal SWI : slv8 := (others=>'0');
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signal BTN : slv4 := (others=>'0');
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signal LED : slv8 := (others=>'0');
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signal DSP_DAT : slv16 := (others=>'0');
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signal DSP_DP : slv4 := (others=>'0');
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signal RB_MREQ : rb_mreq_type := rb_mreq_init;
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signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
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signal FX2_RXDATA : slv8 := (others=>'0');
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signal FX2_RXVAL : slbit := '0';
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signal FX2_RXHOLD : slbit := '0';
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signal FX2_RXAEMPTY : slbit := '0';
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signal FX2_TXDATA : slv8 := (others=>'0');
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signal FX2_TXENA : slbit := '0';
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signal FX2_TXBUSY : slbit := '0';
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signal FX2_TXAFULL : slbit := '0';
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signal FX2_TX2DATA : slv8 := (others=>'0');
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signal FX2_TX2ENA : slbit := '0';
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signal FX2_TX2BUSY : slbit := '0';
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signal FX2_TX2AFULL : slbit := '0';
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signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init;
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constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx
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begin
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assert (sys_conf_clksys mod 1000000) = 0
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report "assert sys_conf_clksys on MHz grid"
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severity failure;
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DCM : dcm_sfs
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generic map (
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CLKFX_DIVIDE => sys_conf_clkfx_divide,
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CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
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CLKIN_PERIOD => 10.0)
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port map (
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CLKIN => I_CLK100,
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CLKFX => CLK,
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LOCKED => open
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);
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CLKDIV : clkdivce
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generic map (
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CDUWIDTH => 7, -- good for up to 127 MHz !
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USECDIV => sys_conf_clksys_mhz,
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MSECDIV => 1000)
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port map (
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CLK => CLK,
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CE_USEC => CE_USEC,
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CE_MSEC => CE_MSEC
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);
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IOB_RS232 : bp_rs232_2l4l_iob
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port map (
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CLK => CLK,
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RESET => '0',
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SEL => SWI(0),
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RXD => RXSD,
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TXD => TXSD,
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CTS_N => CTS_N,
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RTS_N => RTS_N,
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I_RXD0 => I_USB_RXD,
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O_TXD0 => O_USB_TXD,
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I_RXD1 => I_FUSP_RXD,
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O_TXD1 => O_FUSP_TXD,
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I_CTS1_N => I_FUSP_CTS_N,
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O_RTS1_N => O_FUSP_RTS_N
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);
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HIO : sn_humanio_demu_rbus
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generic map (
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DEBOUNCE => sys_conf_hio_debounce,
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RB_ADDR => rbaddr_hio)
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port map (
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CLK => CLK,
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RESET => RESET,
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CE_MSEC => CE_MSEC,
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RB_MREQ => RB_MREQ,
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RB_SRES => RB_SRES_HIO,
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SWI => SWI,
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BTN => BTN,
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LED => LED,
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DSP_DAT => DSP_DAT,
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DSP_DP => DSP_DP,
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I_SWI => I_HIO_SWI,
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I_BTN => I_HIO_BTN,
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O_LED => O_HIO_LED
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);
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FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate
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CNTL : fx2_2fifoctl_ic
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generic map (
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RXFAWIDTH => 5,
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TXFAWIDTH => 5,
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PETOWIDTH => sys_conf_fx2_petowidth,
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CCWIDTH => sys_conf_fx2_ccwidth,
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RXAEMPTY_THRES => 1,
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TXAFULL_THRES => 1)
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port map (
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CLK => CLK,
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RESET => RESET,
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RXDATA => FX2_RXDATA,
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RXVAL => FX2_RXVAL,
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RXHOLD => FX2_RXHOLD,
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RXAEMPTY => FX2_RXAEMPTY,
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TXDATA => FX2_TXDATA,
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TXENA => FX2_TXENA,
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TXBUSY => FX2_TXBUSY,
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TXAFULL => FX2_TXAFULL,
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MONI => FX2_MONI,
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I_FX2_IFCLK => I_FX2_IFCLK,
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O_FX2_FIFO => O_FX2_FIFO,
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I_FX2_FLAG => I_FX2_FLAG,
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O_FX2_SLRD_N => O_FX2_SLRD_N,
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O_FX2_SLWR_N => O_FX2_SLWR_N,
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O_FX2_SLOE_N => O_FX2_SLOE_N,
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O_FX2_PKTEND_N => O_FX2_PKTEND_N,
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IO_FX2_DATA => IO_FX2_DATA
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);
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end generate FX2_CNTL_IC;
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FX2_CNTL_IC3 : if sys_conf_fx2_type = "ic3" generate
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CNTL : fx2_3fifoctl_ic
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generic map (
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RXFAWIDTH => 5,
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TXFAWIDTH => 5,
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PETOWIDTH => sys_conf_fx2_petowidth,
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CCWIDTH => sys_conf_fx2_ccwidth,
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RXAEMPTY_THRES => 1,
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TXAFULL_THRES => 1,
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TX2AFULL_THRES => 1)
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port map (
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CLK => CLK,
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RESET => RESET,
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RXDATA => FX2_RXDATA,
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RXVAL => FX2_RXVAL,
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RXHOLD => FX2_RXHOLD,
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RXAEMPTY => FX2_RXAEMPTY,
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TXDATA => FX2_TXDATA,
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TXENA => FX2_TXENA,
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TXBUSY => FX2_TXBUSY,
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TXAFULL => FX2_TXAFULL,
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TX2DATA => FX2_TX2DATA,
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TX2ENA => FX2_TX2ENA,
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TX2BUSY => FX2_TX2BUSY,
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TX2AFULL => FX2_TX2AFULL,
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MONI => FX2_MONI,
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I_FX2_IFCLK => I_FX2_IFCLK,
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O_FX2_FIFO => O_FX2_FIFO,
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I_FX2_FLAG => I_FX2_FLAG,
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O_FX2_SLRD_N => O_FX2_SLRD_N,
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O_FX2_SLWR_N => O_FX2_SLWR_N,
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O_FX2_SLOE_N => O_FX2_SLOE_N,
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O_FX2_PKTEND_N => O_FX2_PKTEND_N,
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IO_FX2_DATA => IO_FX2_DATA
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);
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end generate FX2_CNTL_IC3;
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|
281 |
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TST : entity work.tst_rlink_cuff
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282 |
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port map (
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283 |
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CLK => CLK,
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284 |
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RESET => '0',
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285 |
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CE_USEC => CE_USEC,
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286 |
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CE_MSEC => CE_MSEC,
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RB_MREQ_TOP => RB_MREQ,
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288 |
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RB_SRES_TOP => RB_SRES_HIO,
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SWI => SWI,
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BTN => BTN(3 downto 0),
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LED => LED,
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292 |
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DSP_DAT => DSP_DAT,
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DSP_DP => DSP_DP,
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RXSD => RXSD,
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TXSD => TXSD,
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RTS_N => RTS_N,
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CTS_N => CTS_N,
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298 |
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FX2_RXDATA => FX2_RXDATA,
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FX2_RXVAL => FX2_RXVAL,
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FX2_RXHOLD => FX2_RXHOLD,
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FX2_TXDATA => FX2_TXDATA,
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FX2_TXENA => FX2_TXENA,
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FX2_TXBUSY => FX2_TXBUSY,
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FX2_TX2DATA => FX2_TX2DATA,
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FX2_TX2ENA => FX2_TX2ENA,
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FX2_TX2BUSY => FX2_TX2BUSY,
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307 |
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FX2_MONI => FX2_MONI
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308 |
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);
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309 |
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310 |
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end syn;
|
311 |
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