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-- $Id: sys_tst_sram_n3.vhd 791 2016-07-21 22:01:10Z mueller $
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--
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-- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: sys_tst_sram_n3 - syn
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-- Description: test of nexys3 sram and its controller
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--
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-- Dependencies: vlib/xlib/s6_cmt_sfs
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-- vlib/genlib/clkdivce
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-- bplib/bpgen/bp_rs232_2l4l_iob
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-- bplib/bpgen/sn_humanio
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-- vlib/rlink/rlink_sp1c
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-- tst_sram
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-- bplib/nxcramlib/nx_cram_memctl_as
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--
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-- Test bench: tb/tb_tst_sram_n3
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--
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-- Target Devices: generic
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-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.33
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--
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2014-12-20 614 14.7 131013 xc6slx16-2 922 1574 48 574 t 9.6 ns
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-- 2014-08-13 581 14.7 131013 xc6slx16-2 765 1261 32 441 t 9.6 ns
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-- 2011-12-21 442 13.4 O40d xc6slx16-2 722 1367 32 506 t 9.6 ns
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-- 2011-11-27 433 13.4 O40d xc6slx16-2 699 1194 20 406 t 8.9 ns
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2016-07-10 785 1.5.1 SWI(1) now XON; SWI(0) now portsel
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-- 2016-07-09 784 1.5 tst_sram with AWIDTH and 22bit support
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-- 2016-03-19 748 1.4.2 define rlink SYSID
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-- 2015-04-11 666 1.4.1 rearrange XON handling
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-- 2014-08-28 588 1.4 use new rlink v4 iface and 4 bit STAT
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-- 2014-08-15 583 1.3 rb_mreq addr now 16 bit
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-- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect
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-- 2011-12-21 442 1.1.1 use rlink_sp1c
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-- 2011-12-03 435 1.1 use int&ext serport and bp_rs232_2l4l_iob
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-- 2011-11-27 433 1.0 Initial version (derived from sys_tst_sram_n2)
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.xlib.all;
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use work.genlib.all;
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use work.serportlib.all;
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use work.rblib.all;
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use work.rlinklib.all;
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use work.bpgenlib.all;
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use work.s3boardlib.all;
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use work.nxcramlib.all;
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use work.sys_conf.all;
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-- ----------------------------------------------------------------------------
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entity sys_tst_sram_n3 is -- top level
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-- implements nexys3_fusp_aif
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port (
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I_CLK100 : in slbit; -- 100 MHz clock
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I_RXD : in slbit; -- receive data (board view)
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O_TXD : out slbit; -- transmit data (board view)
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I_SWI : in slv8; -- n3 switches
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I_BTN : in slv5; -- n3 buttons
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O_LED : out slv8; -- n3 leds
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O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
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O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
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O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
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O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
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O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
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O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
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O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
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O_MEM_CLK : out slbit; -- cram: clock
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O_MEM_CRE : out slbit; -- cram: command register enable
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I_MEM_WAIT : in slbit; -- cram: mem wait
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O_MEM_ADDR : out slv23; -- cram: address lines
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IO_MEM_DATA : inout slv16; -- cram: data lines
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O_PPCM_CE_N : out slbit; -- ppcm: ...
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O_PPCM_RST_N : out slbit; -- ppcm: ...
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O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
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I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
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I_FUSP_RXD : in slbit; -- fusp: rs232 rx
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O_FUSP_TXD : out slbit -- fusp: rs232 tx
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);
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end sys_tst_sram_n3;
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architecture syn of sys_tst_sram_n3 is
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signal CLK : slbit := '0';
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signal CE_USEC : slbit := '0';
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signal CE_MSEC : slbit := '0';
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signal GBL_RESET : slbit := '0';
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signal RXD : slbit := '1';
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signal TXD : slbit := '0';
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signal CTS_N : slbit := '0';
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signal RTS_N : slbit := '0';
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signal SWI : slv8 := (others=>'0');
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signal BTN : slv5 := (others=>'0');
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signal LED : slv8 := (others=>'0');
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signal DSP_DAT : slv16 := (others=>'0');
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signal DSP_DP : slv4 := (others=>'0');
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signal RB_MREQ : rb_mreq_type := rb_mreq_init;
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signal RB_SRES : rb_sres_type := rb_sres_init;
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signal RB_LAM : slv16 := (others=>'0');
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signal RB_STAT : slv4 := (others=>'0');
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signal SER_MONI : serport_moni_type := serport_moni_init;
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signal RB_SRES_TST : rb_sres_type := rb_sres_init;
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signal RB_LAM_TST : slbit := '0';
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signal MEM_RESET : slbit := '0';
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signal MEM_REQ : slbit := '0';
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signal MEM_WE : slbit := '0';
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signal MEM_BUSY : slbit := '0';
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signal MEM_ACK_R : slbit := '0';
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signal MEM_ACK_W : slbit := '0';
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signal MEM_ACT_R : slbit := '0';
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signal MEM_ACT_W : slbit := '0';
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signal MEM_ADDR : slv22 := (others=>'0');
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signal MEM_BE : slv4 := (others=>'0');
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signal MEM_DI : slv32 := (others=>'0');
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signal MEM_DO : slv32 := (others=>'0');
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constant sysid_proj : slv16 := x"0104"; -- tst_sram
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constant sysid_board : slv8 := x"03"; -- nexys3
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constant sysid_vers : slv8 := x"00";
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begin
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GEN_CLKSYS : s6_cmt_sfs
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generic map (
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VCO_DIVIDE => sys_conf_clksys_vcodivide,
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VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
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OUT_DIVIDE => sys_conf_clksys_outdivide,
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CLKIN_PERIOD => 10.0,
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CLKIN_JITTER => 0.01,
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STARTUP_WAIT => false,
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GEN_TYPE => sys_conf_clksys_gentype)
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port map (
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CLKIN => I_CLK100,
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CLKFX => CLK,
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LOCKED => open
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);
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CLKDIV : clkdivce
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generic map (
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CDUWIDTH => 7, -- good for up to 127 MHz !
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USECDIV => sys_conf_clksys_mhz,
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MSECDIV => 1000)
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port map (
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CLK => CLK,
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CE_USEC => CE_USEC,
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CE_MSEC => CE_MSEC
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);
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IOB_RS232 : bp_rs232_2l4l_iob
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port map (
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CLK => CLK,
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RESET => '0',
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SEL => SWI(0),
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RXD => RXD,
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TXD => TXD,
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CTS_N => CTS_N,
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RTS_N => RTS_N,
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I_RXD0 => I_RXD,
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O_TXD0 => O_TXD,
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I_RXD1 => I_FUSP_RXD,
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O_TXD1 => O_FUSP_TXD,
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I_CTS1_N => I_FUSP_CTS_N,
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O_RTS1_N => O_FUSP_RTS_N
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);
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HIO : sn_humanio
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generic map (
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BWIDTH => 5)
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port map (
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CLK => CLK,
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RESET => '0',
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CE_MSEC => CE_MSEC,
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SWI => SWI,
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BTN => BTN,
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LED => LED,
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DSP_DAT => DSP_DAT,
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DSP_DP => DSP_DP,
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I_SWI => I_SWI,
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I_BTN => I_BTN,
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O_LED => O_LED,
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O_ANO_N => O_ANO_N,
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O_SEG_N => O_SEG_N
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);
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RLINK : rlink_sp1c
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generic map (
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BTOWIDTH => 6, -- 64 cycles access timeout
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RTAWIDTH => 12,
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SYSID => sysid_proj & sysid_board & sysid_vers,
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IFAWIDTH => 5, -- 32 word input fifo
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OFAWIDTH => 5, -- 32 word output fifo
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ENAPIN_RLMON => sbcntl_sbf_rlmon,
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ENAPIN_RBMON => sbcntl_sbf_rbmon,
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CDWIDTH => 13,
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CDINIT => sys_conf_ser2rri_cdinit,
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RBMON_AWIDTH => 0,
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RBMON_RBADDR => x"ffe8")
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port map (
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CLK => CLK,
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CE_USEC => CE_USEC,
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CE_MSEC => CE_MSEC,
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CE_INT => CE_MSEC,
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RESET => GBL_RESET,
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ENAXON => SWI(1),
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ESCFILL => '0',
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RXSD => RXD,
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TXSD => TXD,
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CTS_N => CTS_N,
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RTS_N => RTS_N,
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RB_MREQ => RB_MREQ,
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RB_SRES => RB_SRES,
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RB_LAM => RB_LAM,
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RB_STAT => RB_STAT,
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RL_MONI => open,
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SER_MONI => SER_MONI
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);
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TST : entity work.tst_sram
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generic map (
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RB_ADDR => slv(to_unsigned(2#0000000000000000#,16)),
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AWIDTH => 22)
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port map (
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CLK => CLK,
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RESET => GBL_RESET,
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RB_MREQ => RB_MREQ,
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RB_SRES => RB_SRES_TST,
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RB_STAT => RB_STAT,
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RB_LAM => RB_LAM_TST,
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SWI => SWI,
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BTN => BTN(3 downto 0),
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LED => LED,
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DSP_DAT => DSP_DAT,
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MEM_RESET => MEM_RESET,
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MEM_REQ => MEM_REQ,
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MEM_WE => MEM_WE,
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MEM_BUSY => MEM_BUSY,
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MEM_ACK_R => MEM_ACK_R,
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MEM_ACK_W => MEM_ACK_W,
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MEM_ACT_R => MEM_ACT_R,
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MEM_ACT_W => MEM_ACT_W,
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MEM_ADDR => MEM_ADDR,
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MEM_BE => MEM_BE,
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MEM_DI => MEM_DI,
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MEM_DO => MEM_DO
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);
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CRAMCTL : nx_cram_memctl_as
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generic map (
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READ0DELAY => sys_conf_memctl_read0delay, -- was 2 for 50 MHz
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READ1DELAY => sys_conf_memctl_read1delay, -- was 2 "
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WRITEDELAY => sys_conf_memctl_writedelay) -- was 3 "
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port map (
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CLK => CLK,
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RESET => MEM_RESET,
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REQ => MEM_REQ,
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WE => MEM_WE,
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BUSY => MEM_BUSY,
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ACK_R => MEM_ACK_R,
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ACK_W => MEM_ACK_W,
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ACT_R => MEM_ACT_R,
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ACT_W => MEM_ACT_W,
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ADDR => MEM_ADDR,
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BE => MEM_BE,
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DI => MEM_DI,
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DO => MEM_DO,
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O_MEM_CE_N => O_MEM_CE_N,
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O_MEM_BE_N => O_MEM_BE_N,
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O_MEM_WE_N => O_MEM_WE_N,
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O_MEM_OE_N => O_MEM_OE_N,
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O_MEM_ADV_N => O_MEM_ADV_N,
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O_MEM_CLK => O_MEM_CLK,
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O_MEM_CRE => O_MEM_CRE,
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I_MEM_WAIT => I_MEM_WAIT,
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O_MEM_ADDR => O_MEM_ADDR,
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IO_MEM_DATA => IO_MEM_DATA
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);
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O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
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O_PPCM_RST_N <= '1'; --
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RB_SRES <= RB_SRES_TST; -- can be sres_or later...
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RB_LAM(0) <= RB_LAM_TST;
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DSP_DP(3) <= not SER_MONI.txok;
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DSP_DP(2) <= SER_MONI.txact;
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DSP_DP(1) <= not SER_MONI.rxok;
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DSP_DP(0) <= SER_MONI.rxact;
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end syn;
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315 |
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