URL https://opencores.org/ocsvn/w11/w11/trunk

Subversion Repositories w11

[/] [w11/] [tags/] [w11a_V0.74/] [rtl/] [sys_gen/] [tst_sram/] [tst_sram.vbom] - Blame information for rev 37

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# libs
../../vlib/slvtypes.vhd
../../vlib/memlib/memlib.vhd
../../vlib/rbus/rblib.vhd
${sys_conf}
# components
[sim]../../vlib/memlib/ram_1swsr_wfirst_gen.vbom
[sim]../../vlib/memlib/ram_2swsr_wfirst_gen.vbom
[xst]../../vlib/memlib/ram_1swsr_wfirst_gen_unisim.vbom
[vsyn]../../vlib/memlib/ram_1swsr_wfirst_gen.vbom
[xst]../../vlib/memlib/ram_2swsr_wfirst_gen_unisim.vbom
[vsyn]../../vlib/memlib/ram_2swsr_wfirst_gen.vbom
# design
tst_sram.vhd

Line No.	Rev	Author	Line
1	37	wfjm	`# libs`
2			`../../vlib/slvtypes.vhd`
3			`../../vlib/memlib/memlib.vhd`
4			`../../vlib/rbus/rblib.vhd`
5			`${sys_conf}`
6			`# components`
7			`[sim]../../vlib/memlib/ram_1swsr_wfirst_gen.vbom`
8			`[sim]../../vlib/memlib/ram_2swsr_wfirst_gen.vbom`
9			`[xst]../../vlib/memlib/ram_1swsr_wfirst_gen_unisim.vbom`
10			`[vsyn]../../vlib/memlib/ram_1swsr_wfirst_gen.vbom`
11			`[xst]../../vlib/memlib/ram_2swsr_wfirst_gen_unisim.vbom`
12			`[vsyn]../../vlib/memlib/ram_2swsr_wfirst_gen.vbom`
13			`# design`
14			`tst_sram.vhd`

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Subversion Repositories w11

[/] [w11/] [tags/] [w11a_V0.74/] [rtl/] [sys_gen/] [tst_sram/] [tst_sram.vbom] - Blame information for rev 37