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## $Id: sys_w11a_n4.ucf_cpp 643 2015-02-07 17:41:53Z mueller $

##

## Revision History:

## Date         Rev Version  Comment

## 2013-10-13   540   1.1    add pad->clk constraints

## 2013-09-22   534   1.0    Initial version

##

NET "I_CLK100" TNM_NET = "I_CLK100";

TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %;

OFFSET =  IN 10 ns BEFORE "I_CLK100";

OFFSET = OUT 20 ns  AFTER "I_CLK100";

## constrain pad->net clock delay

NET CLK TNM = TNM_CLK;

TIMESPEC TS_PAD_CLK=FROM PADS(I_CLK100) TO TNM_CLK 10 ns;

## std board

##

#include "bplib/nexys4/nexys4_pins.ucf"

#include "bplib/nexys4/nexys4_pins_cram.ucf"