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-- $Id: sys_w11a_s3.vhd 677 2015-05-09 21:52:32Z mueller $
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--
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-- Copyright 2007-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: sys_w11a_s3 - syn
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-- Description: w11a test design for s3board
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--
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-- Dependencies: vlib/genlib/clkdivce
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-- bplib/bpgen/bp_rs232_2l4l_iob
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-- vlib/rlink/rlink_sp1c
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-- w11a/pdp11_sys70
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-- ibus/ibdr_maxisys
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-- bplib/s3board/s3_sram_memctl
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-- vlib/rlink/ioleds_sp1c
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-- w11a/pdp11_hio70
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-- bplib/bpgen/sn_humanio_rbus
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-- vlib/rbus/rb_sres_or_2
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--
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-- Test bench: tb/tb_sys_w11a_s3
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--
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-- Target Devices: generic
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-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
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--
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2015-05-02 673 14.7 131013 xc3s1000-4 2054 6196 350 3858 OK: +RHRP 50%
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-- 2015-02-21 649 14.7 131013 xc3s1000-4 1643 5124 318 3176 OK: +RL11
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-- 2014-12-22 619 14.7 131013 xc3s1000-4 1569 4768 302 2994 OK: +rbmon
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-- 2014-12-20 614 14.7 131013 xc3s1000-4 1455 4523 302 2807 OK: -RL11,rlv4
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-- 2014-06-08 561 14.7 131013 xc3s1000-4 1374 4580 286 2776 OK: +RL11
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-- 2014-06-01 558 14.7 131013 xc3s1000-4 1301 4306 270 2614 OK:
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-- 2011-12-21 442 13.1 O40d xc3s1000-4 1301 4307 270 2613 OK: LP+PC+DL+II
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-- 2011-11-19 427 13.1 O40d xc3s1000-4 1322 4298 242 2616 OK: LP+PC+DL+II
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-- 2010-12-30 351 12.1 M53d xc3s1000-4 1316 4291 242 2609 OK: LP+PC+DL+II
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-- 2010-11-06 336 12.1 M53d xc3s1000-4 1284 4253* 242 2575 OK: LP+PC+DL+II
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-- 2010-10-24 335 12.1 M53d xc3s1000-4 1284 4495 242 2575 OK: LP+PC+DL+II
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-- 2010-05-01 285 11.4 L68 xc3s1000-4 1239 4086 224 2471 OK: LP+PC+DL+II
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-- 2010-04-26 283 11.4 L68 xc3s1000-4 1245 4083 224 2474 OK: LP+PC+DL+II
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-- 2009-07-12 233 11.2 L46 xc3s1000-4 1245 4078 224 2472 OK: LP+PC+DL+II
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-- 2009-07-12 233 10.1.03 K39 xc3s1000-4 1250 4097 224 2494 OK: LP+PC+DL+II
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-- 2009-06-01 221 10.1.03 K39 xc3s1000-4 1209 3986 224 2425 OK: LP+PC+DL+II
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-- 2009-05-17 216 10.1.03 K39 xc3s1000-4 1039 3542 224 2116 m+p; TIME OK
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-- 2009-05-09 213 10.1.03 K39 xc3s1000-4 1037 3500 224 2100 m+p; TIME OK
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-- 2009-04-26 209 8.2.03 I34 xc3s1000-4 1099 3557 224 2264 m+p; TIME OK
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-- 2008-12-13 176 8.2.03 I34 xc3s1000-4 1116 3672 224 2280 m+p; TIME OK
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-- 2008-12-06 174 10.1.02 K37 xc3s1000-4 1038 3503 224 2100 m+p; TIME OK
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-- 2008-12-06 174 8.2.03 I34 xc3s1000-4 1116 3682 224 2281 m+p; TIME OK
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-- 2008-08-22 161 8.2.03 I34 xc3s1000-4 1118 3677 224 2288 m+p; TIME OK
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-- 2008-08-22 161 10.1.02 K37 xc3s1000-4 1035 3488 224 2086 m+p; TIME OK
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-- 2008-05-01 140 8.2.03 I34 xc3s1000-4 1057 3344 224 2119 m+p; 21ns;BR-32
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-- 2008-05-01 140 8.2.03 I34 xc3s1000-4 1057 3357 224 2128 m+p; 21ns;BR-16
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-- 2008-05-01 140 8.2.03 I34 xc3s1000-4 1057 3509 224 2220 m+p; TIME OK
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-- 2008-05-01 140 9.2.04 J40 xc3s200-4 1009 3195 224 1918 m+p; T-OK;BR-16
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-- 2008-03-19 127 8.2.03 I34 xc3s1000-4 1077 3471 224 2207 m+p; TIME OK
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-- 2008-03-02 122 8.2.03 I34 xc3s1000-4 1068 3448 224 2179 m+p; TIME OK
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-- 2008-03-02 121 8.2.03 I34 xc3s1000-4 1064 3418 224 2148 m+p; TIME FAIL
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-- 2008-02-24 119 8.2.03 I34 xc3s1000-4 1071 3372 224 2141 m+p; TIME OK
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-- 2008-02-23 118 8.2.03 I34 xc3s1000-4 1035 3301 182 1996 m+p; TIME OK
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-- 2008-01-06 111 8.2.03 I34 xc3s1000-4 971 2898 182 1831 m+p; TIME OK
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-- 2007-12-30 107 8.2.03 I34 xc3s1000-4 891 2719 137 1515 s 18.8
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-- 2007-12-30 107 8.2.03 I34 xc3s1000-4 891 2661 137 1654 m+p; TIME OK
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-- Note: till 2010-10-24 lutm included 'route-thru', after only logic
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul
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-- 2015-05-02 673 2.0 use pdp11_sys70 and pdp11_hio70; now in std form
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-- 2015-04-11 666 1.7.1 rearrange XON handling
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-- 2015-02-21 649 1.7 use ioleds_sp1c,pdp11_(statleds,ledmux,dspmux)
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-- 2014-12-24 620 1.6.2 relocate ibus window and hio rbus address
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-- 2014-12-22 619 1.6.1 add rbus monitor rbd_rbmon
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-- 2014-08-28 588 1.6 use new rlink v4 iface and 4 bit STAT
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-- 2014-08-15 583 1.5 rb_mreq addr now 16 bit
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-- 2011-12-21 442 1.4.4 use rlink_sp1c; hio led usage now a for n2/n3
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-- 2011-11-19 427 1.4.3 now numeric_std clean
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-- 2011-07-09 391 1.4.2 use now bp_rs232_2l4l_iob
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-- 2011-07-08 390 1.4.1 use now sn_humanio
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-- 2010-12-30 351 1.4 ported to rbv3
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-- 2010-11-06 336 1.3.7 rename input pin CLK -> I_CLK50
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-- 2010-10-23 335 1.3.3 rename RRI_LAM->RB_LAM;
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-- 2010-06-26 309 1.3.2 use constants for rbus addresses (rbaddr_...)
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-- 2010-06-18 306 1.3.1 rename RB_ADDR->RB_ADDR_CORE, add RB_ADDR_IBUS;
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-- remove pdp11_ibdr_rri
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-- 2010-06-13 305 1.6.1 add CP_ADDR, wire up pdp11_core_rri->pdp11_core
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-- 2010-06-11 303 1.6 use IB_MREQ.racc instead of RRI_REQ
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-- 2010-06-03 300 1.5.6 use default FAWIDTH for rri_core_serport
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-- 2010-05-28 295 1.5.5 rename sys_pdp11core -> sys_w11a_s3
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-- 2010-05-21 292 1.5.4 rename _PM1_ -> _FUSP_
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-- 2010-05-16 291 1.5.3 rename memctl_s3sram->s3_sram_memctl
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-- 2010-05-05 288 1.5.2 add sys_conf_hio_debounce
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-- 2010-05-02 287 1.5.1 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
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-- drop RP_IINT from interfaces; drop RTSFLUSH generic
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-- add pm1 rs232 (usp) support
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-- 2010-05-01 285 1.5 port to rri V2 interface, use rri_core_serport
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-- 2010-04-17 278 1.4.5 rename sram_dummy -> s3_sram_dummy
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-- 2010-04-10 275 1.4.4 use s3_humanio; invert DP(1,3)
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-- 2009-07-12 233 1.4.3 adapt to ibdr_(mini|maxi)sys interface changes
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-- 2009-06-01 221 1.4.2 support ibdr_maxisys as well as _minisys
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-- 2009-05-10 214 1.4.1 use pdp11_tmu_sb instead of pdp11_tmu
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-- 2008-08-22 161 1.4.0 use iblib, ibdlib; renames
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-- 2008-05-03 143 1.3.6 rename _cpursta->_cpurust
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-- 2008-05-01 142 1.3.5 reassign LED(cpugo,halt,rust) and DISP(dispreg)
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-- 2008-04-19 137 1.3.4 add DM_STAT_(DP|VM|CO|SY) signals, add pdp11_tmu
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-- 2008-04-18 136 1.3.3 add RESET for ibdr_minisys
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-- 2008-04-13 135 1.3.2 add _mem70 also for _bram configs
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-- 2008-02-23 118 1.3.1 add _mem70
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-- 2008-02-17 117 1.3 use ext. memory interface of _core;
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-- use _cache + memctl or _bram (configurable)
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-- 2008-01-20 113 1.2.1 finalize AP_LAM handling (0=cpu,1=dl11;4=rk05)
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-- 2008-01-20 112 1.2 rename clkgen->clkdivce; use ibdr_minisys, BRESET
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-- add _ib_mux2
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-- 2008-01-06 111 1.1 use now iob_reg_*; remove rricp_pdp11core hack
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-- instanciate all parts directly
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-- 2007-12-23 105 1.0.4 add rritb_cpmon_sb
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-- 2007-12-16 101 1.0.3 use _N for active low; set IOB attribute to RI/RO
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-- 2007-12-09 100 1.0.2 add sram memory signals, dummy handle them
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-- 2007-10-19 90 1.0.1 init RI_RXD,RO_TXD=1 to avoid startup glitch
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-- 2007-09-23 84 1.0 Initial version
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------------------------------------------------------------------------------
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--
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-- w11a test design for s3board
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-- w11a + rlink + serport
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--
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-- Usage of S3BOARD Switches, Buttons, LEDs:
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--
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-- SWI(7:6): no function (only connected to sn_humanio_rbus)
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-- (5:4): select DSP
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-- 00 abclkdiv & abclkdiv_f
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-- 01 PC
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-- 10 DISPREG
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-- 11 DR emulation
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-- (3): select LED display
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-- 0 overall status
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-- 1 DR emulation
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-- (2) 0 -> int/ext RS242 port for rlink
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-- 1 -> use USB interface for rlink
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-- (1): 1 enable XON
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-- (0): 0 -> main board RS232 port
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-- 1 -> Pmod B/top RS232 port
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--
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-- LEDs if SWI(3) = 1
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-- (7:0) DR emulation; shows R0(lower 8 bits) during wait like 11/45+70
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--
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-- LEDs if SWI(3) = 0
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-- (7) MEM_ACT_W
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-- (6) MEM_ACT_R
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-- (5) cmdbusy (all rlink access, mostly rdma)
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-- (4:0) if cpugo=1 show cpu mode activity
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-- (4) kernel mode, pri>0
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-- (3) kernel mode, pri=0
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-- (2) kernel mode, wait
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-- (1) supervisor mode
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-- (0) user mode
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-- if cpugo=0 shows cpurust
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-- (4) '1'
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-- (3:0) cpurust code
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--
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-- DP(3): not SER_MONI.txok (shows tx back preasure)
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-- DP(2): SER_MONI.txact (shows tx activity)
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-- DP(1): not SER_MONI.rxok (shows rx back preasure)
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-- DP(0): SER_MONI.rxact (shows rx activity)
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.genlib.all;
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use work.serportlib.all;
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use work.rblib.all;
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use work.rlinklib.all;
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use work.bpgenlib.all;
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use work.bpgenrbuslib.all;
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use work.s3boardlib.all;
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use work.iblib.all;
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use work.ibdlib.all;
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use work.pdp11.all;
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use work.sys_conf.all;
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-- ----------------------------------------------------------------------------
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entity sys_w11a_s3 is -- top level
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-- implements s3board_fusp_aif
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port (
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I_CLK50 : in slbit; -- 50 MHz board clock
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I_RXD : in slbit; -- receive data (board view)
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O_TXD : out slbit; -- transmit data (board view)
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I_SWI : in slv8; -- s3 switches
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I_BTN : in slv4; -- s3 buttons
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O_LED : out slv8; -- s3 leds
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O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
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O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
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O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
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O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
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O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
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O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
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O_MEM_ADDR : out slv18; -- sram: address lines
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IO_MEM_DATA : inout slv32; -- sram: data lines
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O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
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I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
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I_FUSP_RXD : in slbit; -- fusp: rs232 rx
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O_FUSP_TXD : out slbit -- fusp: rs232 tx
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);
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end sys_w11a_s3;
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217 |
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architecture syn of sys_w11a_s3 is
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219 |
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signal CLK : slbit := '0';
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signal RESET : slbit := '0';
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signal CE_USEC : slbit := '0';
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signal CE_MSEC : slbit := '0';
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224 |
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signal RXD : slbit := '1';
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signal TXD : slbit := '0';
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signal RTS_N : slbit := '0';
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signal CTS_N : slbit := '0';
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signal RB_MREQ : rb_mreq_type := rb_mreq_init;
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signal RB_SRES : rb_sres_type := rb_sres_init;
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signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
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signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
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signal RB_LAM : slv16 := (others=>'0');
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signal RB_STAT : slv4 := (others=>'0');
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signal SER_MONI : serport_moni_type := serport_moni_init;
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signal SWI : slv8 := (others=>'0');
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signal BTN : slv4 := (others=>'0');
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signal LED : slv8 := (others=>'0');
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signal DSP_DAT : slv16 := (others=>'0');
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signal DSP_DP : slv4 := (others=>'0');
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signal GRESET : slbit := '0'; -- general reset (from rbus)
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signal CRESET : slbit := '0'; -- cpu reset (from cp)
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248 |
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signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
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249 |
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signal ITIMER : slbit := '0';
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signal EI_PRI : slv3 := (others=>'0');
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252 |
|
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signal EI_VECT : slv9_2 := (others=>'0');
|
253 |
|
|
signal EI_ACKM : slbit := '0';
|
254 |
30 |
wfjm |
|
255 |
|
|
signal CP_STAT : cp_stat_type := cp_stat_init;
|
256 |
|
|
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
|
257 |
2 |
wfjm |
|
258 |
|
|
signal MEM_REQ : slbit := '0';
|
259 |
|
|
signal MEM_WE : slbit := '0';
|
260 |
|
|
signal MEM_BUSY : slbit := '0';
|
261 |
|
|
signal MEM_ACK_R : slbit := '0';
|
262 |
16 |
wfjm |
signal MEM_ACT_R : slbit := '0';
|
263 |
|
|
signal MEM_ACT_W : slbit := '0';
|
264 |
2 |
wfjm |
signal MEM_ADDR : slv20 := (others=>'0');
|
265 |
|
|
signal MEM_BE : slv4 := (others=>'0');
|
266 |
|
|
signal MEM_DI : slv32 := (others=>'0');
|
267 |
|
|
signal MEM_DO : slv32 := (others=>'0');
|
268 |
|
|
|
269 |
|
|
signal IB_MREQ : ib_mreq_type := ib_mreq_init;
|
270 |
|
|
signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
|
271 |
|
|
|
272 |
|
|
signal DISPREG : slv16 := (others=>'0');
|
273 |
29 |
wfjm |
signal STATLEDS : slv8 := (others=>'0');
|
274 |
|
|
signal ABCLKDIV : slv16 := (others=>'0');
|
275 |
2 |
wfjm |
|
276 |
28 |
wfjm |
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx
|
277 |
|
|
constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0004: 1111 1110 1111 00xx
|
278 |
2 |
wfjm |
|
279 |
|
|
begin
|
280 |
|
|
|
281 |
8 |
wfjm |
CLK <= I_CLK50; -- use 50MHz as system clock
|
282 |
|
|
|
283 |
30 |
wfjm |
CLKDIV : clkdivce -- usec/msec clock divider -----------
|
284 |
2 |
wfjm |
generic map (
|
285 |
|
|
CDUWIDTH => 6,
|
286 |
|
|
USECDIV => 50,
|
287 |
|
|
MSECDIV => 1000)
|
288 |
|
|
port map (
|
289 |
|
|
CLK => CLK,
|
290 |
|
|
CE_USEC => CE_USEC,
|
291 |
|
|
CE_MSEC => CE_MSEC
|
292 |
|
|
);
|
293 |
|
|
|
294 |
30 |
wfjm |
IOB_RS232 : bp_rs232_2l4l_iob -- serport iob/switch ----------------
|
295 |
2 |
wfjm |
port map (
|
296 |
|
|
CLK => CLK,
|
297 |
12 |
wfjm |
RESET => '0',
|
298 |
2 |
wfjm |
SEL => SWI(0),
|
299 |
|
|
RXD => RXD,
|
300 |
|
|
TXD => TXD,
|
301 |
|
|
CTS_N => CTS_N,
|
302 |
|
|
RTS_N => RTS_N,
|
303 |
|
|
I_RXD0 => I_RXD,
|
304 |
|
|
O_TXD0 => O_TXD,
|
305 |
|
|
I_RXD1 => I_FUSP_RXD,
|
306 |
|
|
O_TXD1 => O_FUSP_TXD,
|
307 |
|
|
I_CTS1_N => I_FUSP_CTS_N,
|
308 |
|
|
O_RTS1_N => O_FUSP_RTS_N
|
309 |
|
|
);
|
310 |
|
|
|
311 |
30 |
wfjm |
RLINK : rlink_sp1c -- rlink for serport -----------------
|
312 |
2 |
wfjm |
generic map (
|
313 |
27 |
wfjm |
BTOWIDTH => 6, -- 64 cycles access timeout
|
314 |
|
|
RTAWIDTH => 12,
|
315 |
|
|
SYSID => (others=>'0'),
|
316 |
16 |
wfjm |
IFAWIDTH => 5, -- 32 word input fifo
|
317 |
|
|
OFAWIDTH => 5, -- 32 word output fifo
|
318 |
|
|
ENAPIN_RLMON => sbcntl_sbf_rlmon,
|
319 |
|
|
ENAPIN_RBMON => sbcntl_sbf_rbmon,
|
320 |
|
|
CDWIDTH => 13,
|
321 |
30 |
wfjm |
CDINIT => sys_conf_ser2rri_cdinit,
|
322 |
|
|
RBMON_AWIDTH => sys_conf_rbmon_awidth,
|
323 |
|
|
RBMON_RBADDR => rbaddr_rbmon)
|
324 |
2 |
wfjm |
port map (
|
325 |
|
|
CLK => CLK,
|
326 |
|
|
CE_USEC => CE_USEC,
|
327 |
|
|
CE_MSEC => CE_MSEC,
|
328 |
|
|
CE_INT => CE_MSEC,
|
329 |
|
|
RESET => RESET,
|
330 |
16 |
wfjm |
ENAXON => SWI(1),
|
331 |
30 |
wfjm |
ESCFILL => '0',
|
332 |
2 |
wfjm |
RXSD => RXD,
|
333 |
|
|
TXSD => TXD,
|
334 |
|
|
CTS_N => CTS_N,
|
335 |
|
|
RTS_N => RTS_N,
|
336 |
|
|
RB_MREQ => RB_MREQ,
|
337 |
|
|
RB_SRES => RB_SRES,
|
338 |
|
|
RB_LAM => RB_LAM,
|
339 |
9 |
wfjm |
RB_STAT => RB_STAT,
|
340 |
|
|
RL_MONI => open,
|
341 |
16 |
wfjm |
SER_MONI => SER_MONI
|
342 |
2 |
wfjm |
);
|
343 |
16 |
wfjm |
|
344 |
30 |
wfjm |
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
|
345 |
2 |
wfjm |
port map (
|
346 |
30 |
wfjm |
CLK => CLK,
|
347 |
|
|
RESET => RESET,
|
348 |
|
|
RB_MREQ => RB_MREQ,
|
349 |
|
|
RB_SRES => RB_SRES_CPU,
|
350 |
|
|
RB_STAT => RB_STAT,
|
351 |
|
|
RB_LAM_CPU => RB_LAM(0),
|
352 |
|
|
GRESET => GRESET,
|
353 |
|
|
CRESET => CRESET,
|
354 |
|
|
BRESET => BRESET,
|
355 |
|
|
CP_STAT => CP_STAT,
|
356 |
|
|
EI_PRI => EI_PRI,
|
357 |
|
|
EI_VECT => EI_VECT,
|
358 |
|
|
EI_ACKM => EI_ACKM,
|
359 |
|
|
ITIMER => ITIMER,
|
360 |
|
|
IB_MREQ => IB_MREQ,
|
361 |
|
|
IB_SRES => IB_SRES_IBDR,
|
362 |
|
|
MEM_REQ => MEM_REQ,
|
363 |
|
|
MEM_WE => MEM_WE,
|
364 |
|
|
MEM_BUSY => MEM_BUSY,
|
365 |
|
|
MEM_ACK_R => MEM_ACK_R,
|
366 |
|
|
MEM_ADDR => MEM_ADDR,
|
367 |
|
|
MEM_BE => MEM_BE,
|
368 |
|
|
MEM_DI => MEM_DI,
|
369 |
|
|
MEM_DO => MEM_DO,
|
370 |
|
|
DM_STAT_DP => DM_STAT_DP
|
371 |
2 |
wfjm |
);
|
372 |
30 |
wfjm |
|
373 |
|
|
IBDR_SYS : ibdr_maxisys -- IO system -------------------------
|
374 |
|
|
port map (
|
375 |
|
|
CLK => CLK,
|
376 |
|
|
CE_USEC => CE_USEC,
|
377 |
|
|
CE_MSEC => CE_MSEC,
|
378 |
|
|
RESET => GRESET,
|
379 |
|
|
BRESET => BRESET,
|
380 |
|
|
ITIMER => ITIMER,
|
381 |
|
|
CPUSUSP => CP_STAT.cpususp,
|
382 |
|
|
RB_LAM => RB_LAM(15 downto 1),
|
383 |
|
|
IB_MREQ => IB_MREQ,
|
384 |
|
|
IB_SRES => IB_SRES_IBDR,
|
385 |
|
|
EI_ACKM => EI_ACKM,
|
386 |
|
|
EI_PRI => EI_PRI,
|
387 |
|
|
EI_VECT => EI_VECT,
|
388 |
|
|
DISPREG => DISPREG);
|
389 |
28 |
wfjm |
|
390 |
30 |
wfjm |
SRAM_CTL: s3_sram_memctl -- memory controller -----------------
|
391 |
2 |
wfjm |
port map (
|
392 |
30 |
wfjm |
CLK => CLK,
|
393 |
|
|
RESET => GRESET,
|
394 |
|
|
REQ => MEM_REQ,
|
395 |
|
|
WE => MEM_WE,
|
396 |
|
|
BUSY => MEM_BUSY,
|
397 |
|
|
ACK_R => MEM_ACK_R,
|
398 |
|
|
ACK_W => open,
|
399 |
|
|
ACT_R => MEM_ACT_R,
|
400 |
|
|
ACT_W => MEM_ACT_W,
|
401 |
|
|
ADDR => MEM_ADDR(17 downto 0),
|
402 |
|
|
BE => MEM_BE,
|
403 |
|
|
DI => MEM_DI,
|
404 |
|
|
DO => MEM_DO,
|
405 |
|
|
O_MEM_CE_N => O_MEM_CE_N,
|
406 |
|
|
O_MEM_BE_N => O_MEM_BE_N,
|
407 |
|
|
O_MEM_WE_N => O_MEM_WE_N,
|
408 |
|
|
O_MEM_OE_N => O_MEM_OE_N,
|
409 |
|
|
O_MEM_ADDR => O_MEM_ADDR,
|
410 |
|
|
IO_MEM_DATA => IO_MEM_DATA
|
411 |
2 |
wfjm |
);
|
412 |
|
|
|
413 |
30 |
wfjm |
LED_IO : ioleds_sp1c -- hio leds from serport -------------
|
414 |
2 |
wfjm |
port map (
|
415 |
29 |
wfjm |
SER_MONI => SER_MONI,
|
416 |
|
|
IOLEDS => DSP_DP
|
417 |
|
|
);
|
418 |
|
|
|
419 |
30 |
wfjm |
ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f;
|
420 |
|
|
|
421 |
|
|
HIO70 : pdp11_hio70 -- hio from sys70 --------------------
|
422 |
|
|
generic map (
|
423 |
|
|
LWIDTH => LED'length,
|
424 |
|
|
DCWIDTH => 2)
|
425 |
29 |
wfjm |
port map (
|
426 |
30 |
wfjm |
SEL_LED => SWI(3),
|
427 |
|
|
SEL_DSP => SWI(5 downto 4),
|
428 |
29 |
wfjm |
MEM_ACT_R => MEM_ACT_R,
|
429 |
|
|
MEM_ACT_W => MEM_ACT_W,
|
430 |
|
|
CP_STAT => CP_STAT,
|
431 |
|
|
DM_STAT_DP => DM_STAT_DP,
|
432 |
30 |
wfjm |
ABCLKDIV => ABCLKDIV,
|
433 |
|
|
DISPREG => DISPREG,
|
434 |
|
|
LED => LED,
|
435 |
|
|
DSP_DAT => DSP_DAT
|
436 |
29 |
wfjm |
);
|
437 |
30 |
wfjm |
|
438 |
|
|
HIO : sn_humanio_rbus -- hio manager -----------------------
|
439 |
29 |
wfjm |
generic map (
|
440 |
30 |
wfjm |
DEBOUNCE => sys_conf_hio_debounce,
|
441 |
|
|
RB_ADDR => rbaddr_hio)
|
442 |
29 |
wfjm |
port map (
|
443 |
30 |
wfjm |
CLK => CLK,
|
444 |
|
|
RESET => RESET,
|
445 |
|
|
CE_MSEC => CE_MSEC,
|
446 |
|
|
RB_MREQ => RB_MREQ,
|
447 |
|
|
RB_SRES => RB_SRES_HIO,
|
448 |
|
|
SWI => SWI,
|
449 |
|
|
BTN => BTN,
|
450 |
|
|
LED => LED,
|
451 |
|
|
DSP_DAT => DSP_DAT,
|
452 |
|
|
DSP_DP => DSP_DP,
|
453 |
|
|
I_SWI => I_SWI,
|
454 |
|
|
I_BTN => I_BTN,
|
455 |
|
|
O_LED => O_LED,
|
456 |
|
|
O_ANO_N => O_ANO_N,
|
457 |
|
|
O_SEG_N => O_SEG_N
|
458 |
29 |
wfjm |
);
|
459 |
16 |
wfjm |
|
460 |
30 |
wfjm |
RB_SRES_OR : rb_sres_or_2 -- rbus or ---------------------------
|
461 |
29 |
wfjm |
port map (
|
462 |
30 |
wfjm |
RB_SRES_1 => RB_SRES_CPU,
|
463 |
|
|
RB_SRES_2 => RB_SRES_HIO,
|
464 |
|
|
RB_SRES_OR => RB_SRES
|
465 |
29 |
wfjm |
);
|
466 |
30 |
wfjm |
|
467 |
2 |
wfjm |
end syn;
|