1 |
36 |
wfjm |
-- $Id: cdclib.vhd 774 2016-06-12 17:08:47Z mueller $
|
2 |
|
|
--
|
3 |
|
|
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
4 |
|
|
--
|
5 |
|
|
-- This program is free software; you may redistribute and/or modify it under
|
6 |
|
|
-- the terms of the GNU General Public License as published by the Free
|
7 |
|
|
-- Software Foundation, either version 2, or at your option any later version.
|
8 |
|
|
--
|
9 |
|
|
-- This program is distributed in the hope that it will be useful, but
|
10 |
|
|
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
|
11 |
|
|
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
12 |
|
|
-- for complete details.
|
13 |
|
|
--
|
14 |
|
|
------------------------------------------------------------------------------
|
15 |
|
|
-- Package Name: cdclib
|
16 |
|
|
-- Description: clock domain crossing components
|
17 |
|
|
--
|
18 |
|
|
-- Dependencies: -
|
19 |
|
|
-- Tool versions: viv 2016.1-2016.2; ghdl 0.33
|
20 |
|
|
-- Revision History:
|
21 |
|
|
-- Date Rev Version Comment
|
22 |
|
|
-- 2016-06-11 774 1.0.1 add cdc_signal_s1_as; add INIT generic
|
23 |
|
|
-- 2016-04-02 757 1.0 Initial version
|
24 |
|
|
------------------------------------------------------------------------------
|
25 |
|
|
|
26 |
|
|
library ieee;
|
27 |
|
|
use ieee.std_logic_1164.all;
|
28 |
|
|
|
29 |
|
|
use work.slvtypes.all;
|
30 |
|
|
|
31 |
|
|
package cdclib is
|
32 |
|
|
|
33 |
|
|
component cdc_signal_s1 is -- cdc for signal (2 stage)
|
34 |
|
|
generic (
|
35 |
|
|
INIT : slbit := '0'); -- initial state
|
36 |
|
|
port (
|
37 |
|
|
CLKO : in slbit; -- O|output clock
|
38 |
|
|
DI : in slbit; -- I|input data
|
39 |
|
|
DO : out slbit -- O|output data
|
40 |
|
|
);
|
41 |
|
|
end component;
|
42 |
|
|
|
43 |
|
|
component cdc_signal_s1_as is -- cdc for signal (2 stage), asyn input
|
44 |
|
|
generic (
|
45 |
|
|
INIT : slbit := '0'); -- initial state
|
46 |
|
|
port (
|
47 |
|
|
CLKO : in slbit; -- O|output clock
|
48 |
|
|
DI : in slbit; -- I|input data
|
49 |
|
|
DO : out slbit -- O|output data
|
50 |
|
|
);
|
51 |
|
|
end component;
|
52 |
|
|
|
53 |
|
|
component cdc_vector_s0 is -- cdc for vector (1 stage)
|
54 |
|
|
generic (
|
55 |
|
|
DWIDTH : positive := 16); -- data port width
|
56 |
|
|
port (
|
57 |
|
|
CLKO : in slbit; -- O|output clock
|
58 |
|
|
DI : in slv(DWIDTH-1 downto 0); -- I|input data
|
59 |
|
|
DO : out slv(DWIDTH-1 downto 0) -- O|output data
|
60 |
|
|
);
|
61 |
|
|
end component;
|
62 |
|
|
|
63 |
|
|
component cdc_vector_s1 is -- cdc for vector (2 stage)
|
64 |
|
|
generic (
|
65 |
|
|
DWIDTH : positive := 16); -- data port width
|
66 |
|
|
port (
|
67 |
|
|
CLKO : in slbit; -- O|output clock
|
68 |
|
|
DI : in slv(DWIDTH-1 downto 0); -- I|input data
|
69 |
|
|
DO : out slv(DWIDTH-1 downto 0) -- O|output data
|
70 |
|
|
);
|
71 |
|
|
end component;
|
72 |
|
|
|
73 |
|
|
component cdc_pulse is -- clock domain crossing for a pulse
|
74 |
|
|
generic (
|
75 |
|
|
POUT_SINGLE : boolean := false; -- if true: single cycle pout
|
76 |
|
|
BUSY_WACK : boolean := false; -- if true: busy waits for ack
|
77 |
|
|
INIT : slbit := '0'); -- initial state
|
78 |
|
|
port (
|
79 |
|
|
CLKM : in slbit; -- M|clock master
|
80 |
|
|
RESET : in slbit := '0'; -- M|reset
|
81 |
|
|
CLKS : in slbit; -- S|clock slave
|
82 |
|
|
PIN : in slbit; -- M|pulse in
|
83 |
|
|
BUSY : out slbit; -- M|busy
|
84 |
|
|
POUT : out slbit -- S|pulse out
|
85 |
|
|
);
|
86 |
|
|
end component;
|
87 |
|
|
|
88 |
|
|
component cdc_value is -- cdc for value (slow change)
|
89 |
|
|
generic (
|
90 |
|
|
DWIDTH : positive := 16); -- data port width
|
91 |
|
|
port (
|
92 |
|
|
CLKO : in slbit; -- O|output clock
|
93 |
|
|
DI : in slv(DWIDTH-1 downto 0); -- I|input data
|
94 |
|
|
DO : out slv(DWIDTH-1 downto 0); -- O|output data
|
95 |
|
|
DFIX : out slbit -- O|output data frozen
|
96 |
|
|
);
|
97 |
|
|
end component;
|
98 |
|
|
|
99 |
|
|
end package cdclib;
|