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-- $Id: ram_1swar_1ar_gen.vhd 750 2016-03-24 23:11:51Z mueller $
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--
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-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: ram_1swar_1ar_gen - syn
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-- Description: Dual-Port RAM with with one synchronous write and two
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-- asynchronius read ports (as distributed RAM).
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-- The code is inspired by Xilinx example rams_09.vhd. The
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-- 'ram_style' attribute is set to 'distributed', this will
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-- force in XST a synthesis as distributed RAM.
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--
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-- Dependencies: -
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-- Test bench: -
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-- Target Devices: generic Spartan, Virtex
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-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31
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-- Revision History:
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-- Date Rev Version Comment
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-- 2011-11-08 422 1.0.2 now numeric_std clean
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-- 2008-03-08 123 1.0.1 use std_..._arith, not _unsigned; use unsigned()
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-- 2007-06-03 45 1.0 Initial version
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--
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-- Some synthesis results:
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-- - 2010-06-03 (r123) with ise 11.4 for xc3s1000-ft256-4:
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-- AWIDTH DWIDTH LUTl LUTm RAM16X1D MUXF5 MUXF6 MUXF7
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-- 4 16 - 32 16 0 0 0
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-- 5 16 34 64 32 0 0 0
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-- 6 16 68 128 64 32 0 0
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-- 7 16 136 256 128 64 32 0
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-- 8 16 292 512 256 144 64 32
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-- - 2007-12-31 ise 8.2.03 for xc3s1000-ft256-4:
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-- {same results as above for AW=4 and 6}
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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entity ram_1swar_1ar_gen is -- RAM, 1 sync w asyn r + 1 asyn r port
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generic (
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AWIDTH : positive := 4; -- address port width
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DWIDTH : positive := 16); -- data port width
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port (
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CLK : in slbit; -- clock
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WE : in slbit; -- write enable (port A)
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ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
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ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
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DI : in slv(DWIDTH-1 downto 0); -- data in (port A)
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DOA : out slv(DWIDTH-1 downto 0); -- data out port A
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DOB : out slv(DWIDTH-1 downto 0) -- data out port B
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);
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end ram_1swar_1ar_gen;
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architecture syn of ram_1swar_1ar_gen is
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constant memsize : positive := 2**AWIDTH;
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constant datzero : slv(DWIDTH-1 downto 0) := (others=>'0');
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type ram_type is array (memsize-1 downto 0) of slv (DWIDTH-1 downto 0);
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signal RAM : ram_type := (others=>datzero);
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attribute ram_style : string;
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attribute ram_style of RAM : signal is "distributed";
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begin
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proc_clk: process (CLK)
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begin
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if rising_edge(CLK) then
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if WE = '1' then
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RAM(to_integer(unsigned(ADDRA))) <= DI;
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end if;
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end if;
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end process proc_clk;
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DOA <= RAM(to_integer(unsigned(ADDRA)));
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DOB <= RAM(to_integer(unsigned(ADDRB)));
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end syn;
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