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-- $Id: rblib.vhd 593 2014-09-14 22:21:33Z mueller $
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--
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-- Copyright 2007-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Package Name: rblib
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-- Description: Definitions for rbus interface and bus entities
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--
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-- Dependencies: -
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-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2014-09-14 593 4.0 use new rlink v4 iface and 4 bit STAT
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-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit
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-- 2011-12-23 444 3.1 CLK_CYCLE now integer
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-- 2011-08-13 405 3.0.3 add in direction for FADDR,SEL ports
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-- 2010-12-26 349 3.0.2 add rb_sel
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-- 2010-12-22 346 3.0.1 add rb_mon and rb_mon_sb;
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-- 2010-12-04 343 3.0 extracted from rrilib and rritblib;
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-- rbus V3 interface: use aval,re,we
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-- ... rrilib history removed ...
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-- 2007-09-09 81 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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package rblib is
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type rb_mreq_type is record -- rbus - master request
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aval : slbit; -- address valid
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re : slbit; -- read enable
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we : slbit; -- write enable
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init : slbit; -- init
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addr : slv16; -- address
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din : slv16; -- data (input to slave)
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end record rb_mreq_type;
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constant rb_mreq_init : rb_mreq_type :=
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('0','0','0','0', -- aval, re, we, init
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(others=>'0'), -- addr
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(others=>'0')); -- din
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type rb_sres_type is record -- rbus - slave response
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ack : slbit; -- acknowledge
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busy : slbit; -- busy
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err : slbit; -- error
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dout : slv16; -- data (output from slave)
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end record rb_sres_type;
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constant rb_sres_init : rb_sres_type :=
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('0','0','0', -- ack, busy, err
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(others=>'0')); -- dout
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component rb_sel is -- rbus address select logic
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generic (
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RB_ADDR : slv16; -- rbus address base
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SAWIDTH : natural := 0); -- device subaddress space width
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port (
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CLK : in slbit; -- clock
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RB_MREQ : in rb_mreq_type; -- rbus request
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SEL : out slbit -- select state bit
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);
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end component;
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component rb_sres_or_2 is -- rbus result or, 2 input
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port (
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RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
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RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
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RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
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);
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end component;
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component rb_sres_or_3 is -- rbus result or, 3 input
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port (
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RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
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RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
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RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3
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RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
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);
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end component;
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component rb_sres_or_4 is -- rbus result or, 4 input
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port (
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RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
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RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
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RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3
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RB_SRES_4 : in rb_sres_type := rb_sres_init; -- rb_sres input 4
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RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
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);
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end component;
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component rbus_aif is -- rbus, abstract interface
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port (
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CLK : in slbit; -- clock
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RESET : in slbit := '0'; -- reset
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RB_MREQ : in rb_mreq_type; -- rbus: request
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RB_SRES : out rb_sres_type; -- rbus: response
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RB_LAM : out slv16; -- rbus: look at me
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RB_STAT : out slv4 -- rbus: status flags
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);
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end component;
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component rb_wreg_rw_3 is -- rbus: wide register r/w 3 bit select
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generic (
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DWIDTH : positive := 16);
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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FADDR : in slv3; -- field address
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SEL : in slbit; -- select
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DATA : out slv(DWIDTH-1 downto 0); -- data
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RB_MREQ : in rb_mreq_type; -- rbus request
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RB_SRES : out rb_sres_type -- rbus response
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);
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end component;
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component rb_wreg_w_3 is -- rbus: wide register w-o 3 bit select
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generic (
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DWIDTH : positive := 16);
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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FADDR : in slv3; -- field address
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SEL : in slbit; -- select
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DATA : out slv(DWIDTH-1 downto 0); -- data
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RB_MREQ : in rb_mreq_type; -- rbus request
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RB_SRES : out rb_sres_type -- rbus response
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);
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end component;
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component rb_wreg_r_3 is -- rbus: wide register r-o 3 bit select
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generic (
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DWIDTH : positive := 16);
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port (
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FADDR : in slv3; -- field address
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SEL : in slbit; -- select
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DATA : in slv(DWIDTH-1 downto 0); -- data
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RB_SRES : out rb_sres_type -- rbus response
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);
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end component;
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--
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-- components for use in test benches (not synthesizable)
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--
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component rb_sres_or_mon is -- rbus result or monitor
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port (
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RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
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RB_SRES_2 : in rb_sres_type; -- rb_sres input 2
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RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3
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RB_SRES_4 : in rb_sres_type := rb_sres_init -- rb_sres input 4
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);
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end component;
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-- simbus sb_cntl field usage for rbus
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constant sbcntl_sbf_rbmon : integer := 13;
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component rb_mon is -- rbus monitor
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generic (
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DBASE : positive := 2); -- base for writing data values
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port (
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CLK : in slbit; -- clock
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CLK_CYCLE : in integer := 0; -- clock cycle number
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ENA : in slbit := '1'; -- enable monitor output
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RB_MREQ : in rb_mreq_type; -- rbus: request
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RB_SRES : in rb_sres_type; -- rbus: response
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RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me
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RB_STAT : in slv4 -- rbus: status flags
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);
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end component;
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component rb_mon_sb is -- simbus wrapper for rbus monitor
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generic (
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DBASE : positive := 2; -- base for writing data values
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ENAPIN : integer := sbcntl_sbf_rbmon); -- SB_CNTL signal to use for enable
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port (
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CLK : in slbit; -- clock
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RB_MREQ : in rb_mreq_type; -- rbus: request
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RB_SRES : in rb_sres_type; -- rbus: response
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RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me
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RB_STAT : in slv4 -- rbus: status flags
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);
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end component;
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end package rblib;
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