OpenCores
URL https://opencores.org/ocsvn/w11/w11/trunk

Subversion Repositories w11

[/] [w11/] [tags/] [w11a_V0.74/] [rtl/] [vlib/] [rbus/] [rblib.vhd] - Blame information for rev 9

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 9 wfjm 
-- $Id: rblib.vhd 349 2010-12-28 14:02:13Z mueller $
2 2 wfjm 
--
3 
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4 
--
5 
-- This program is free software; you may redistribute and/or modify it under
6 
-- the terms of the GNU General Public License as published by the Free
7 
-- Software Foundation, either version 2, or at your option any later version.
8 
--
9 
-- This program is distributed in the hope that it will be useful, but
10 
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
11 
-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
12 
-- for complete details.
13 
--
14 
------------------------------------------------------------------------------
15 9 wfjm 
-- Package Name:   rblib
16 
-- Description:    Definitions for rbus interface and bus entities
17 2 wfjm 
--
18 
-- Dependencies:   -
19 9 wfjm 
-- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
20 
--
21 2 wfjm 
-- Revision History:
22 
-- Date         Rev Version  Comment
23 9 wfjm 
-- 2010-12-26   349   3.0.2  add rb_sel
24 
-- 2010-12-22   346   3.0.1  add rb_mon and rb_mon_sb;
25 
-- 2010-12-04   343   3.0    extracted from rrilib and rritblib;
26 
--                           rbus V3 interface: use aval,re,we
27 
--                           ... rrilib history removed ...
28 2 wfjm 
-- 2007-09-09    81   1.0    Initial version
29 
------------------------------------------------------------------------------
30 
 
31 
library ieee;
32 
use ieee.std_logic_1164.all;
33 
 
34 
use work.slvtypes.all;
35 
 
36 9 wfjm 
package rblib is
37 2 wfjm 
 
38 9 wfjm 
type rb_mreq_type is record             -- rbus - master request
39 
  aval : slbit;                         -- address valid
40 
  re   : slbit;                         -- read enable
41 2 wfjm 
  we   : slbit;                         -- write enable
42 
  init : slbit;                         -- init
43 
  addr : slv8;                          -- address
44 
  din  : slv16;                         -- data (input to slave)
45 
end record rb_mreq_type;
46 
 
47 
constant rb_mreq_init : rb_mreq_type :=
48 9 wfjm 
  ('0','0','0','0',                     -- aval, re, we, init
49 2 wfjm 
   (others=>'0'),                       -- addr
50 
   (others=>'0'));                      -- din
51 
 
52 9 wfjm 
type rb_sres_type is record             -- rbus - slave response
53 2 wfjm 
  ack  : slbit;                         -- acknowledge
54 
  busy : slbit;                         -- busy
55 
  err  : slbit;                         -- error
56 
  dout : slv16;                         -- data (output from slave)
57 
end record rb_sres_type;
58 
 
59 
constant rb_sres_init : rb_sres_type :=
60 
  ('0','0','0',                         -- ack, busy, err
61 
   (others=>'0'));                      -- dout
62 
 
63 9 wfjm 
component rb_sel is                     -- rbus address select logic
64 2 wfjm 
  generic (
65 9 wfjm 
    RB_ADDR : slv8;                     -- rbus address base
66 
    SAWIDTH : natural := 0);            -- device subaddress space width
67 2 wfjm 
  port (
68 9 wfjm 
    CLK : in slbit;                     -- clock
69 
    RB_MREQ : in rb_mreq_type;          -- rbus request
70 
    SEL : out slbit                     -- select state bit
71 2 wfjm 
  );
72 
end component;
73 
 
74 9 wfjm 
component rb_sres_or_2 is               -- rbus result or, 2 input
75 2 wfjm 
  port (
76 
    RB_SRES_1  :  in rb_sres_type;                 -- rb_sres input 1
77 
    RB_SRES_2  :  in rb_sres_type := rb_sres_init; -- rb_sres input 2
78 
    RB_SRES_OR : out rb_sres_type       -- rb_sres or'ed output
79 
  );
80 
end component;
81 9 wfjm 
component rb_sres_or_3 is               -- rbus result or, 3 input
82 2 wfjm 
  port (
83 
    RB_SRES_1  :  in rb_sres_type;                 -- rb_sres input 1
84 
    RB_SRES_2  :  in rb_sres_type := rb_sres_init; -- rb_sres input 2
85 
    RB_SRES_3  :  in rb_sres_type := rb_sres_init; -- rb_sres input 3
86 
    RB_SRES_OR : out rb_sres_type       -- rb_sres or'ed output
87 
  );
88 
end component;
89 9 wfjm 
component rb_sres_or_4 is               -- rbus result or, 4 input
90 2 wfjm 
  port (
91 
    RB_SRES_1  :  in rb_sres_type;                 -- rb_sres input 1
92 
    RB_SRES_2  :  in rb_sres_type := rb_sres_init; -- rb_sres input 2
93 
    RB_SRES_3  :  in rb_sres_type := rb_sres_init; -- rb_sres input 3
94 
    RB_SRES_4  :  in rb_sres_type := rb_sres_init; -- rb_sres input 4
95 
    RB_SRES_OR : out rb_sres_type       -- rb_sres or'ed output
96 
  );
97 
end component;
98 
 
99 9 wfjm 
component rbus_aif is                   -- rbus, abstract interface
100 
  port (
101 
    CLK  : in slbit;                    -- clock
102 
    RESET  : in slbit := '0';           -- reset
103 
    RB_MREQ : in rb_mreq_type;          -- rbus: request
104 
    RB_SRES : out rb_sres_type;         -- rbus: response
105 
    RB_LAM : out slv16;                 -- rbus: look at me
106 
    RB_STAT : out slv3                  -- rbus: status flags
107 
  );
108 
end component;
109 
 
110 
component rb_wreg_rw_3 is               -- rbus: wide register r/w 3 bit select
111 2 wfjm 
  generic (
112 
    DWIDTH : positive := 16);
113 
  port (
114 
    CLK  : in slbit;                    -- clock
115 
    RESET  : in slbit;                  -- reset
116 
    FADDR : slv3;                       -- field address
117 
    SEL : slbit;                        -- select
118 
    DATA : out slv(DWIDTH-1 downto 0);  -- data
119 9 wfjm 
    RB_MREQ :  in rb_mreq_type;         -- rbus request
120 
    RB_SRES : out rb_sres_type          -- rbus response
121 2 wfjm 
  );
122 
end component;
123 
 
124 9 wfjm 
component rb_wreg_w_3 is                -- rbus: wide register w-o 3 bit select
125 2 wfjm 
  generic (
126 
    DWIDTH : positive := 16);
127 
  port (
128 
    CLK  : in slbit;                    -- clock
129 
    RESET  : in slbit;                  -- reset
130 
    FADDR : slv3;                       -- field address
131 
    SEL : slbit;                        -- select
132 
    DATA : out slv(DWIDTH-1 downto 0);  -- data
133 9 wfjm 
    RB_MREQ :  in rb_mreq_type;         -- rbus request
134 
    RB_SRES : out rb_sres_type          -- rbus response
135 2 wfjm 
  );
136 
end component;
137 
 
138 9 wfjm 
component rb_wreg_r_3 is                -- rbus: wide register r-o 3 bit select
139 2 wfjm 
  generic (
140 
    DWIDTH : positive := 16);
141 
  port (
142 
    FADDR : slv3;                       -- field address
143 
    SEL : slbit;                        -- select
144 
    DATA : in slv(DWIDTH-1 downto 0);   -- data
145 9 wfjm 
    RB_SRES : out rb_sres_type          -- rbus response
146 2 wfjm 
  );
147 
end component;
148 
 
149 9 wfjm 
--
150 
-- components for use in test benches (not synthesizable)
151 
--
152 
 
153 
component rb_sres_or_mon is             -- rbus result or monitor
154 
  port (
155 
    RB_SRES_1  :  in rb_sres_type;      -- rb_sres input 1
156 
    RB_SRES_2  :  in rb_sres_type;      -- rb_sres input 2
157 
    RB_SRES_3  :  in rb_sres_type := rb_sres_init; -- rb_sres input 3
158 
    RB_SRES_4  :  in rb_sres_type := rb_sres_init  -- rb_sres input 4
159 
  );
160 
end component;
161 
 
162 
-- simbus sb_cntl field usage for rbus
163 
constant sbcntl_sbf_rbmon : integer := 14;
164 
 
165 
component rb_mon is                     -- rbus monitor
166 
  generic (
167 
    DBASE : positive :=  2);            -- base for writing data values
168 
  port (
169 
    CLK  : in slbit;                    -- clock
170 
    CLK_CYCLE : in slv31 := (others=>'0');  -- clock cycle number
171 
    ENA  : in slbit := '1';             -- enable monitor output
172 
    RB_MREQ : in rb_mreq_type;          -- rbus: request
173 
    RB_SRES : in rb_sres_type;          -- rbus: response
174 
    RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me
175 
    RB_STAT : in slv3                   -- rbus: status flags
176 
  );
177 
end component;
178 
 
179 
component rb_mon_sb is                  -- simbus wrapper for rbus monitor
180 
  generic (
181 
    DBASE : positive :=  2;             -- base for writing data values
182 
    ENAPIN : integer := sbcntl_sbf_rbmon); -- SB_CNTL signal to use for enable
183 
  port (
184 
    CLK  : in slbit;                    -- clock
185 
    RB_MREQ : in rb_mreq_type;          -- rbus: request
186 
    RB_SRES : in rb_sres_type;          -- rbus: response
187 
    RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me
188 
    RB_STAT : in slv3                   -- rbus: status flags
189 
  );
190 
end component;
191 
 
192 
 
193 
end rblib;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.