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-- $Id: rri_core.vhd 314 2010-07-09 17:38:41Z mueller $
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--
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-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: rri_core - syn
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-- Description: rri: core interface
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--
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-- Dependencies: comlib/crc8
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--
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-- Test bench: tb/tb_rri_core
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-- tb/tb_rritba_ttcombo
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-- tb/tb_rriext_ttcombo
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--
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-- Target Devices: generic
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
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--
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2010-06-06 302 11.4 L68 xc3s1000-4 151 323 0 197 s 8.9
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-- 2010-04-03 274 11.4 L68 xc3s1000-4 148 313 0 190 s 8.0
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-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 147 321 0 197 s 8.3
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2010-06-20 308 2.6 use rbinit,rbreq,rbwe state flops to drive rb_mreq;
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-- now nak on reserved cmd 111; use do_comma_abort();
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-- 2010-06-18 306 2.5.1 rename rbus data fields to _rbf_
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-- 2010-06-06 302 2.5 use sop/eop framing instead of soc+chaining
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-- 2010-06-03 299 2.1.2 drop unneeded unsigned casts; change init encoding
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-- 2010-05-02 287 2.1.1 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
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-- drop RP_IINT signal from interfaces
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-- 2010-04-03 274 2.1 add CP_FLUSH output
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-- 2009-07-12 233 2.0.1 remove snoopers
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-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface
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-- 2008-03-02 121 1.1.1 comment out snoopers
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-- 2007-11-24 98 1.1 new internal init handling (addr=11111111)
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-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
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-- 2007-09-15 82 1.0 Initial version, fully functional
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-- 2007-06-17 58 0.5 First preliminary version
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------------------------------------------------------------------------------
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--
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-- Overall protocol:
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-- _idle : expect
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-- sop -> _txsop (echo sop, , to _txsop, _rxcmd)
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-- eop -> _txeop (send nak,eop , to _txnak, _txeop, _idle)
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-- nak -> _txnak (silently ignore nak)
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-- attn -> _txito (send ito , to _idle)
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-- data -> _idle (silently ignore data)
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-- _error: expect
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-- sop -> _txnak (send nak , to _txnak, _error)
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-- eop -> _txeop (echo eop , to _txeop, _idle)
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-- nak -> _txnak (echo nak , to _txnak, _error)
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-- attn -> _txito (silently ignore attn)
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-- data -> _idle (silently ignore data)
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-- _rxcmd: expect
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-- sop -> _txnak (send nak , to _txnak, _error)
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-- eop -> _txeop (echo eop , to _txeop, _idle)
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-- nak -> _txnak (echo nak , to _txnak, _error)
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-- attn -> _txito (silently ignore attn)
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-- data -> _idle (decode command)
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-- _rx...: expect
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-- sop -> _txnak (send nak , to _txnak, _error)
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-- eop -> _txnak (send nak,eop , to _txnak, _txeop, _idle)
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-- nak -> _txnak (echo nak , to _txnak, _error)
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-- attn -> _txito (silently ignore attn)
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-- data -> _idle (decode data)
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--
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-- 7 supported commands:
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--
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-- 000 read reg (rreg):
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-- rx: cmd addr ccrc
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-- tx: cmd dl dh stat crc
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-- seq: _rxcmd _rxaddr _rxccrc (_txcmd|_txnak)
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-- _rreg _txdatl _txdath _txstat _txcrc (_rxcmd|_idle)
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--
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-- 001 read blk (rblk):
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-- rx: cmd addr cnt ccrc
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-- tx: cmd cnt dl dh ... stat crc
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-- seq: _rxcmd _rxaddr _rxcnt _rxccrc (_txcmd|_txnak) _txcnt
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-- {_rreg _txdatl _txdath _blk}* _txstat _txcrc (_rxcmd|_idle)
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--
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-- 010 write reg (wreg):
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-- rx: cmd addr dl dh ccrc
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-- tx: cmd stat crc
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-- seq: _rxcmd _rxaddr _rxdatl _rxdath _rxccrc (_txcmd|_txnak)
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-- seq: _wreg _txstat _txcrc (_rxcmd|_idle)
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--
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-- 011 write blk (wblk):
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-- rx: cmd addr cnt ccrc dl dh ... dcrc
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-- tx: cmd stat crc
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-- seq: _rxcmd _rxaddr _rxcnt _rxccrc (_txcmd|_txnak)
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-- {_rxdatl _rxdath _wreg _blk}* _rxdcrc _txstat _txcrc (_rxcmd|_idle)
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--
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-- 100 read stat (stat):
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-- rx: cmd ccrc
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-- tx: cmd ccmd dl dh stat crc
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-- seq: _rxcmd _rxccrc (_txcmd|_txnak)
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-- _txccmd _txdatl _txdath _txstat _txcrc (_rxcmd|_idle)
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--
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-- 101 read attn (attn):
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-- rx: cmd ccrc
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-- tx: cmd dl dh stat crc
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-- seq: _rxcmd _rxccrc (_txcmd|_txnak)
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-- _attn _txdatl _txdath _txstat _txcrc (_rxcmd|_idle)
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--
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-- 110 write init (init):
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-- rx: cmd addr dl dh ccrc
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-- tx: cmd stat crc
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-- seq: _rxcmd _rxaddr _rxdatl _rxdath _rxccrc (_txcmd|_txnak)
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-- seq: _txstat _txcrc (_rxcmd|_idle)
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-- like wreg, but no rp_we - rp_hold, just a 1 cycle rp_init pulse
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--
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-- 111 is currently not a legal command and causes a nak
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-- seq: _txnak
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--
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-- The different rbus cycle types are encoded as:
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--
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-- init ack we
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-- 0 0 0 idle
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-- 0 0 1 idle
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-- 0 1 0 read
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-- 0 1 1 write
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-- 1 0 0 internal init
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-- 1 0 1 external init
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-- 1 1 0 not allowed
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-- 1 1 1 not allowed
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use work.slvtypes.all;
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use work.comlib.all;
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use work.rrilib.all;
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entity rri_core is -- rri, core interface
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generic (
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ATOWIDTH : positive := 5; -- access timeout counter width
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ITOWIDTH : positive := 6); -- idle timeout counter width
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port (
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CLK : in slbit; -- clock
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CE_INT : in slbit := '0'; -- rri ito time unit clock enable
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RESET : in slbit; -- reset
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CP_DI : in slv9; -- comm port: data in
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CP_ENA : in slbit; -- comm port: data enable
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CP_BUSY : out slbit; -- comm port: data busy
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CP_DO : out slv9; -- comm port: data out
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CP_VAL : out slbit; -- comm port: data valid
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CP_HOLD : in slbit; -- comm port: data hold
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CP_FLUSH : out slbit; -- comm port: data flush
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RB_MREQ : out rb_mreq_type; -- rbus: request
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RB_SRES : in rb_sres_type; -- rbus: response
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RB_LAM : in slv16; -- rbus: look at me
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RB_STAT : in slv3 -- rbus: status flags
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);
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end entity rri_core;
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architecture syn of rri_core is
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type state_type is (
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s_idle, -- s_idle: wait for sop
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s_txito, -- s_txito: send timeout symbol
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s_txsop, -- s_txsop: send sop
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s_txnak, -- s_txnak: send nak
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s_txeop, -- s_txeop: send eop
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s_error, -- s_error: wait for eop
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s_rxcmd, -- s_rxcmd: wait for cmd
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s_rxaddr, -- s_rxaddr: wait for addr
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s_rxdatl, -- s_rxdatl: wait for data low
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s_rxdath, -- s_rxdath: wait for data high
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s_rxcnt, -- s_rxcnt: wait for count
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s_rxccrc, -- s_rxccrc: wait for command crc
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s_txcmd, -- s_txcmd: send cmd
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s_txcnt, -- s_txcnt: send cnt
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s_rreg, -- s_rreg: reg or blk read
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s_txdatl, -- s_txdatl: send data low
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s_txdath, -- s_txdath: send data high
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s_wreg, -- s_wreg: reg or blk write
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s_blk, -- s_blk: block count handling
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s_rxdcrc, -- s_rxdcrc: wait for data crc
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s_attn, -- s_attn: handle attention flags
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s_txccmd, -- s_txccmd: send last command
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s_txstat, -- s_txstat: send status
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s_txcrc -- s_txcrc: send crc
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);
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type regs_type is record
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state : state_type; -- state
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rcmd : slv8; -- received command
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ccmd : slv8; -- current command
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addr : slv8; -- register address
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dil : slv8; -- input data, lsb
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dih : slv8; -- input data, msb
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dol : slv8; -- output data, lsb
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doh : slv8; -- output data, msb
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cnt : slv8; -- block transfer count
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attn : slv16; -- attn mask
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atocnt : slv(ATOWIDTH-1 downto 0); -- access timeout counter
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itocnt : slv(ITOWIDTH-1 downto 0); -- idle timeout counter
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itoval : slv(ITOWIDTH-1 downto 0); -- idle timeout value
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itoena : slbit; -- idle timeout enable flag
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anena : slbit; -- attn notification enable flag
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andone : slbit; -- attn notification done
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ccrc : slbit; -- stat: command crc error
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dcrc : slbit; -- stat: data crc error
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ioto : slbit; -- stat: i/o time out
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ioerr : slbit; -- stat: i/o time error
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nakeop : slbit; -- send eop after nak
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rbinit : slbit; -- rbus init signal
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rbreq : slbit; -- rbus req signal
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rbwe : slbit; -- rbus we signal
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flush : slbit; -- flush pulse
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stat : slv3; -- external status flags
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end record regs_type;
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constant atocnt_init : slv(ATOWIDTH-1 downto 0) := (others=>'1');
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constant itocnt_init : slv(ITOWIDTH-1 downto 0) := (others=>'0');
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constant c_idle : slv4 := "0000";
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constant c_sop : slv4 := "0001";
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constant c_eop : slv4 := "0010";
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constant c_nak : slv4 := "0011";
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constant c_attn : slv4 := "0100";
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constant regs_init : regs_type := (
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s_idle, --
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(others=>'0'), -- rcmd
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(others=>'0'), -- ccmd
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(others=>'0'), -- addr
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(others=>'0'), -- dil
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(others=>'0'), -- dih
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(others=>'0'), -- dol
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(others=>'0'), -- doh
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(others=>'0'), -- cnt
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(others=>'0'), -- attn
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atocnt_init, -- atocnt
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itocnt_init, -- itocnt
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itocnt_init, -- itoval
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'0', -- itoena
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'0','0', -- anena, andone
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'0','0','0','0', -- stat flags
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'0', -- nakeop
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'0','0','0', -- rbinit,rbreq,rbwe
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'0', -- flush
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(others=>'0') -- stat
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);
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signal R_REGS : regs_type := regs_init; -- state registers
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signal N_REGS : regs_type := regs_init; -- next value state regs
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signal CRC_RESET : slbit := '0';
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signal ICRC_ENA : slbit := '0';
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signal OCRC_ENA : slbit := '0';
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signal ICRC_OUT : slv8 := (others=>'0');
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signal OCRC_OUT : slv8 := (others=>'0');
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signal OCRC_IN : slv8 := (others=>'0');
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begin
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assert ITOWIDTH<=8
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report "assert(ITOWIDTH<=8): max byte size ITO counter supported"
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severity failure;
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ICRC : crc8 -- crc generator for input data
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port map (
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CLK => CLK,
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RESET => CRC_RESET,
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ENA => ICRC_ENA,
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DI => CP_DI(7 downto 0),
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CRC => ICRC_OUT
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);
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OCRC : crc8 -- crc generator for output data
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port map (
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CLK => CLK,
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RESET => CRC_RESET,
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ENA => OCRC_ENA,
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DI => OCRC_IN,
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CRC => OCRC_OUT
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);
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proc_regs: process (CLK)
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begin
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if CLK'event and CLK='1' then
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if RESET = '1' then
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R_REGS <= regs_init;
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else
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R_REGS <= N_REGS;
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end if;
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end if;
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end process proc_regs;
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proc_next: process (R_REGS, CE_INT, CP_DI, CP_ENA, CP_HOLD, RB_LAM,
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RB_SRES, RB_STAT, ICRC_OUT, OCRC_OUT)
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variable r : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable ival : slbit := '0';
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variable ibusy : slbit := '0';
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variable ido : slv9 := (others=>'0');
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|
variable ato_go : slbit := '0';
|
317 |
|
|
variable ato_end : slbit := '0';
|
318 |
|
|
variable ito_go : slbit := '0';
|
319 |
|
|
variable ito_end : slbit := '0';
|
320 |
|
|
variable crcreset : slbit := '0';
|
321 |
|
|
variable icrcena : slbit := '0';
|
322 |
|
|
variable ocrcena : slbit := '0';
|
323 |
|
|
variable has_attn : slbit := '0';
|
324 |
|
|
variable idi8 : slv8 := (others=>'0');
|
325 |
|
|
variable is_comma : slbit := '0';
|
326 |
|
|
variable comma_typ : slv4 := "0000";
|
327 |
|
|
|
328 |
|
|
procedure do_comma_abort(nstate : inout state_type;
|
329 |
|
|
nnakeop : inout slbit;
|
330 |
|
|
comma_typ : in slv4) is
|
331 |
|
|
begin
|
332 |
|
|
if comma_typ=c_sop or comma_typ=c_eop or comma_typ=c_nak then
|
333 |
|
|
if comma_typ = c_eop then
|
334 |
|
|
nnakeop := '1';
|
335 |
|
|
end if;
|
336 |
|
|
nstate := s_txnak; -- next: send nak
|
337 |
|
|
end if;
|
338 |
|
|
end procedure do_comma_abort;
|
339 |
|
|
|
340 |
|
|
begin
|
341 |
|
|
|
342 |
|
|
r := R_REGS;
|
343 |
|
|
n := R_REGS;
|
344 |
|
|
|
345 |
|
|
idi8 := CP_DI(7 downto 0); -- get data part of CP_DI
|
346 |
|
|
is_comma := CP_DI(8); -- get comma marker
|
347 |
|
|
comma_typ := CP_DI(3 downto 0); -- get comma type
|
348 |
|
|
|
349 |
|
|
n.rbinit := '0'; -- clear rbinit,rbreq,rbwe by default
|
350 |
|
|
n.rbreq := '0'; -- they must always be set by the
|
351 |
|
|
n.rbwe := '0'; -- 'previous state'
|
352 |
|
|
|
353 |
|
|
n.flush := '0'; -- dito for flush
|
354 |
|
|
|
355 |
|
|
ibusy := '1'; -- default is to hold input
|
356 |
|
|
ival := '0';
|
357 |
|
|
ido := (others=>'0');
|
358 |
|
|
|
359 |
|
|
crcreset := '0';
|
360 |
|
|
icrcena := '0';
|
361 |
|
|
ocrcena := '0';
|
362 |
|
|
|
363 |
|
|
for i in RB_LAM'range loop -- handle attention "LAM's"
|
364 |
|
|
if RB_LAM(i) = '1' then -- if LAM bit set
|
365 |
|
|
n.attn(i) := '1'; -- set attention bit
|
366 |
|
|
end if;
|
367 |
|
|
end loop;
|
368 |
|
|
|
369 |
|
|
has_attn := '0';
|
370 |
|
|
if unsigned(r.attn) /= 0 then -- is any of the attn bits set ?
|
371 |
|
|
has_attn := '1';
|
372 |
|
|
end if;
|
373 |
|
|
|
374 |
|
|
ato_go := '0'; -- default: keep access timeout in reset
|
375 |
|
|
ato_end := '0';
|
376 |
|
|
if unsigned(r.atocnt) = 0 then -- if access timeout count at zero
|
377 |
|
|
ato_end := '1'; -- signal expiration
|
378 |
|
|
end if;
|
379 |
|
|
|
380 |
|
|
ito_go := '0'; -- default: keep idle timeout in reset
|
381 |
|
|
ito_end := '0';
|
382 |
|
|
if unsigned(r.itocnt) = 0 then -- if idle timeout count at zero
|
383 |
|
|
ito_end := '1'; -- signal expiration
|
384 |
|
|
end if;
|
385 |
|
|
|
386 |
|
|
case r.state is
|
387 |
|
|
when s_idle => -- s_idle: wait for sop --------------
|
388 |
|
|
ito_go := '1'; -- idle timeout active
|
389 |
|
|
if (r.anena='1' and -- if attn notification to send
|
390 |
|
|
has_attn='1' and r.andone='0') then
|
391 |
|
|
n.state := s_txito; -- next send ito byte
|
392 |
|
|
else
|
393 |
|
|
ibusy := '0'; -- accept input
|
394 |
|
|
if CP_ENA = '1' then -- if input
|
395 |
|
|
if is_comma = '1' then -- if comma
|
396 |
|
|
case comma_typ is
|
397 |
|
|
when c_sop => -- if sop
|
398 |
|
|
crcreset := '1'; -- reset crc generators
|
399 |
|
|
n.state := s_txsop; -- next: echo it
|
400 |
|
|
when c_eop => -- if eop (unexpected)
|
401 |
|
|
n.nakeop := '1'; -- send nak,eop
|
402 |
|
|
n.state := s_txnak; -- next: send nak
|
403 |
|
|
when c_attn => -- if attn
|
404 |
|
|
n.state := s_txito; -- next: send ito byte
|
405 |
|
|
when others => null; -- other commas: silently ignore
|
406 |
|
|
end case;
|
407 |
|
|
else -- if normal data
|
408 |
|
|
n.state := s_idle; -- silently dropped
|
409 |
|
|
end if;
|
410 |
|
|
elsif (r.itoena='1' and -- if ito enable, expired and XSEC
|
411 |
|
|
ito_end='1' and CE_INT='1') then
|
412 |
|
|
n.state := s_txito; -- next: send ito byte
|
413 |
|
|
end if;
|
414 |
|
|
end if;
|
415 |
|
|
|
416 |
|
|
when s_txito => -- s_txito: send timeout symbol ------
|
417 |
|
|
if has_attn = '1' then
|
418 |
|
|
ido := c_rri_dat_attn; -- if attn pending: send attn symbol
|
419 |
|
|
n.andone := '1';
|
420 |
|
|
else
|
421 |
|
|
ido := c_rri_dat_idle; -- otherwise: send idle symbol
|
422 |
|
|
end if;
|
423 |
|
|
ival := '1';
|
424 |
|
|
if CP_HOLD = '0' then -- wait for accept
|
425 |
|
|
n.state := s_idle; -- next: wait for sop
|
426 |
|
|
end if;
|
427 |
|
|
|
428 |
|
|
when s_txsop => -- s_txsop: send sop -----------------
|
429 |
|
|
ido := c_rri_dat_sop; -- send sop character
|
430 |
|
|
ival := '1';
|
431 |
|
|
if CP_HOLD = '0' then -- wait for accept
|
432 |
|
|
n.state := s_rxcmd; -- next: read first command
|
433 |
|
|
end if;
|
434 |
|
|
|
435 |
|
|
when s_txnak => -- s_txnak: send nak -----------------
|
436 |
|
|
ido := c_rri_dat_nak; -- send nak character
|
437 |
|
|
ival := '1';
|
438 |
|
|
if CP_HOLD = '0' then -- wait for accept
|
439 |
|
|
n.nakeop := '0';
|
440 |
|
|
if r.nakeop = '1' then -- if eop after nak requested
|
441 |
|
|
n.state := s_txeop; -- next: send eop
|
442 |
|
|
else
|
443 |
|
|
n.state := s_error; -- next: error state, wait for eop
|
444 |
|
|
end if;
|
445 |
|
|
end if;
|
446 |
|
|
|
447 |
|
|
when s_txeop => -- s_txeop: send eop -----------------
|
448 |
|
|
ido := c_rri_dat_eop; -- send eop character
|
449 |
|
|
ival := '1';
|
450 |
|
|
if CP_HOLD = '0' then -- wait for accept
|
451 |
|
|
n.flush := '1'; -- send flush pulse
|
452 |
|
|
n.state := s_idle; -- next: idle state, wait for sop
|
453 |
|
|
end if;
|
454 |
|
|
|
455 |
|
|
when s_error => -- s_error: wait for eop -------------
|
456 |
|
|
ibusy := '0'; -- accept input
|
457 |
|
|
if CP_ENA = '1' then
|
458 |
|
|
if is_comma = '1' then -- if comma
|
459 |
|
|
case comma_typ is
|
460 |
|
|
when c_sop => -- if sop (unexpected)
|
461 |
|
|
n.state := s_txnak; -- next: send nak
|
462 |
|
|
when c_eop => -- if eop
|
463 |
|
|
n.state := s_txeop; -- next: echo eop
|
464 |
|
|
when c_nak => -- if nak
|
465 |
|
|
n.state := s_txnak; -- next: echo nak
|
466 |
|
|
when others => null; -- other commas: silently ignore
|
467 |
|
|
end case;
|
468 |
|
|
else -- if normal data
|
469 |
|
|
n.state := s_error; -- silently dropped
|
470 |
|
|
end if;
|
471 |
|
|
end if;
|
472 |
|
|
|
473 |
|
|
when s_rxcmd => -- s_rxcmd: wait for cmd -------------
|
474 |
|
|
ibusy := '0'; -- accept input
|
475 |
|
|
if CP_ENA = '1' then
|
476 |
|
|
if is_comma = '1' then -- if comma
|
477 |
|
|
case comma_typ is
|
478 |
|
|
when c_sop => -- if sop (unexpected)
|
479 |
|
|
n.state := s_txnak; -- next: send nak
|
480 |
|
|
when c_eop => -- if eop
|
481 |
|
|
n.state := s_txeop; -- next: echo eop
|
482 |
|
|
when c_nak => -- if nak
|
483 |
|
|
n.state := s_txnak; -- next: echo nak
|
484 |
|
|
when others => null; --other commas: silently ignore
|
485 |
|
|
end case;
|
486 |
|
|
else
|
487 |
|
|
icrcena := '1'; -- update input crc
|
488 |
|
|
n.rcmd := idi8; -- latch read command code
|
489 |
|
|
case CP_DI(c_rri_cmd_rbf_code) is
|
490 |
|
|
when c_rri_cmd_rreg | c_rri_cmd_rblk |
|
491 |
|
|
c_rri_cmd_wreg | c_rri_cmd_wblk |
|
492 |
|
|
c_rri_cmd_init => -- for commands needing addr(data)
|
493 |
|
|
n.state := s_rxaddr; -- next: read address
|
494 |
|
|
when c_rri_cmd_stat | c_rri_cmd_attn => -- stat and attn commands
|
495 |
|
|
n.state := s_rxccrc; -- next: read command crc
|
496 |
|
|
when others =>
|
497 |
|
|
n.state := s_idle; -- if bad command abort here
|
498 |
|
|
end case; -- rcmd,ccmd always hold good cmd
|
499 |
|
|
end if;
|
500 |
|
|
end if;
|
501 |
|
|
|
502 |
|
|
when s_rxaddr => -- s_rxaddr: wait for addr -----------
|
503 |
|
|
ibusy := '0'; -- accept input
|
504 |
|
|
if CP_ENA = '1' then
|
505 |
|
|
if is_comma = '1' then -- if comma
|
506 |
|
|
do_comma_abort(n.state, n.nakeop, comma_typ);
|
507 |
|
|
else
|
508 |
|
|
icrcena := '1'; -- update input crc
|
509 |
|
|
n.addr := idi8; -- latch read address
|
510 |
|
|
case r.rcmd(c_rri_cmd_rbf_code) is
|
511 |
|
|
when c_rri_cmd_rreg => -- for rreg command
|
512 |
|
|
n.state := s_rxccrc; -- next: read command crc
|
513 |
|
|
when c_rri_cmd_wreg | c_rri_cmd_init => -- for wreg, init command
|
514 |
|
|
n.state := s_rxdatl; -- next: read data lsb
|
515 |
|
|
when others => -- for rblk or wblk
|
516 |
|
|
n.state := s_rxcnt; -- next: read count
|
517 |
|
|
end case;
|
518 |
|
|
end if;
|
519 |
|
|
end if;
|
520 |
|
|
|
521 |
|
|
when s_rxdatl => -- s_rxdatl: wait for data low -------
|
522 |
|
|
ibusy := '0'; -- accept input
|
523 |
|
|
if CP_ENA = '1' then
|
524 |
|
|
if is_comma = '1' then -- if comma
|
525 |
|
|
do_comma_abort(n.state, n.nakeop, comma_typ);
|
526 |
|
|
else
|
527 |
|
|
icrcena := '1'; -- update input crc
|
528 |
|
|
n.dil := idi8; -- latch data lsb part
|
529 |
|
|
n.state := s_rxdath; -- next: read data msb
|
530 |
|
|
end if;
|
531 |
|
|
end if;
|
532 |
|
|
|
533 |
|
|
when s_rxdath => -- s_rxdath: wait for data high ------
|
534 |
|
|
ibusy := '0'; -- accept input
|
535 |
|
|
if CP_ENA = '1' then
|
536 |
|
|
if is_comma = '1' then -- if comma
|
537 |
|
|
do_comma_abort(n.state, n.nakeop, comma_typ);
|
538 |
|
|
else
|
539 |
|
|
icrcena := '1'; -- update input crc
|
540 |
|
|
n.dih := idi8; -- latch data msb part
|
541 |
|
|
if r.rcmd(c_rri_cmd_rbf_code) = c_rri_cmd_wblk then -- if wblk
|
542 |
|
|
n.rbreq := '1';
|
543 |
|
|
n.rbwe := '1';
|
544 |
|
|
n.state := s_wreg; -- next: write reg
|
545 |
|
|
else -- otherwise
|
546 |
|
|
n.state := s_rxccrc; -- next: read command crc
|
547 |
|
|
end if;
|
548 |
|
|
end if;
|
549 |
|
|
end if;
|
550 |
|
|
|
551 |
|
|
when s_rxcnt => -- s_rxcnt: wait for count -----------
|
552 |
|
|
ibusy := '0'; -- accept input
|
553 |
|
|
if CP_ENA = '1' then
|
554 |
|
|
if is_comma = '1' then -- if comma
|
555 |
|
|
do_comma_abort(n.state, n.nakeop, comma_typ);
|
556 |
|
|
else
|
557 |
|
|
icrcena := '1'; -- update input crc
|
558 |
|
|
n.cnt := idi8; -- latch count
|
559 |
|
|
n.state := s_rxccrc; -- next: read command crc
|
560 |
|
|
end if;
|
561 |
|
|
end if;
|
562 |
|
|
|
563 |
|
|
when s_rxccrc => -- s_rxccrc: wait for command crc ----
|
564 |
|
|
ibusy := '0'; -- accept input
|
565 |
|
|
if CP_ENA = '1' then
|
566 |
|
|
if is_comma = '1' then -- if comma
|
567 |
|
|
do_comma_abort(n.state, n.nakeop, comma_typ);
|
568 |
|
|
else
|
569 |
|
|
if idi8 /= ICRC_OUT then -- if crc error
|
570 |
|
|
n.ccrc := '1'; -- set command crc error flag
|
571 |
|
|
n.state := s_txnak; -- next: send nak
|
572 |
|
|
else -- if crc ok
|
573 |
|
|
n.state := s_txcmd; -- next: echo command
|
574 |
|
|
end if;
|
575 |
|
|
end if;
|
576 |
|
|
end if;
|
577 |
|
|
|
578 |
|
|
when s_txcmd => -- s_txcmd: send cmd -----------------
|
579 |
|
|
ido := '0' & r.rcmd; -- send read command
|
580 |
|
|
ival := '1';
|
581 |
|
|
if CP_HOLD = '0' then -- wait for accept
|
582 |
|
|
ocrcena := '1'; -- update output crc
|
583 |
|
|
if r.rcmd(c_rri_cmd_rbf_code) /= c_rri_cmd_stat then -- unless stat
|
584 |
|
|
n.ccmd := r.rcmd; -- latch read command in ccmd
|
585 |
|
|
n.stat := RB_STAT; -- latch external status bits
|
586 |
|
|
n.ccrc := '0';
|
587 |
|
|
n.dcrc := '0';
|
588 |
|
|
n.ioto := '0';
|
589 |
|
|
n.ioerr := '0';
|
590 |
|
|
end if;
|
591 |
|
|
case r.rcmd(c_rri_cmd_rbf_code) is -- main command dispatcher
|
592 |
|
|
when c_rri_cmd_rreg => -- rreg ----------------
|
593 |
|
|
n.rbreq := '1';
|
594 |
|
|
n.state := s_rreg;
|
595 |
|
|
when c_rri_cmd_rblk => -- rblk ----------------
|
596 |
|
|
n.state := s_txcnt;
|
597 |
|
|
when c_rri_cmd_wreg => -- wreg ----------------
|
598 |
|
|
n.rbreq := '1';
|
599 |
|
|
n.rbwe := '1';
|
600 |
|
|
n.state := s_wreg;
|
601 |
|
|
when c_rri_cmd_wblk => -- wblk ----------------
|
602 |
|
|
n.state := s_rxdatl;
|
603 |
|
|
when c_rri_cmd_stat => -- stat ----------------
|
604 |
|
|
n.state := s_txccmd;
|
605 |
|
|
when c_rri_cmd_attn => -- attn ----------------
|
606 |
|
|
n.state := s_attn;
|
607 |
|
|
|
608 |
|
|
when c_rri_cmd_init => -- init ----------------
|
609 |
|
|
n.rbinit := '1'; -- send init pulse
|
610 |
|
|
if r.addr(7 downto 3) = "11111" then -- is internal init
|
611 |
|
|
if r.addr(2 downto 0) = "111" then -- is rri init
|
612 |
|
|
n.anena := r.dih(c_rri_iint_rbf_anena - 8);
|
613 |
|
|
n.itoena := r.dih(c_rri_iint_rbf_itoena - 8);
|
614 |
|
|
n.itoval := r.dil(ITOWIDTH-1 downto 0);
|
615 |
|
|
-- note: itocnt will load in next
|
616 |
|
|
-- cycle because ito_go=0, so no
|
617 |
|
|
-- action required here
|
618 |
|
|
|
619 |
|
|
end if;
|
620 |
|
|
else -- is external init
|
621 |
|
|
n.rbwe := '1'; -- send init with we
|
622 |
|
|
end if;
|
623 |
|
|
n.state := s_txstat;
|
624 |
|
|
|
625 |
|
|
when others => -- '111' ---------------
|
626 |
|
|
n.state := s_txnak; -- send NAK on reserved command
|
627 |
|
|
end case;
|
628 |
|
|
end if;
|
629 |
|
|
|
630 |
|
|
when s_txcnt => -- s_txcnt: send cnt -----------------
|
631 |
|
|
ido := '0' & r.cnt; -- send cnt
|
632 |
|
|
ival := '1';
|
633 |
|
|
if CP_HOLD = '0' then -- wait for accept
|
634 |
|
|
ocrcena := '1'; -- update output crc
|
635 |
|
|
n.rbreq := '1';
|
636 |
|
|
n.state := s_rreg; -- next: first read reg
|
637 |
|
|
end if;
|
638 |
|
|
|
639 |
|
|
when s_rreg => -- s_rreg: reg or blk read -----------
|
640 |
|
|
-- this state handles all rbus reads. Expects that previous state
|
641 |
|
|
-- sets n.rbreq := '1' to start an rbus read cycle
|
642 |
|
|
ato_go := '1'; -- activate timeout counter
|
643 |
|
|
if RB_SRES.err = '1' then -- latch error flag
|
644 |
|
|
n.ioerr := '1';
|
645 |
|
|
end if;
|
646 |
|
|
n.doh := RB_SRES.dout(15 downto 8); -- latch data
|
647 |
|
|
n.dol := RB_SRES.dout( 7 downto 0);
|
648 |
|
|
n.stat := RB_STAT; -- latch external status bits
|
649 |
|
|
if RB_SRES.busy='0' or ato_end='1' then -- wait for non-busy or timeout
|
650 |
|
|
if RB_SRES.busy='1' and ato_end='1' then -- if timeout and still busy
|
651 |
|
|
n.ioto := '1'; -- set timeout flag
|
652 |
|
|
elsif RB_SRES.ack = '0' then -- if non-busy and no ack
|
653 |
|
|
n.ioto := '1'; -- set timeout flag
|
654 |
|
|
end if;
|
655 |
|
|
n.state := s_txdatl; -- next: send data lsb
|
656 |
|
|
else -- otherwise rbus read continues
|
657 |
|
|
n.rbreq := '1'; -- extend req
|
658 |
|
|
end if;
|
659 |
|
|
|
660 |
|
|
when s_txdatl => -- s_txdatl: send data low -----------
|
661 |
|
|
ido := '0' & r.dol; -- send data
|
662 |
|
|
ival := '1';
|
663 |
|
|
if CP_HOLD = '0' then -- wait for accept
|
664 |
|
|
ocrcena := '1'; -- update output crc
|
665 |
|
|
n.state := s_txdath; -- next: send data msb
|
666 |
|
|
end if;
|
667 |
|
|
|
668 |
|
|
when s_txdath => -- s_txdath: send data high
|
669 |
|
|
ido := '0' & r.doh; -- send data
|
670 |
|
|
ival := '1';
|
671 |
|
|
if CP_HOLD = '0' then -- wait for accept
|
672 |
|
|
ocrcena := '1'; -- update output crc
|
673 |
|
|
if r.rcmd(c_rri_cmd_rbf_code) = c_rri_cmd_rblk then -- if rblk
|
674 |
|
|
n.state := s_blk; -- next: block count handling
|
675 |
|
|
else -- otherwise
|
676 |
|
|
n.state := s_txstat; -- next: send stat
|
677 |
|
|
end if;
|
678 |
|
|
end if;
|
679 |
|
|
|
680 |
|
|
when s_wreg => -- s_wreg: reg or blk write ----------
|
681 |
|
|
-- this state handles all rbus writes. Expects that previous state
|
682 |
|
|
-- sets n.rbreq := '1' and n.rbwe := '1' to start an rbus write cycle
|
683 |
|
|
ato_go := '1'; -- activate timeout counter
|
684 |
|
|
if RB_SRES.err = '1' then -- latch error flag
|
685 |
|
|
n.ioerr := '1';
|
686 |
|
|
end if;
|
687 |
|
|
n.stat := RB_STAT; -- latch external status bits
|
688 |
|
|
if RB_SRES.busy='0' or ato_end='1' then -- wait for non-busy or timeout
|
689 |
|
|
if RB_SRES.busy='1' and ato_end='1' then -- if timeout and still busy
|
690 |
|
|
n.ioto := '1'; -- set timeout flag
|
691 |
|
|
elsif RB_SRES.ack='0' then -- if non-busy and no ack
|
692 |
|
|
n.ioto := '1'; -- set timeout flag
|
693 |
|
|
end if;
|
694 |
|
|
if r.rcmd(c_rri_cmd_rbf_code) = c_rri_cmd_wblk then -- if wblk
|
695 |
|
|
n.state := s_blk; -- next: block count handling
|
696 |
|
|
else -- otherwise
|
697 |
|
|
n.state := s_txstat; -- next: send stat
|
698 |
|
|
end if;
|
699 |
|
|
else -- otherwise rbus write continues
|
700 |
|
|
n.rbreq := '1'; -- extend req
|
701 |
|
|
n.rbwe := '1'; -- extend we
|
702 |
|
|
end if;
|
703 |
|
|
|
704 |
|
|
when s_blk => -- s_blk: block count handling -------
|
705 |
|
|
n.cnt := unsigned(r.cnt) - 1; -- decrement transfer count
|
706 |
|
|
if unsigned(r.cnt) = 0 then -- if last transfer
|
707 |
|
|
if r.rcmd(c_rri_cmd_rbf_code) = c_rri_cmd_rblk then -- if rblk
|
708 |
|
|
n.state := s_txstat; -- next: send stat
|
709 |
|
|
else -- otherwise
|
710 |
|
|
n.state := s_rxdcrc; -- next: read data crc
|
711 |
|
|
end if;
|
712 |
|
|
|
713 |
|
|
else -- otherwise more to transfer
|
714 |
|
|
if r.rcmd(c_rri_cmd_rbf_code) = c_rri_cmd_rblk then -- if rblk
|
715 |
|
|
n.rbreq := '1';
|
716 |
|
|
n.state := s_rreg; -- next: read blk
|
717 |
|
|
else -- otherwise
|
718 |
|
|
n.state := s_rxdatl; -- next: read data
|
719 |
|
|
end if;
|
720 |
|
|
end if;
|
721 |
|
|
|
722 |
|
|
when s_rxdcrc => -- s_rxdcrc: wait for data crc -------
|
723 |
|
|
ibusy := '0'; -- accept input
|
724 |
|
|
if CP_ENA = '1' then
|
725 |
|
|
if is_comma = '1' then -- if comma
|
726 |
|
|
do_comma_abort(n.state, n.nakeop, comma_typ);
|
727 |
|
|
else
|
728 |
|
|
if idi8 /= ICRC_OUT then -- if crc error
|
729 |
|
|
n.dcrc := '1'; -- set data crc error flag
|
730 |
|
|
end if;
|
731 |
|
|
n.state := s_txstat; -- next: echo command
|
732 |
|
|
end if;
|
733 |
|
|
end if;
|
734 |
|
|
|
735 |
|
|
when s_attn => -- s_attn: handle attention flags ----
|
736 |
|
|
n.dol := r.attn(7 downto 0); -- move attention flags to do buffer
|
737 |
|
|
n.doh := r.attn(15 downto 8);
|
738 |
|
|
n.attn := RB_LAM; -- LAM in current cycle send next time
|
739 |
|
|
n.andone := '0'; -- reenable attn nofification
|
740 |
|
|
n.state := s_txdatl; -- next: send data lsb
|
741 |
|
|
|
742 |
|
|
when s_txccmd => -- s_txccmd: send last command
|
743 |
|
|
ido := '0' & r.ccmd; -- send last accepted command
|
744 |
|
|
ival := '1';
|
745 |
|
|
if CP_HOLD = '0' then -- wait for accept
|
746 |
|
|
ocrcena := '1'; -- update output crc
|
747 |
|
|
n.state := s_txdatl; -- next: send last data lsb
|
748 |
|
|
end if;
|
749 |
|
|
|
750 |
|
|
when s_txstat => -- s_txstat: send status -------------
|
751 |
|
|
ido := (others=>'0');
|
752 |
|
|
ido(c_rri_stat_rbf_stat) := r.stat;
|
753 |
|
|
ido(c_rri_stat_rbf_attn) := has_attn;
|
754 |
|
|
ido(c_rri_stat_rbf_ccrc) := r.ccrc;
|
755 |
|
|
ido(c_rri_stat_rbf_dcrc) := r.dcrc;
|
756 |
|
|
ido(c_rri_stat_rbf_ioto) := r.ioto;
|
757 |
|
|
ido(c_rri_stat_rbf_ioerr) := r.ioerr;
|
758 |
|
|
ival := '1';
|
759 |
|
|
if CP_HOLD ='0' then -- wait for accept
|
760 |
|
|
ocrcena := '1'; -- update output crc
|
761 |
|
|
n.state := s_txcrc; -- next: send crc
|
762 |
|
|
end if;
|
763 |
|
|
|
764 |
|
|
when s_txcrc => -- s_txcrc: send crc -----------------
|
765 |
|
|
ido := "0" & OCRC_OUT; -- send crc code
|
766 |
|
|
ival := '1';
|
767 |
|
|
if CP_HOLD = '0' then -- wait for accept
|
768 |
|
|
n.state := s_rxcmd; -- next: read command or eop
|
769 |
|
|
end if;
|
770 |
|
|
|
771 |
|
|
when others => null; -- <> --------------------------------
|
772 |
|
|
end case;
|
773 |
|
|
|
774 |
|
|
if ato_go = '0' then -- handle access timeout counter
|
775 |
|
|
n.atocnt := atocnt_init; -- if ato_go=0, keep in reset
|
776 |
|
|
else
|
777 |
|
|
n.atocnt := unsigned(r.atocnt) - 1;-- otherwise count down
|
778 |
|
|
end if;
|
779 |
|
|
|
780 |
|
|
if ito_go = '0' then -- handle idle timeout counter
|
781 |
|
|
n.itocnt := r.itoval; -- if ito_go=0, keep at start value
|
782 |
|
|
else
|
783 |
|
|
if CE_INT = '1' then
|
784 |
|
|
n.itocnt := unsigned(r.itocnt) - 1;-- otherwise count down every CE_INT
|
785 |
|
|
end if;
|
786 |
|
|
end if;
|
787 |
|
|
|
788 |
|
|
N_REGS <= n;
|
789 |
|
|
|
790 |
|
|
CP_BUSY <= ibusy;
|
791 |
|
|
CP_DO <= ido;
|
792 |
|
|
CP_VAL <= ival;
|
793 |
|
|
CP_FLUSH <= r.flush;
|
794 |
|
|
|
795 |
|
|
RB_MREQ <= rb_mreq_init;
|
796 |
|
|
RB_MREQ.req <= r.rbreq;
|
797 |
|
|
RB_MREQ.we <= r.rbwe;
|
798 |
|
|
RB_MREQ.init <= r.rbinit;
|
799 |
|
|
RB_MREQ.addr <= r.addr;
|
800 |
|
|
RB_MREQ.din <= r.dih & r.dil;
|
801 |
|
|
|
802 |
|
|
CRC_RESET <= crcreset;
|
803 |
|
|
ICRC_ENA <= icrcena;
|
804 |
|
|
OCRC_ENA <= ocrcena;
|
805 |
|
|
OCRC_IN <= ido(7 downto 0);
|
806 |
|
|
|
807 |
|
|
end process proc_next;
|
808 |
|
|
|
809 |
|
|
end syn;
|