Subversion Repositories w11

-- $Id: rlink_core.vhd 799 2016-08-21 09:20:19Z mueller $

--

-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>

--

-- This program is free software; you may redistribute and/or modify it under

-- the terms of the GNU General Public License as published by the Free

-- Software Foundation, either version 2, or at your option any later version.

--

-- This program is distributed in the hope that it will be useful, but

-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY

-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

-- for complete details.

-- 

------------------------------------------------------------------------------

-- Module Name:    rlink_core - syn

-- Description:    rlink core with 9bit interface (with rlmon+rbmon)

--

-- Dependencies:   memlib/ram_2swsr_rfirst_gen

--                 memlib/fifo_1c_dram

--                 comlib/crc16

--                 rb_sel

--                 rb_sres_or_2

--                 rlink_mon_sb    [sim only]

--                 rbus/rb_mon_sb  [sim only]

--

-- Test bench:     tb/tb_rlink_direct

--                 tb/tb_rlink_serport

--                 tb/tb_rlink_tba_ttcombo

--

-- Target Devices: generic

-- Tool versions:  ise 8.2-14.7; viv 2014.4-2016.2; ghdl 0.18-0.33

--

-- Synthesized (xst):

-- Date         Rev  ise         Target      flop lutl lutm slic t peri

-- 2015-12-26   718 14.7  131013 xc6slx16-2   312  460   16  150 s  7.0 ver 4.1

-- 2014-12-20   614 14.7  131013 xc6slx16-2   310  453   16  146 s  6.8 ver 4.0

-- 2014-08-13   581 14.7  131013 xc6slx16-2   160  230    0   73 s  6.0 ver 3.0

-- 2014-08-13   581 14.7  131013 xc3s1000-4   160  358    0  221 s  8.9 ver 3.0

--

-- Revision History: 

-- Date         Rev Version  Comment

-- 2016-08-18   799   4.1.3  remove 'assert false' from report statements

-- 2016-05-22   767   4.1.2  don't init N_REGS (vivado fix for fsm inference)

-- 2015-12-26   718   4.1.1  add proc_sres: strip 'x' from RB_SRES.dout

-- 2014-12-21   617   4.1    use stat(_rbf_rbtout) to signal rbus timeout

-- 2014-12-20   614   4.0    largely rewritten; 2 FSMs; v3 protocol; 4 bit STAT

-- 2014-08-15   583   3.5    rb_mreq addr now 16 bit; add s_rxaddrl state

-- 2011-11-19   427   3.1.3  now numeric_std clean

-- 2010-12-25   348   3.1.2  drop RL_FLUSH support, add RL_MONI for rlink_core;

-- 2010-12-24   347   3.1.1  rename: CP_*->RL->*

-- 2010-12-22   346   3.1    wblk dcrc error: send nak, transit to s_error now;

--                           rename stat flags: [cd]crc->[cd]err, ioto->rbnak,

--                           ioerr->rberr; '111' cmd now aborts via s_txnak and

--                           sets cerr flag; set [cd]err on eop/nak aborts;

-- 2010-12-04   343   3.0    renamed rri_ -> rlink_; rbus V3 interface: use now

--                           aval,re,we; add new states: s_rstart, s_wstart

-- 2010-06-20   308   2.6    use rbinit,rbreq,rbwe state flops to drive rb_mreq;

--                           now nak on reserved cmd 111; use do_comma_abort();

-- 2010-06-18   306   2.5.1  rename rbus data fields to _rbf_

-- 2010-06-06   302   2.5    use sop/eop framing instead of soc+chaining

-- 2010-06-03   299   2.1.2  drop unneeded unsigned casts; change init encoding

-- 2010-05-02   287   2.1.1  ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM

--                           drop RP_IINT signal from interfaces

-- 2010-04-03   274   2.1    add CP_FLUSH output

-- 2009-07-12   233   2.0.1  remove snoopers

-- 2008-08-24   162   2.0    with new rb_mreq/rb_sres interface

-- 2008-03-02   121   1.1.1  comment out snoopers

-- 2007-11-24    98   1.1    new internal init handling (addr=11111111)

-- 2007-10-12    88   1.0.1  avoid ieee.std_logic_unsigned, use cast to unsigned

-- 2007-09-15    82   1.0    Initial version, fully functional

-- 2007-06-17    58   0.5    First preliminary version

------------------------------------------------------------------------------

--  7 supported commands:

--    nak aborts to _txnak are indicated as [nak:<nakcode>]

--    commands to rbus engine are indicated as [bcmd:<bfunc>]

--

--   000 read reg (rreg):

--        rx: cmd al ah ccrcl ccrch

--        tx: cmd dl dh stat crcl crch

--       seq: _rxcmd _rxaddrl _rxaddrh

--            _rxccrcl[nak:ccrc] _rxccrch[nak:ccrc] _txcmd

--            _rstart[bcmd:rblk] {_txdat}*

--            _txstat _txcrcl[nak:rtovfl] -> _txcrch -> _rxcmd

--

--   001 read blk (rblk):

--        rx: cmd al ah cl ch ccrcl ccrch

--        tx: cmd cnt dl dh ... dcl dch stat crcl crch

--       seq: _rxcmd _rxaddrl _rxaddrh _rxcntl _rxcnth

--            _rxccrcl[nak:ccrc] _rxccrch[nak:ccrc] _txcmd

--            _txcntl _txcnth _rstart[bcmd:rblk] {_txdat}* _txdcntl _txdcnth

--            _txstat _txcrcl[nak:rtovfl] -> _txcrch -> _rxcmd

--

--   010 write reg (wreg):

--        rx: cmd al ah dl dh ccrcl ccrch

--        tx: cmd stat crcl crch

--       seq: _rxcmd _rxaddrl _rxaddrh _rxdatl _rxdath

--            _rxccrcl[nak:ccrc] _rxccrch[nak:ccrc] _txcmd

--            _txcmd[bcmd:wblk] _wwait0

--            _txstat _txcrcl[nak:rtovfl] -> _txcrch -> _rxcmd

--

--   011 write blk (wblk):

--        rx: cmd al ah cnt ccrcl ccrch dl dh ... dcrcl dcrch

--        tx: cmd dcl dch stat crcl crch

--       seq: _rxcmd _rxaddrl _rxaddrh _rxcntl _rxcnth

--            _rxccrcl[nak:ccrc] _rxccrch[nak:ccrc] _txcmd

--            _wblk {_rxwblk}* _rxdcrc[nak:dcrc,rtwblk]

--            _wblk0 _wblk1 _wblk2[bcmd:wblk] {_wblkl _wblkh}*

--            _wwait0 _wwait1 _txdcntl _txdcnth

--            _txstat _txcrcl[nak:rtovfl] -> _txcrch -> _rxcmd

--

--   100 list abort (labo):

--        rx: cmd ccrcl ccrch

--        tx: cmd babo stat crcl crch

--       seq: _rxcmd 

--            _rxccrcl[nak:ccrc] _rxccrch[nak:ccrc] _txcmd

--            _txlabo

--            _txstat_txcrcl[nak:rtovfl] -> _txcrch -> [_rxcmd|_rxeop]

--

--   101 read attn (attn):

--        rx: cmd ccrcl ccrch

--        tx: cmd dl dh stat crcl crch

--       seq: _rxcmd

--            _rxccrcl[nak:ccrc] _rxccrch[nak:ccrc] _txcmd

--            _attn _txcntl _txcnth

--            _txstat _txcrcl[nak:rtovfl] -> _txcrch -> _rxcmd

--

--   110 write init (init):

--        rx: cmd al ah dl dh ccrcl ccrch

--        tx: cmd stat crcl crch

--       seq: _rxcmd _rxaddrl _rxaddrh _rxdatl _rxdath

--            _rxccrcl[nak:ccrc] _rxccrch[nak:ccrc] _txcmd[bcmd:init]

--            _txstat _txcrc[nak:rtovfl] -> _rxcmd

--

--   111 is currently not a legal command and causes a nak

--       seq: _txnak

--

-- The different rbus cycle types are encoded as:

--

--        init aval re we

--          0    0   0  0   idle

--          0    1   1  0   read 

--          0    1   0  1   write

--          1    0   0  0   init

--          0    0   1  0   not allowed

--          0    0   0  1   not allowed

--          1    0   0  1   not allowed

--          1    0   1  0   not allowed

--          *    *   1  1   not allowed

--          1    1   *  *   not allowed

--

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use work.slvtypes.all;

use work.memlib.all;

use work.comlib.all;

use work.rblib.all;

use work.rlinklib.all;

entity rlink_core is                    -- rlink core with 9bit interface

  generic (

    BTOWIDTH : positive :=  5;          -- rbus timeout counter width

    RTAWIDTH : positive :=  12;         -- retransmit buffer address width

    SYSID : slv32 := (others=>'0');     -- rlink system id

    ENAPIN_RLMON : integer := -1;       -- SB_CNTL for rlmon  (-1=none)

    ENAPIN_RBMON : integer := -1);      -- SB_CNTL for rbmon  (-1=none)

  port (

    CLK  : in slbit;                    -- clock      

    CE_INT : in slbit := '0';           -- rri ato time unit clock enable

    RESET  : in slbit;                  -- reset

    RL_DI : in slv9;                    -- rlink 9b: data in

    RL_ENA : in slbit;                  -- rlink 9b: data enable

    RL_BUSY : out slbit;                -- rlink 9b: data busy

    RL_DO : out slv9;                   -- rlink 9b: data out

    RL_VAL : out slbit;                 -- rlink 9b: data valid

    RL_HOLD : in slbit;                 -- rlink 9b: data hold

    RL_MONI : out rl_moni_type;         -- rlink: monitor port

    RB_MREQ : out rb_mreq_type;         -- rbus: request

    RB_SRES : in rb_sres_type;          -- rbus: response

    RB_LAM : in slv16;                  -- rbus: look at me

    RB_STAT : in slv4                   -- rbus: status flags

  );

  attribute fsm_encoding : string;

  attribute fsm_encoding of rlink_core : entity is "one-hot";

end entity rlink_core;

architecture syn of rlink_core is

   -- core config registers (top 4 in rbus space)

  constant rbaddr : slv16 := x"fffc";    -- fffc/4: 1111 1111 1111 11xx

  constant rbaddr_cntl : slv2 := "11";   -- cntl address offset

  constant rbaddr_stat : slv2 := "10";   -- stat address offset

  constant rbaddr_id1  : slv2 := "01";   -- id1  address offset

  constant rbaddr_id0  : slv2 := "00";   -- id0  address offset

  constant d_f_cflag   : integer := 8;                -- d9: comma flag

  subtype  d_f_ctyp   is integer range  2 downto  0;  -- d9: comma type

  subtype  d_f_data   is integer range  7 downto  0;  -- d9: data field

  subtype  f_byte1    is integer range 15 downto 8;

  subtype  f_byte0    is integer range  7 downto 0;

  constant cntl_rbf_anena    : integer := 15;               -- anena flag

  constant cntl_rbf_atoena   : integer := 14;               -- atoena flag

  subtype  cntl_rbf_atoval  is integer range  7 downto  0;  -- atoval value

  subtype  stat_rbf_lcmd    is integer range 15 downto  8;  -- lcmd

  constant stat_rbf_babo     : integer :=  7;               -- block abort flag

  constant stat_rbf_arpend   : integer :=  6;               -- attn read pend

  subtype  stat_rbf_rbsize  is integer range  2 downto  0;  -- rbuf size

  -- following 4 constants can derived from c_rlink_dat_sop,...

  -- defined directly here to work around a ghdl bug

  constant c_sop  : slv3 := "000";

  constant c_eop  : slv3 := "001";

  constant c_nak  : slv3 := "010";

  constant c_attn : slv3 := "011";

  constant c_bcmd_stat : slv2 := "00";

  constant c_bcmd_init : slv2 := "01";

  constant c_bcmd_rblk : slv2 := "10";

  constant c_bcmd_wblk : slv2 := "11";

  constant cntawidth : positive := RTAWIDTH-1;        -- cnt is word count

  subtype  cnt_f_dat  is integer range cntawidth-1 downto  0;   -- cnt data

  -- link FSM states and state vector ----------------------------------------

  type lstate_type is (

    sl_idle,                            -- sl_idle: wait for sop

    sl_txanot,                          -- sl_txanot: send attn notify

    sl_txsop,                           -- sl_txsop: send sop

    sl_txnak,                           -- sl_txnak: send nak

    sl_txnakcode,                       -- sl_txnakcode: send nakcode

    sl_txrtbuf,                         -- sl_txrtbuf: send rtbuf

    sl_txeop,                           -- sl_txeop: send eop

    sl_rxeop,                           -- sl_rxeop: wait for eop

    sl_rxcmd,                           -- sl_rxcmd: wait for cmd

    sl_rxaddrl,                         -- sl_rxaddrl: wait for addr low

    sl_rxaddrh,                         -- sl_rxaddrh: wait for addr high

    sl_rxdatl,                          -- sl_rxdatl: wait for data low

    sl_rxdath,                          -- sl_rxdath: wait for data high

    sl_rxcntl,                          -- sl_rxcntl: wait for count low

    sl_rxcnth,                          -- sl_rxcnth: wait for count low

    sl_rxccrcl,                         -- sl_rxccrcl: wait for command crc low

    sl_rxccrch,                         -- sl_rxccrcl: wait for command crc high

    sl_txcmd,                           -- sl_txcmd: send cmd

    sl_txcntl,                          -- sl_txcntl: send cnt lsb

    sl_txcnth,                          -- sl_txcnth: send cnt msb

    sl_rstart,                          -- sl_rstart: start rreg or rblk

    sl_txdat,                           -- sl_txdat: send data

    sl_wblk,                            -- sl_wblk: setup rx wblk data

    sl_rxwblk,                          -- sl_rxwblk: wait for wblk data

    sl_rxdcrcl,                         -- sl_rxdcrcl: wait for data crc low

    sl_rxdcrch,                         -- sl_rxdcrch: wait for data crc high

    sl_wblk0,                           -- sl_wblk0: start wblk pipe

    sl_wblk1,                           -- sl_wblk1: start wblk data lsb

    sl_wblk2,                           -- sl_wblk2: start wblk data msb

    sl_wblkl,                           -- sl_wblkl: wblk data lsb

    sl_wblkh,                           -- sl_wblkh: wblk data msb

    sl_wwait0,                          -- sl_wwait0: wait for wdone

    sl_wwait1,                          -- sl_wwait1: wait for dcnt

    sl_txdcntl,                         -- sl_txdcntl: send dcnt lsb

    sl_txdcnth,                         -- sl_txdcnth: send dcnt lsb

    sl_txlabo,                          -- sl_txlabo: send labo flag

    sl_attn,                            -- sl_attn: handle attention flags

    sl_txstat,                          -- sl_txstat: send status

    sl_txcrcl,                          -- sl_txcrcl: send crc low

    sl_txcrch                           -- sl_txcrch: send crc high

  );

  type lregs_type is record

    state : lstate_type;                -- state

    rcmd : slv8;                        -- received command

    lcmd : slv8;                        -- last command

    addr : slv16;                       -- rbus register address

    din : slv16;                        -- rbus input data

    cnt : slv16;                        -- block transfer count

    bcnt : slv(RTAWIDTH-1 downto 0);    -- blk counter (byte and word)

    attn : slv16;                       -- attn mask

    anreq : slbit;                      -- attn notify request

    anact : slbit;                      -- attn notify active

    arpend : slbit;                     -- attn read pending

    atocnt : slv8;                      -- attn timeout counter

    babo : slbit;                       -- last blk aborted

    nakdone : slbit;                    -- nak done

    nakcode : slv3;                     -- nak code

    cmdseen : slbit;                    -- 1st command seen

    doretra : slbit;                    -- do a retransmit

    dinl : slv8;                        -- din lsb for wblk pipeline

    rtaddra : slv(RTAWIDTH-1 downto 0); -- rtbuf port a addr (write pointer)

    rtaddra_red : slbit;                -- rtaddra red (at max)

    rtaddra_bad : slbit;                -- rtaddra bad (inc beyond max)

    rtaddrb : slv(RTAWIDTH-1 downto 0); -- rtbuf port b addr (aux pointer)

    rtaddrb_red : slbit;                -- rtaddrb red (at max)

    rtaddrb_bad : slbit;                -- rtaddrb bad (inc beyond max)

    moneop : slbit;                     -- rl_moni: eop send pulse

    monattn : slbit;                    -- rl_moni: attn send pulse

  end record lregs_type;

  constant bcnt_zero   : slv(RTAWIDTH-1 downto 0) := (others=>'0');

  constant rtaddr_zero : slv(RTAWIDTH-1 downto 0) := (others=>'0');

  constant rtaddr_tred : slv(RTAWIDTH-1 downto 0) := (0=>'0', others=>'1');

  constant lregs_init : lregs_type := (

    sl_idle,                            -- state

    (others=>'0'),                      -- rcmd

    (others=>'1'),                      -- lcmd

    (others=>'0'),                      -- addr

    (others=>'0'),                      -- din

    (others=>'0'),                      -- cnt

    bcnt_zero,                          -- bcnt

    (others=>'0'),                      -- attn

    '0','0','0',                        -- anreq,anact,arpend

    (others=>'0'),                      -- atocnt

    '0',                                -- babo

    '0',                                -- nakdone

    (others=>'0'),                      -- nakcode

    '0','0',                            -- cmdseen,doretra

    (others=>'0'),                      -- dinl

    rtaddr_zero,                        -- rtaddra

    '0','0',                            -- rtaddra_red, rtaddra_bad

    rtaddr_zero,                        -- rtaddrb

    '0','0',                            -- rtaddrb_red, rtaddrb_bad

    '0','0'                             -- moneop,monattn

  );

  -- bus FSM states and state vector -----------------------------------------

  type bstate_type is (

    sb_idle,                            -- sb_idle: wait for cmd

    sb_rstart,                          -- sb_rstart: start rblk

    sb_rreg0,                           -- sb_rreg0: rbus read cycle

    sb_rreg1,                           -- sb_rreg1: send read data

    sb_rwait,                           -- sb_rwait: wait for fifo

    sb_rend,                            -- sb_rend: send last read data

    sb_rabo0,                           -- sb_rabo0: rblk abort, lsb data

    sb_rabo1,                           -- sb_rabo1: rblk abort, msb data

    sb_wstart,                          -- sb_wstart: start wblk

    sb_wreg0,                           -- sb_wreg0: rbus write cycle

    sb_wreg1,                           -- sb_wreg1: wait write data

    sb_wabo0,                           -- sb_wabo0: wblk abort, drop data

    sb_wabo1                            -- sb_wabo1: wblk abort, wait

  );

  type bregs_type is record

    state : bstate_type;                -- state

    rbinit : slbit;                     -- rbus init signal

    rbaval : slbit;                     -- rbus aval signal

    rbre : slbit;                       -- rbus re signal

    rbwe : slbit;                       -- rbus we signal

    rbdout : slv16;                     -- rbus dout

    rbtout: slbit;                      -- rbus timeout

    rbnak: slbit;                       -- rbus no ack

    rberr : slbit;                      -- rbus err bit set

    blkabo : slbit;                     -- blk abort

    cnt : slv(cntawidth-1 downto 0);    -- word count for rblk and wblk

    dcnt : slv(cntawidth-1 downto 0);   -- done count for rblk and wblk

    btocnt : slv(BTOWIDTH-1 downto 0);  -- rbus timeout counter

    dathpend : slbit;                   -- dat msb pending

    wfifo : slbit;                      -- wait for fifo

    stat : slv4;                        -- external status flags

  end record bregs_type;

  constant btocnt_init : slv(BTOWIDTH-1 downto 0) := (others=>'1');

  constant cnt_zero    : slv(cntawidth-1 downto 0) := (others=>'0');

  constant bregs_init : bregs_type := (

    sb_idle,                            -- state

    '0','0','0','0',                    -- rbinit,rbaval,rbre,rbwe

    (others=>'0'),                      -- rbdout

    '0','0','0',                        -- rbtout,rbnak,rberr

    '0',                                -- blkabo

    cnt_zero,                           -- cnt

    cnt_zero,                           -- dcnt

    btocnt_init,                        -- btocnt

    '0','0',                            -- dathpend,wfifo

    (others=>'0')                       -- stat

  );

  -- config state regs --------------------------------------------------------

  type cregs_type is record

    anena : slbit;                      -- attn notification enable flag

    atoena : slbit;                     -- attn timeout enable flag

    atoval : slv8;                      -- attn timeout value

  end record cregs_type;

  constant cregs_init : cregs_type := (

    '0','0',                            -- anena,atoena

    (others=>'0')                       -- atoval

  );

  signal R_LREGS : lregs_type := lregs_init;  -- state registers link FSM

  signal N_LREGS : lregs_type;         -- don't init (vivado fix for fsm infer)

  signal R_BREGS : bregs_type := bregs_init;  -- state registers bus FSM

  signal N_BREGS : bregs_type;         -- don't init (vivado fix for fsm infer)

  signal R_CREGS : cregs_type := cregs_init;  -- state registers config

  signal N_CREGS : cregs_type := cregs_init;  -- next value state regs config

  signal RTBUF_ENB : slbit := '0';

  signal RTBUF_WEA : slbit := '0';

  signal RTBUF_WEB : slbit := '0';

  signal RTBUF_DIA : slv8 := (others=>'0');

  signal RTBUF_DIB : slv8 := (others=>'0');

  signal RTBUF_DOB : slv8 := (others=>'0');

  signal DOFIFO_DI   : slv8  := (others=>'0');

  signal DOFIFO_ENA  : slbit := '0';

  signal DOFIFO_DO   : slv8  := (others=>'0');

  signal DOFIFO_VAL  : slbit := '0';

  signal DOFIFO_HOLD : slbit := '0';

  signal DOFIFO_SIZE : slv6  := (others=>'0');

  signal CRC_RESET : slbit := '0';

  signal ICRC_ENA  : slbit := '0';

  signal OCRC_ENA  : slbit := '0';

  signal ICRC_OUT  : slv16 := (others=>'0');

  signal OCRC_OUT  : slv16 := (others=>'0');

  signal OCRC_IN   : slv8  := (others=>'0');

  signal RBSEL : slbit := '0';

  signal RB_MREQ_L     : rb_mreq_type := rb_mreq_init;  -- internal mreq

  signal RB_SRES_CLEAN : rb_sres_type := rb_sres_init;  -- cleaned rb_sres

  signal RB_SRES_CONF  : rb_sres_type := rb_sres_init;  -- config sres

  signal RB_SRES_TOT   : rb_sres_type := rb_sres_init;  -- total  sres

  signal RL_BUSY_L : slbit := '0';

  signal RL_DO_L   : slv9  := (others=>'0');

  signal RL_VAL_L  : slbit := '0';

  signal L2B_GO    : slbit := '0';

  signal L2B_CMD  : slv2 := (others=>'0');

  signal B2L_WDONE : slbit := '0';

begin

  -- allow 11 bit (1 x 18kbit BRAM) to 15 bit (8 x 36 kbit BRAMs)

  assert RTAWIDTH>=11 and RTAWIDTH<=14

    report "assert(RTAWIDTH>=11 and RTAWIDTH<=15): unsupported RTAWIDTH"

    severity failure;

  RTBUF : ram_2swsr_rfirst_gen

    generic map (

      AWIDTH => RTAWIDTH,

      DWIDTH =>  8)

    port map (

      CLKA  => CLK,

      CLKB  => CLK,

      ENA   => RTBUF_WEA,               -- port A write only, thus en=we

      ENB   => RTBUF_ENB,

      WEA   => RTBUF_WEA,

      WEB   => RTBUF_WEB,

      ADDRA => R_LREGS.rtaddra,

      ADDRB => R_LREGS.rtaddrb,

      DIA   => RTBUF_DIA,

      DIB   => RTBUF_DIB,

      DOA   => open,

      DOB   => RTBUF_DOB

      );

  DOFIFO : fifo_1c_dram

    generic map (

      AWIDTH => 5,

      DWIDTH => 8)

    port map (

      CLK   => CLK,

      RESET => RESET,

      DI    => DOFIFO_DI,

      ENA   => DOFIFO_ENA,

      BUSY  => open,

      DO    => DOFIFO_DO,

      VAL   => DOFIFO_VAL,

      HOLD  => DOFIFO_HOLD,

      SIZE  => DOFIFO_SIZE

    );

  ICRC : crc16                          -- crc generator for input data

    port map (

      CLK   => CLK,

      RESET => CRC_RESET,

      ENA   => ICRC_ENA,

      DI    => RL_DI(d_f_data),

      CRC   => ICRC_OUT

    );

  OCRC : crc16                          -- crc generator for output data

    port map (

      CLK   => CLK,

      RESET => CRC_RESET,

      ENA   => OCRC_ENA,

      DI    => OCRC_IN,

      CRC   => OCRC_OUT

    );

  SEL : rb_sel                          -- rbus address select for config regs

    generic map (

      RB_ADDR => rbaddr,

      SAWIDTH => 2)

    port map (

      CLK     => CLK,

      RB_MREQ => RB_MREQ_L,

      SEL     => RBSEL

    );

  RB_SRES_OR : rb_sres_or_2

    port map (

      RB_SRES_1  => RB_SRES_CLEAN,

      RB_SRES_2  => RB_SRES_CONF,

      RB_SRES_OR => RB_SRES_TOT

    );

  proc_sres: process (RB_SRES)

    variable sres : rb_sres_type := rb_sres_init;

    variable datax01 : slv16 := (others=>'0');

    variable data01  : slv16 := (others=>'0');

  begin

    sres.ack  := to_x01(RB_SRES.ack);

    sres.busy := to_x01(RB_SRES.busy);

    sres.err  := to_x01(RB_SRES.err);

    sres.dout := to_x01(RB_SRES.dout);

    if sres.ack = '1' and sres.busy = '0' and is_x(sres.dout) then

      report "rlink_core: seen 'x' in rb_sres.data"

        severity warning;

      sres.dout := (others=>'1');

    end if;

    RB_SRES_CLEAN <= sres;

  end process proc_sres;

  proc_regs: process (CLK)

  begin

    if rising_edge(CLK) then

      if RESET = '1' then

        R_LREGS <= lregs_init;

        R_BREGS <= bregs_init;

        R_CREGS <= cregs_init;

      else

        R_LREGS <= N_LREGS;

        R_BREGS <= N_BREGS;

        R_CREGS <= N_CREGS;

     end if;

    end if;

  end process proc_regs;

  -- link FSM ================================================================

  proc_lnext: process (R_LREGS, R_CREGS, R_BREGS,

                       CE_INT, RL_DI, RL_ENA, RL_HOLD, RB_LAM,

                       ICRC_OUT, OCRC_OUT, RTBUF_DOB,

                       DOFIFO_DO, DOFIFO_VAL,

                       B2L_WDONE)

    variable r : lregs_type := lregs_init;

    variable n : lregs_type := lregs_init;

    variable ival : slbit := '0';

    variable ibusy : slbit := '0';

    variable ido : slv9 := (others=>'0');

    variable crcreset : slbit := '0';

    variable icrcena : slbit := '0';

    variable ocrcena : slbit := '0';

    variable has_attn : slbit := '0';

    variable idi8 : slv8 := (others=>'0');

    variable is_comma : slbit := '0';

    variable comma_typ : slv3 := "000";

    variable idohold : slbit := '0';

    variable cnt_iszero : slbit := '0';

    variable bcnt_load : slbit := '0';

    variable bcnt_val : slv(RTAWIDTH-1 downto 0) := (others=>'0');

    variable bcnt_dec : slbit := '0';

    variable bcnt_end : slbit := '0';

    variable irtwea : slbit := '0';

    variable irtreb : slbit := '0';

    variable irtweb : slbit := '0';

    variable addra_clear : slbit := '0';

    variable addrb_load  : slbit := '0';

    variable addrb_sela  : slbit := '0';

    variable ibcmd : slv2 := (others=>'0');

    variable ibgo  : slbit := '0';

  begin

    r := R_LREGS;

    n := R_LREGS;

    n.moneop  := '0';                   -- default '0', only set by states

    n.monattn := '0';                   -- "

    ival := '0';

    ibusy := '1';                       -- default is to hold input

    ido  := (others=>'0');

    crcreset := '0';

    icrcena  := '0';

    ocrcena  := '0';

    has_attn := '0';

    is_comma  := RL_DI(d_f_cflag);      -- get comma marker

    comma_typ := RL_DI(d_f_ctyp);       -- get comma type

    idi8      := RL_DI(d_f_data);       -- get data part of RL_DI

    idohold := '1';                     -- default is to hold DOFIFO

    cnt_iszero := '0';

    if unsigned(r.cnt(cnt_f_dat)) = 0 then

      cnt_iszero := '1';

    end if;

    bcnt_load := '0';

    bcnt_val  := r.cnt(cnt_f_dat) & '0'; -- default: 2*cnt (most used)

    bcnt_dec  := '0';

    bcnt_end  := '0';

    if unsigned(r.bcnt) = 1 then

      bcnt_end := '1';

    end if;

    irtwea  := '0';

    irtreb  := '0';

    irtweb  := '0';

    addra_clear := '0';

    addrb_load  := '0';

    addrb_sela  := '1';           -- default: addra (most used)

    ibcmd := (others=>'0');

    ibgo := '0';

    -- handle attention "LAM's"

    n.attn := r.attn or RB_LAM;

    -- detect attn notify requests

    if unsigned(r.attn) /= 0 then       -- if any of the attn bits set

      has_attn  := '1';

      if R_CREGS.anena='1' and r.arpend='0' then -- if attn to be send

        n.anreq := '1';                      -- set notify request flag

      end if;

    end if;

    -- handle attn read timeouts

    --  atocnt is held in reset when no attn read is pending

    --    counting down in CE_INT cycles till zero

    --    when zero, an attn notify is requested when atoena is set

    --    the attn notify flag will reset atocnt to its start value

    --    --> when atoena='1' this creates a notify every atoval CE_INT periods

    --    --> when atoena='0' atocnt will count to zero and stay there

    if r.arpend = '0' or r.anreq = '1' then   -- if no attn read pending

      n.atocnt := R_CREGS.atoval;         -- keep at start value

    else                                -- otherwise

      if CE_INT = '1' then                -- if CE_INT

        if unsigned(r.atocnt) = 0 then      -- alread counted down 

          n.anreq :=  R_CREGS.atoena;         -- request attn notify if enabled

        else                                -- not yet down

          n.atocnt := slv(unsigned(r.atocnt) - 1);  -- decrement

        end if;

      end if;

    end if;

    case r.state is

      when sl_idle =>                   -- sl_idle: wait for sop -------------