1 |
36 |
wfjm |
-- $Id: rlink_sp2c.vhd 755 2016-03-28 17:59:59Z mueller $
|
2 |
|
|
--
|
3 |
|
|
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
4 |
|
|
--
|
5 |
|
|
-- This program is free software; you may redistribute and/or modify it under
|
6 |
|
|
-- the terms of the GNU General Public License as published by the Free
|
7 |
|
|
-- Software Foundation, either version 2, or at your option any later version.
|
8 |
|
|
--
|
9 |
|
|
-- This program is distributed in the hope that it will be useful, but
|
10 |
|
|
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
|
11 |
|
|
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
12 |
|
|
-- for complete details.
|
13 |
|
|
--
|
14 |
|
|
------------------------------------------------------------------------------
|
15 |
|
|
-- Module Name: rlink_sp2c - syn
|
16 |
|
|
-- Description: rlink_core8 + serport_2clock2 combo
|
17 |
|
|
--
|
18 |
|
|
-- Dependencies: rlink_core8
|
19 |
|
|
-- serport/serport_2clock2
|
20 |
|
|
-- rbus/rbd_rbmon
|
21 |
|
|
-- rbus/rb_sres_or_2
|
22 |
|
|
--
|
23 |
|
|
-- Test bench: -
|
24 |
|
|
--
|
25 |
|
|
-- Target Devices: generic
|
26 |
|
|
-- Tool versions: viv 2015.4; ghdl 0.33
|
27 |
|
|
--
|
28 |
|
|
-- Revision History:
|
29 |
|
|
-- Date Rev Version Comment
|
30 |
|
|
-- 2016-03-28 755 1.0 Initial version (derived from rlink_sp1c)
|
31 |
|
|
------------------------------------------------------------------------------
|
32 |
|
|
|
33 |
|
|
library ieee;
|
34 |
|
|
use ieee.std_logic_1164.all;
|
35 |
|
|
use ieee.numeric_std.all;
|
36 |
|
|
|
37 |
|
|
use work.slvtypes.all;
|
38 |
|
|
use work.rblib.all;
|
39 |
|
|
use work.rbdlib.all;
|
40 |
|
|
use work.rlinklib.all;
|
41 |
|
|
use work.serportlib.all;
|
42 |
|
|
|
43 |
|
|
entity rlink_sp2c is -- rlink_core8+serport_2clock2 combo
|
44 |
|
|
generic (
|
45 |
|
|
BTOWIDTH : positive := 5; -- rbus timeout counter width
|
46 |
|
|
RTAWIDTH : positive := 12; -- retransmit buffer address width
|
47 |
|
|
SYSID : slv32 := (others=>'0'); -- rlink system id
|
48 |
|
|
IFAWIDTH : natural := 5; -- input fifo address width (0=none)
|
49 |
|
|
OFAWIDTH : natural := 5; -- output fifo address width (0=none)
|
50 |
|
|
ENAPIN_RLMON : integer := -1; -- SB_CNTL for rlmon (-1=none)
|
51 |
|
|
ENAPIN_RLBMON: integer := -1; -- SB_CNTL for rlbmon (-1=none)
|
52 |
|
|
ENAPIN_RBMON : integer := -1; -- SB_CNTL for rbmon (-1=none)
|
53 |
|
|
CDWIDTH : positive := 13; -- clk divider width
|
54 |
|
|
CDINIT : natural := 15; -- clk divider initial/reset setting
|
55 |
|
|
RBMON_AWIDTH : natural := 0; -- rbmon: buffer size, (0=none)
|
56 |
|
|
RBMON_RBADDR : slv16 := slv(to_unsigned(16#ffe8#,16))); -- rbmon: base addr
|
57 |
|
|
port (
|
58 |
|
|
CLK : in slbit; -- U|clock (user design)
|
59 |
|
|
CE_USEC : in slbit; -- U|1 usec clock enable
|
60 |
|
|
CE_MSEC : in slbit; -- U|1 msec clock enable
|
61 |
|
|
CE_INT : in slbit := '0'; -- U|rri ato time unit clock enable
|
62 |
|
|
RESET : in slbit; -- U|reset
|
63 |
|
|
CLKS : in slbit; -- S|clock (frontend:serial)
|
64 |
|
|
CES_MSEC : in slbit; -- S|1 msec clock enable
|
65 |
|
|
ENAXON : in slbit; -- U|enable xon/xoff handling
|
66 |
|
|
ESCFILL : in slbit; -- U|enable fill escaping
|
67 |
|
|
RXSD : in slbit; -- S|receive serial data (board view)
|
68 |
|
|
TXSD : out slbit; -- S|transmit serial data (board view)
|
69 |
|
|
CTS_N : in slbit := '0'; -- S|clear to send (act.low, board view)
|
70 |
|
|
RTS_N : out slbit; -- S|request to send (act.low, brd view)
|
71 |
|
|
RB_MREQ : out rb_mreq_type; -- U|rbus: request
|
72 |
|
|
RB_SRES : in rb_sres_type; -- U|rbus: response
|
73 |
|
|
RB_LAM : in slv16; -- U|rbus: look at me
|
74 |
|
|
RB_STAT : in slv4; -- U|rbus: status flags
|
75 |
|
|
RL_MONI : out rl_moni_type; -- U|rlink_core: monitor port
|
76 |
|
|
SER_MONI : out serport_moni_type -- U|serport: monitor port
|
77 |
|
|
);
|
78 |
|
|
end entity rlink_sp2c;
|
79 |
|
|
|
80 |
|
|
|
81 |
|
|
architecture syn of rlink_sp2c is
|
82 |
|
|
|
83 |
|
|
signal RLB_DI : slv8 := (others=>'0');
|
84 |
|
|
signal RLB_ENA : slbit := '0';
|
85 |
|
|
signal RLB_BUSY : slbit := '0';
|
86 |
|
|
signal RLB_DO : slv8 := (others=>'0');
|
87 |
|
|
signal RLB_VAL : slbit := '0';
|
88 |
|
|
signal RLB_HOLD : slbit := '0';
|
89 |
|
|
|
90 |
|
|
signal RB_MREQ_M : rb_mreq_type := rb_mreq_init;
|
91 |
|
|
signal RB_SRES_M : rb_sres_type := rb_sres_init;
|
92 |
|
|
signal RB_SRES_RBMON : rb_sres_type := rb_sres_init;
|
93 |
|
|
|
94 |
|
|
begin
|
95 |
|
|
|
96 |
|
|
CORE : rlink_core8 -- rlink master ----------------------
|
97 |
|
|
generic map (
|
98 |
|
|
BTOWIDTH => BTOWIDTH,
|
99 |
|
|
RTAWIDTH => RTAWIDTH,
|
100 |
|
|
SYSID => SYSID,
|
101 |
|
|
ENAPIN_RLMON => ENAPIN_RLMON,
|
102 |
|
|
ENAPIN_RLBMON=> ENAPIN_RLBMON,
|
103 |
|
|
ENAPIN_RBMON => ENAPIN_RBMON)
|
104 |
|
|
port map (
|
105 |
|
|
CLK => CLK,
|
106 |
|
|
CE_INT => CE_INT,
|
107 |
|
|
RESET => RESET,
|
108 |
|
|
ESCXON => ENAXON,
|
109 |
|
|
ESCFILL => ESCFILL,
|
110 |
|
|
RLB_DI => RLB_DI,
|
111 |
|
|
RLB_ENA => RLB_ENA,
|
112 |
|
|
RLB_BUSY => RLB_BUSY,
|
113 |
|
|
RLB_DO => RLB_DO,
|
114 |
|
|
RLB_VAL => RLB_VAL,
|
115 |
|
|
RLB_HOLD => RLB_HOLD,
|
116 |
|
|
RL_MONI => RL_MONI,
|
117 |
|
|
RB_MREQ => RB_MREQ_M,
|
118 |
|
|
RB_SRES => RB_SRES_M,
|
119 |
|
|
RB_LAM => RB_LAM,
|
120 |
|
|
RB_STAT => RB_STAT
|
121 |
|
|
);
|
122 |
|
|
|
123 |
|
|
SERPORT : serport_2clock2 -- serport interface -----------------
|
124 |
|
|
generic map (
|
125 |
|
|
CDWIDTH => CDWIDTH,
|
126 |
|
|
CDINIT => CDINIT,
|
127 |
|
|
RXFAWIDTH => IFAWIDTH,
|
128 |
|
|
TXFAWIDTH => OFAWIDTH)
|
129 |
|
|
port map (
|
130 |
|
|
CLKU => CLK,
|
131 |
|
|
RESET => RESET,
|
132 |
|
|
CLKS => CLKS,
|
133 |
|
|
CES_MSEC => CES_MSEC,
|
134 |
|
|
ENAXON => ENAXON,
|
135 |
|
|
ENAESC => '0', -- escaping now in rlink_core8
|
136 |
|
|
RXDATA => RLB_DI,
|
137 |
|
|
RXVAL => RLB_ENA,
|
138 |
|
|
RXHOLD => RLB_BUSY,
|
139 |
|
|
TXDATA => RLB_DO,
|
140 |
|
|
TXENA => RLB_VAL,
|
141 |
|
|
TXBUSY => RLB_HOLD,
|
142 |
|
|
MONI => SER_MONI,
|
143 |
|
|
RXSD => RXSD,
|
144 |
|
|
TXSD => TXSD,
|
145 |
|
|
RXRTS_N => RTS_N,
|
146 |
|
|
TXCTS_N => CTS_N
|
147 |
|
|
);
|
148 |
|
|
|
149 |
|
|
RBMON : if RBMON_AWIDTH > 0 generate -- rbus monitor --------------
|
150 |
|
|
begin
|
151 |
|
|
I0 : rbd_rbmon
|
152 |
|
|
generic map (
|
153 |
|
|
RB_ADDR => RBMON_RBADDR,
|
154 |
|
|
AWIDTH => RBMON_AWIDTH)
|
155 |
|
|
port map (
|
156 |
|
|
CLK => CLK,
|
157 |
|
|
RESET => RESET,
|
158 |
|
|
RB_MREQ => RB_MREQ_M,
|
159 |
|
|
RB_SRES => RB_SRES_RBMON,
|
160 |
|
|
RB_SRES_SUM => RB_SRES_M
|
161 |
|
|
);
|
162 |
|
|
end generate RBMON;
|
163 |
|
|
|
164 |
|
|
RB_SRES_OR : rb_sres_or_2 -- rbus or ---------------------------
|
165 |
|
|
port map (
|
166 |
|
|
RB_SRES_1 => RB_SRES,
|
167 |
|
|
RB_SRES_2 => RB_SRES_RBMON,
|
168 |
|
|
RB_SRES_OR => RB_SRES_M
|
169 |
|
|
);
|
170 |
|
|
|
171 |
|
|
RB_MREQ <= RB_MREQ_M; -- setup output signals
|
172 |
|
|
|
173 |
|
|
end syn;
|