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-- $Id: rlink_tba.vhd 595 2014-09-28 08:47:45Z mueller $
--
-- Copyright 2007-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name:    rlink_tba - syn
-- Description:    rlink test bench adapter
--
-- Dependencies:   -
-- Test bench:     -
-- Target Devices: generic [synthesizable, but only used in tb's]
-- Tool versions:  xst 8.2-14.7; ghdl 0.18-0.31
--
-- Revision History: 
-- Date         Rev Version  Comment
-- 2014-09-27   595   4.0    now full rlink v4 iface
-- 2014-08-15   583   3.5    rb_mreq addr now 16 bit; add state r_txal;
-- 2011-11-22   432   3.0.2  now numeric_std clean
-- 2011-11-19   427   3.0.1  fix crc8_update usage;
-- 2010-12-24   347   3.0    rename rritba->rlink_tba, CP_*->RL_*; rbus v3 port;
-- 2010-06-18   306   2.5.1  rename rbus data fields to _rbf_
-- 2010-06-07   302   2.5    use sop/eop framing instead of soc+chaining
-- 2010-05-05   289   1.0.3  drop dead snooper code and unneeded unsigned casts
-- 2008-03-02   121   1.0.2  remove snoopers
-- 2007-10-12    88   1.0.1  avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-09-09    81   1.0    Initial version 
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.slvtypes.all;
use work.comlib.all;
use work.rlinklib.all;
use work.rlinktblib.all;
 
entity rlink_tba is                     -- rlink test bench adapter
  port (
    CLK  : in slbit;                    -- clock
    RESET  : in slbit;                  -- reset
    CNTL : in rlink_tba_cntl_type;      -- control port
    DI : in slv16;                      -- input data
    STAT : out rlink_tba_stat_type;     -- status port
    DO : out slv16;                     -- output data
    RL_DI : out slv9;                   -- rlink: data in
    RL_ENA : out slbit;                 -- rlink: data enable
    RL_BUSY : in slbit;                 -- rlink: data busy
    RL_DO : in slv9;                    -- rlink: data out
    RL_VAL : in slbit;                  -- rlink: data valid
    RL_HOLD : out slbit                 -- rlink: data hold
  );
end entity rlink_tba;
 
 
architecture syn of rlink_tba is
 
  constant d_f_cflag   : integer := 8;                -- d9: comma flag
  subtype  d_f_data   is integer range  7 downto  0;  -- d9: data field
 
  subtype  f_byte1    is integer range 15 downto 8;
  subtype  f_byte0    is integer range  7 downto 0;
 
  type txstate_type is (
    s_txidle,                           -- s_txidle: wait for ENA
    s_txsop,                            -- s_txsop: send sop
    s_txeop,                            -- s_txeop: send eop
    s_txcmd,                            -- s_txcmd: send cmd
    s_txal,                             -- s_txal: send addr lsb
    s_txah,                             -- s_txah: send addr msb
    s_txcl,                             -- s_txcl: send blk count lsb
    s_txch,                             -- s_txcl: send blk count msb
    s_txdl,                             -- s_txdl: send data lsb
    s_txdh,                             -- s_txdh: send data msb
    s_txcrcl1,                          -- s_txcrcl1: send cmd crc lsb in wblk
    s_txcrch1,                          -- s_txcrch1: send cmd crc msb in wblk
    s_txwbld,                           -- s_txwbld: wblk data load
    s_txwbdl,                           -- s_txwbdl: wblk send data lsb
    s_txwbdh,                           -- s_txwbdh: wblk send data msb
    s_txcrcl2,                          -- s_txcrcl2: send final crc lsb
    s_txcrch2                           -- s_txcrch2: send final crc msb
  );
 
  type txregs_type is record
    state : txstate_type;               -- state
    ccmd : slv3;                        -- current command
    snum : slv5;                        -- command sequence number
    crc : slv16;                        -- crc (cmd and data)
    braddr : slv16;                     -- block read address
    bdata : slv16;                      -- block data
    bloop : slbit;                      -- block loop flag
    tcnt : slv16;                       -- tcnt (down count for wblk)
    sopdone : slbit;                    -- sop send
    eoppend : slbit;                    -- eop pending
  end record txregs_type;
 
  constant txregs_init : txregs_type := (
    s_txidle,                           -- state
    "000",                              -- ccmd
    "00000",                            -- snum
    (others=>'0'),                      -- crc
    (others=>'0'),                      -- braddr
    (others=>'0'),                      -- bdata
    '0',                                -- bloop
    (others=>'0'),                      -- tcnt
    '0','0'                             -- sopdone, eoppend
  );
 
  type rxstate_type is (
    s_rxidle,                           -- s_rxidle: wait for ENA
    s_rxcmd,                            -- s_rxcmd: wait cmd
    s_rxcl,                             -- s_rxcl: wait cnt lsb
    s_rxch,                             -- s_rxcl: wait cnt msb
    s_rxbabo,                           -- s_rxbabo: wait babo
    s_rxdcl,                            -- s_rxdcl: wait dcnt lsb
    s_rxdch,                            -- s_rxdch: wait dcnt msb
    s_rxdl,                             -- s_rxdl: wait data lsb
    s_rxdh,                             -- s_rxdh: wait data msb
    s_rxstat,                           -- s_rxstat: wait status
    s_rxcrcl,                           -- s_rxcrcl: wait crc lsb
    s_rxcrch,                           -- s_rxcrch: wait crc msb
    s_rxapl,                            -- s_rxapl: wait attn pat lsb
    s_rxaph,                            -- s_rxaph: wait attn pat msb
    s_rxacl,                            -- s_rxapl: wait attn crc lsb
    s_rxach                             -- s_rxaph: wait attn crc msb
  );
 
  type rxregs_type is record
    state : rxstate_type;               -- state
    ccmd : slv3;                        -- current command
    crc : slv16;                        -- crc
    bwaddr : slv16;                     -- block write address
    data : slv16;                       -- received data
    dcnt : slv16;                       -- done count
    tcnt : slv16;                       -- tcnt (down count for rblk)
    ack : slbit;                        -- ack flag
    err : slbit;                        -- crc error flag
    stat : slv8;                        -- stat
    apend : slbit;                      -- attn pending
    ano : slbit;                        -- attn notify seen
    apat : slv16;                       -- attn pat
  end record rxregs_type;
 
  constant rxregs_init : rxregs_type := (
             s_rxidle,                  -- state
             "000",                     -- ccmd
             (others=>'0'),             -- crc
             (others=>'0'),             -- bwaddr
             (others=>'0'),             -- data
             (others=>'0'),             -- dcnt
             (others=>'0'),             -- tcnt
             '0','0',                   -- ack, err
             (others=>'0'),             -- stat
             '0','0',                   -- apend, ano
             (others=>'0')              -- attn pat
           );
 
  signal R_TXREGS : txregs_type := txregs_init;  -- TX state registers
  signal N_TXREGS : txregs_type := txregs_init;  -- TX next value state regs
 
  signal R_RXREGS : rxregs_type := rxregs_init;  -- RX state registers
  signal N_RXREGS : rxregs_type := rxregs_init;  -- RX next value state regs
 
  signal TXBUSY : slbit := '0';
  signal RXBUSY : slbit := '0';
 
  signal STAT_L : rlink_tba_stat_type := rlink_tba_stat_init; -- local, readable
 
begin
 
  proc_regs: process (CLK)
  begin
 
    if rising_edge(CLK) then
      if RESET = '1' then
        R_TXREGS <= txregs_init;
        R_RXREGS <= rxregs_init;
      else
        R_TXREGS <= N_TXREGS;
        R_RXREGS <= N_RXREGS;
      end if;
    end if;
 
  end process proc_regs;
 
  -- tx FSM ==================================================================
 
  proc_txnext: process (R_TXREGS, CNTL, DI, RL_BUSY)
    variable r : txregs_type := txregs_init;
    variable n : txregs_type := txregs_init;
 
    variable itxbusy : slbit := '0';
    variable icpdi : slv9 := (others=>'0');
    variable iena : slbit := '0';
    variable ibre : slbit := '0';
    variable do_crc : slbit := '0';
 
  begin
 
    r := R_TXREGS;
    n := R_TXREGS;
 
    itxbusy := '1';
    icpdi := (others=>'0');
    iena  := '0';
    ibre  := '0';
    do_crc := '0';
 
    if CNTL.eop='1' and r.state/= s_txidle then -- if eop requested and busy
      n.eoppend := '1';                           -- queue it
    end if;
 
    case r.state is
      when s_txidle =>                  -- s_txidle: wait for ENA ------------
        itxbusy := '0';
        if CNTL.ena = '1' then            -- cmd requested
          n.ccmd := CNTL.cmd;
          if CNTL.eop = '1' then            -- if eop requested with ENA
            n.eoppend := '1';                 -- queue it, eop after this cmd
          end if;
          if r.sopdone = '0' then           -- if not in active packet
            n.snum := (others=>'0');          -- set snum=0
            n.state := s_txsop;               -- send sop
          else
            n.state := s_txcmd;
          end if;
        else                              -- no cmd requested
          if CNTL.eop='1' and r.sopdone='1' then   -- if eop req and in packet
            n.state := s_txeop;                      -- send eop  
          end if;
        end if;
 
      when s_txsop =>                   -- s_txsop: send sop -----------------
        n.sopdone := '1';
        icpdi := c_rlink_dat_sop;
        iena  := '1';
        if RL_BUSY = '0' then
          n.crc   := (others=>'0');
          n.state := s_txcmd;
        end if;
 
      when s_txeop =>                   -- s_txeop: send eop -----------------
        n.sopdone := '0';
        n.eoppend := '0';
        icpdi := c_rlink_dat_eop;
        iena  := '1';
        if RL_BUSY = '0' then
          n.crc := (others=>'0');
          n.state := s_txidle;
        end if;
 
      when s_txcmd =>                   -- s_txcmd: send cmd -----------------
        n.tcnt   := CNTL.cnt;
        n.braddr := (others=>'0');
        icpdi(c_rlink_cmd_rbf_seq)  := r.snum;
        icpdi(c_rlink_cmd_rbf_code) := r.ccmd;
        iena := '1';
        if RL_BUSY = '0' then
          do_crc := '1';
          n.snum := slv(unsigned(r.snum) + 1);-- otherwise just increment snum
          case r.ccmd is
            when c_rlink_cmd_labo => n.state := s_txcrcl2;
            when c_rlink_cmd_attn => n.state := s_txcrcl2;
            when others => n.state := s_txal;
          end case;
        end if;
 
      when s_txal =>                    -- s_txal: send addr lsb -------------
        icpdi := '0' & CNTL.addr(f_byte0);
        iena  := '1';
        if RL_BUSY = '0' then
          do_crc := '1';
          n.state := s_txah;
        end if;
 
      when s_txah =>                    -- s_txah: send addr msb -------------
        icpdi := '0' & CNTL.addr(f_byte1);
        iena  := '1';
        if RL_BUSY = '0' then
          do_crc := '1';
          case r.ccmd is
            when c_rlink_cmd_rreg => n.state := s_txcrcl2;
            when c_rlink_cmd_rblk => n.state := s_txcl;
            when c_rlink_cmd_wblk => n.state := s_txcl;
            when others => n.state := s_txdl;
          end case;
        end if;
 
      when s_txcl =>                    -- s_txcl: send blk count lsb -------
        icpdi := '0' & CNTL.cnt(f_byte0);
        iena  := '1';
        if RL_BUSY = '0' then
          do_crc := '1';
          n.state := s_txch;
        end if;
 
      when s_txch =>                    -- s_txch: send blk count msb -------
        icpdi := '0' & CNTL.cnt(f_byte1);
        iena  := '1';
        if RL_BUSY = '0' then
          do_crc := '1';
          if r.ccmd = c_rlink_cmd_wblk then
            n.state := s_txcrcl1;
          else
            n.state := s_txcrcl2;
          end if;
        end if;
 
      when s_txdl =>                    -- s_txdl: send data lsb -------------
        icpdi := '0' & DI(d_f_data);
        iena  := '1';
        if RL_BUSY = '0' then
          do_crc := '1';
          n.state := s_txdh;
        end if;
 
      when s_txdh =>                    -- s_txdh: send data msb -------------
        icpdi := '0' & DI(f_byte1);
        iena  := '1';
        if RL_BUSY = '0' then
          do_crc := '1';
          n.state := s_txcrcl2;
        end if;
 
      when s_txcrcl1 =>                 -- s_txcrcl1: send cmd crc lsb in wblk
        icpdi := '0' & r.crc(f_byte0);
        iena  := '1';
        if RL_BUSY = '0' then
          n.state := s_txcrch1;
        end if;
 
      when s_txcrch1 =>                 -- s_txcrch1: send cmd crc msb in wblk
        icpdi := '0' & r.crc(f_byte1);
        iena  := '1';
        if RL_BUSY = '0' then
          n.state := s_txwbld;
        end if;
 
      when s_txwbld =>                  -- s_txwbld: wblk data load ----------
                                        -- this state runs when s_wreg is 
                                        -- executed in rlink, thus doesn't cost
                                        -- an extra cycle in 2nd+ iteration.
        ibre     := '1';
        n.bdata  := DI;
        n.tcnt   := slv(unsigned(r.tcnt)   - 1);
        n.braddr := slv(unsigned(r.braddr) + 1);
        if unsigned(r.tcnt) = 1 then
          n.bloop := '0';
        else
          n.bloop := '1';
        end if;
        n.state := s_txwbdl;
 
      when s_txwbdl =>                  -- s_txwbdl: wblk send data lsb ------
        icpdi := '0' & r.bdata(f_byte0);
        iena  := '1';
        if RL_BUSY = '0' then
          do_crc := '1';
          n.state := s_txwbdh;
        end if;
 
      when s_txwbdh =>                  -- s_txwbdh: wblk send data msb ------
        icpdi := '0' & r.bdata(f_byte1);
        iena  := '1';
        if RL_BUSY = '0' then
          do_crc := '1';
          if r.bloop = '1' then
            n.state := s_txwbld;
          else
            n.state := s_txcrcl2;
          end if;
        end if;
 
      when s_txcrcl2 =>                 -- s_txcrcl2: send final crc lsb -----
        icpdi := '0' & r.crc(f_byte0);
        iena  := '1';
        if RL_BUSY = '0' then
          n.state := s_txcrch2;
        end if;
 
      when s_txcrch2 =>                 -- s_txcrch2: send final crc msb -----
        icpdi := '0' & r.crc(f_byte1);
        iena  := '1';
        if RL_BUSY = '0' then
          if r.eoppend = '1' or unsigned(r.snum)=31 then
            n.state := s_txeop;
          else
            n.state := s_txidle;
          end if;
        end if;
 
      when others => null;              -- <> --------------------------------
    end case;
 
    if do_crc = '1' then
      n.crc := crc16_update(r.crc, icpdi(d_f_data));
    end if;
 
    N_TXREGS <= n;
 
    TXBUSY   <= itxbusy;
 
    STAT_L.braddr <= r.braddr;
    STAT_L.bre    <= ibre;
 
    RL_DI  <= icpdi;
    RL_ENA <= iena;
 
  end process proc_txnext;
 
  -- rx FSM ==================================================================
 
  proc_rxnext: process (R_RXREGS, CNTL, RL_DO, RL_VAL)
    variable r : rxregs_type := rxregs_init;
    variable n : rxregs_type := rxregs_init;
 
    variable irxbusy : slbit := '0';
    variable ibwe : slbit := '0';
    variable do_crc : slbit := '0';
    variable ido : slv16 := (others=>'0');
 
  begin
 
    r := R_RXREGS;
    n := R_RXREGS;
 
    n.ack := '0';
    n.ano := '0';
 
    irxbusy := '1';
    ibwe := '0';
    do_crc := '0';
    ido := r.data;
 
    case r.state is
      when s_rxidle =>                  -- s_rxidle: wait --------------------
        n.crc := (others=>'0');
        n.err := '0';
 
        if RL_VAL = '1' then
          if RL_DO = c_rlink_dat_attn then -- attn seen ?
            n.state := s_rxapl;
          elsif RL_DO = c_rlink_dat_sop then
            n.state := s_rxcmd;
          end if;
        else
          irxbusy := '0';                  -- signal rx not busy
        end if;
 
      when s_rxcmd =>                   -- s_rxcmd: wait cmd  ----------------
       if RL_VAL = '1' then
          if RL_DO = c_rlink_dat_eop then
            n.state := s_rxidle;
          else
            n.bwaddr := (others=>'0');
            do_crc := '1';
            n.ccmd := RL_DO(n.ccmd'range);
            case RL_DO(n.ccmd'range) is
              when c_rlink_cmd_rreg => n.state := s_rxdl;
              when c_rlink_cmd_rblk => n.state := s_rxcl;
              when c_rlink_cmd_wreg => n.state := s_rxstat;
              when c_rlink_cmd_wblk => n.state := s_rxdcl;
              when c_rlink_cmd_labo => n.state := s_rxbabo;
              when c_rlink_cmd_attn => n.state := s_rxdl;
              when c_rlink_cmd_init => n.state := s_rxstat;
              when others => null;
            end case;
          end if;
       else
         irxbusy := '0';                  -- signal rx not busy
       end if;
 
      when s_rxcl =>                    -- s_rxcl: wait cnt lsb --------------
        if RL_VAL = '1' then
          do_crc := '1';
          n.tcnt(f_byte0) := RL_DO(d_f_data);
          n.state := s_rxch;
        end if;
 
      when s_rxch =>                    -- s_rxch: wait cnt msb --------------
        if RL_VAL = '1' then
          do_crc := '1';
          n.tcnt(f_byte1) := RL_DO(d_f_data);
          n.state := s_rxdl;
        end if;
 
      when s_rxbabo =>                  -- s_rxbabo: wait babo ---------------
        if RL_VAL = '1' then
          do_crc := '1';
          n.data(15 downto 0) := (others=>'0');
          n.data(f_byte0) := RL_DO(d_f_data);
          n.state := s_rxstat;
        end if;
 
      when s_rxdl =>                    -- s_rxdl: wait data lsb -------------
        if RL_VAL = '1' then
          do_crc := '1';
          n.data(f_byte0) := RL_DO(d_f_data);
          n.state := s_rxdh;
        end if;
 
      when s_rxdh =>                    -- s_rxdh: wait data msb -------------
        if RL_VAL = '1' then
          do_crc := '1';
          n.data(f_byte1) := RL_DO(d_f_data);
          n.tcnt   := slv(unsigned(r.tcnt)   - 1);
          n.bwaddr := slv(unsigned(r.bwaddr) + 1);
          if r.ccmd = c_rlink_cmd_rblk then
            ido(f_byte1) := RL_DO(d_f_data);
            ibwe := '1';
          end if;
          if r.ccmd /= c_rlink_cmd_rblk then
            n.state := s_rxstat;
          elsif unsigned(r.tcnt) = 1 then
            n.state := s_rxdcl;
          else
            n.state := s_rxdl;
          end if;
        end if;
 
      when s_rxdcl =>                   -- s_rxdcl: wait dcnt lsb ------------
        if RL_VAL = '1' then
          do_crc := '1';
          n.dcnt(f_byte0) := RL_DO(d_f_data);
          n.state := s_rxdch;
        end if;
 
      when s_rxdch =>                   -- s_rxdch: wait dcnt msb ------------
        if RL_VAL = '1' then
          do_crc := '1';
          n.dcnt(f_byte1) := RL_DO(d_f_data);
          n.state := s_rxstat;
        end if;
 
      when s_rxstat =>                  -- s_rxstat: wait status -------------
        if RL_VAL = '1' then
          do_crc := '1';
          n.stat := RL_DO(d_f_data);
          n.apend := RL_DO(c_rlink_stat_rbf_attn); -- update attn status
          n.state := s_rxcrcl;
        end if;
 
      when s_rxcrcl =>                  -- s_rxcrcl: wait crc lsb ------------
        if RL_VAL = '1' then
          if r.crc(f_byte0) /= RL_DO(d_f_data) then
            n.err := '1';
          end if;
          n.state := s_rxcrch;
        end if;
 
      when s_rxcrch =>                  -- s_rxcrch: wait crc msb ------------
        if RL_VAL = '1' then
          if r.crc(f_byte1) /= RL_DO(d_f_data) then
            n.err := '1';
          end if;
          n.ack := '1';
          n.state := s_rxcmd;
        end if;
 
      when s_rxapl =>                   -- s_rxapl: wait attn pat lsb --------
        if RL_VAL = '1' then
          do_crc := '1';
          n.apat(f_byte0) := RL_DO(d_f_data);
          n.state := s_rxaph;
        end if;
 
      when s_rxaph =>                   -- s_rxaph: wait attn pat msb --------
        if RL_VAL = '1' then
          do_crc := '1';
          n.apat(f_byte1) := RL_DO(d_f_data);
          n.state := s_rxacl;
        end if;
 
      when s_rxacl =>                   -- s_rxacl: wait attn crc lsb --------
        if RL_VAL = '1' then
          if r.crc(f_byte0) /= RL_DO(d_f_data) then
            n.err := '1';
          end if;
          n.state := s_rxach;
        end if;
 
      when s_rxach =>                   -- s_rxach: wait attn crc msb --------
        if RL_VAL = '1' then
          if r.crc(f_byte1) /= RL_DO(d_f_data) then
            n.err := '1';
          end if;
          n.ano := '1';
          n.state := s_rxidle;
        end if;
 
      when others => null;              -- <> --------------------------------
    end case;
 
    if do_crc = '1' then
      n.crc := crc16_update(r.crc, RL_DO(d_f_data));
    end if;
 
    N_RXREGS <= n;
 
    RXBUSY   <= irxbusy;
 
    DO   <= ido;
    STAT_L.stat   <= r.stat;
    STAT_L.ack    <= r.ack;
    STAT_L.err    <= r.err;
    STAT_L.bwaddr <= r.bwaddr;
    STAT_L.bwe    <= ibwe;
    STAT_L.dcnt   <= r.dcnt;
    STAT_L.apend  <= r.apend;
    STAT_L.ano    <= r.ano;
    STAT_L.apat   <= r.apat;
 
    RL_HOLD <= '0';
 
  end process proc_rxnext;
 
  STAT_L.busy <= RXBUSY or TXBUSY;
  STAT <= STAT_L;
 
end syn;

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Line No.	Rev	Author	Line
1	37	wfjm	`-- $Id: rlink_tba.vhd 595 2014-09-28 08:47:45Z mueller $`
2			`--`
3			`-- Copyright 2007-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>`
4			`--`
5			`-- This program is free software; you may redistribute and/or modify it under`
6			`-- the terms of the GNU General Public License as published by the Free`
7			`-- Software Foundation, either version 2, or at your option any later version.`
8			`--`
9			`-- This program is distributed in the hope that it will be useful, but`
10			`-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY`
11			`-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
12			`-- for complete details.`
13			`--`
14			`------------------------------------------------------------------------------`
15			`-- Module Name: rlink_tba - syn`
16			`-- Description: rlink test bench adapter`
17			`--`
18			`-- Dependencies: -`
19			`-- Test bench: -`
20			`-- Target Devices: generic [synthesizable, but only used in tb's]`
21			`-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31`
22			`--`
23			`-- Revision History:`
24			`-- Date Rev Version Comment`
25			`-- 2014-09-27 595 4.0 now full rlink v4 iface`
26			`-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit; add state r_txal;`
27			`-- 2011-11-22 432 3.0.2 now numeric_std clean`
28			`-- 2011-11-19 427 3.0.1 fix crc8_update usage;`
29			`-- 2010-12-24 347 3.0 rename rritba->rlink_tba, CP_->RL_; rbus v3 port;`
30			`-- 2010-06-18 306 2.5.1 rename rbus data fields to _rbf_`
31			`-- 2010-06-07 302 2.5 use sop/eop framing instead of soc+chaining`
32			`-- 2010-05-05 289 1.0.3 drop dead snooper code and unneeded unsigned casts`
33			`-- 2008-03-02 121 1.0.2 remove snoopers`
34			`-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned`
35			`-- 2007-09-09 81 1.0 Initial version`
36			`------------------------------------------------------------------------------`
37
38			`library ieee;`
39			`use ieee.std_logic_1164.all;`
40			`use ieee.numeric_std.all;`
41
42			`use work.slvtypes.all;`
43			`use work.comlib.all;`
44			`use work.rlinklib.all;`
45			`use work.rlinktblib.all;`
46
47			`entity rlink_tba is -- rlink test bench adapter`
48			`port (`
49			`CLK : in slbit; -- clock`
50			`RESET : in slbit; -- reset`
51			`CNTL : in rlink_tba_cntl_type; -- control port`
52			`DI : in slv16; -- input data`
53			`STAT : out rlink_tba_stat_type; -- status port`
54			`DO : out slv16; -- output data`
55			`RL_DI : out slv9; -- rlink: data in`
56			`RL_ENA : out slbit; -- rlink: data enable`
57			`RL_BUSY : in slbit; -- rlink: data busy`
58			`RL_DO : in slv9; -- rlink: data out`
59			`RL_VAL : in slbit; -- rlink: data valid`
60			`RL_HOLD : out slbit -- rlink: data hold`
61			`);`
62			`end entity rlink_tba;`
63
64
65			`architecture syn of rlink_tba is`
66
67			`constant d_f_cflag : integer := 8; -- d9: comma flag`
68			`subtype d_f_data is integer range 7 downto 0; -- d9: data field`
69
70			`subtype f_byte1 is integer range 15 downto 8;`
71			`subtype f_byte0 is integer range 7 downto 0;`
72
73			`type txstate_type is (`
74			`s_txidle, -- s_txidle: wait for ENA`
75			`s_txsop, -- s_txsop: send sop`
76			`s_txeop, -- s_txeop: send eop`
77			`s_txcmd, -- s_txcmd: send cmd`
78			`s_txal, -- s_txal: send addr lsb`
79			`s_txah, -- s_txah: send addr msb`
80			`s_txcl, -- s_txcl: send blk count lsb`
81			`s_txch, -- s_txcl: send blk count msb`
82			`s_txdl, -- s_txdl: send data lsb`
83			`s_txdh, -- s_txdh: send data msb`
84			`s_txcrcl1, -- s_txcrcl1: send cmd crc lsb in wblk`
85			`s_txcrch1, -- s_txcrch1: send cmd crc msb in wblk`
86			`s_txwbld, -- s_txwbld: wblk data load`
87			`s_txwbdl, -- s_txwbdl: wblk send data lsb`
88			`s_txwbdh, -- s_txwbdh: wblk send data msb`
89			`s_txcrcl2, -- s_txcrcl2: send final crc lsb`
90			`s_txcrch2 -- s_txcrch2: send final crc msb`
91			`);`
92
93			`type txregs_type is record`
94			`state : txstate_type; -- state`
95			`ccmd : slv3; -- current command`
96			`snum : slv5; -- command sequence number`
97			`crc : slv16; -- crc (cmd and data)`
98			`braddr : slv16; -- block read address`
99			`bdata : slv16; -- block data`
100			`bloop : slbit; -- block loop flag`
101			`tcnt : slv16; -- tcnt (down count for wblk)`
102			`sopdone : slbit; -- sop send`
103			`eoppend : slbit; -- eop pending`
104			`end record txregs_type;`
105
106			`constant txregs_init : txregs_type := (`
107			`s_txidle, -- state`
108			`"000", -- ccmd`
109			`"00000", -- snum`
110			`(others=>'0'), -- crc`
111			`(others=>'0'), -- braddr`
112			`(others=>'0'), -- bdata`
113			`'0', -- bloop`
114			`(others=>'0'), -- tcnt`
115			`'0','0' -- sopdone, eoppend`
116			`);`
117
118			`type rxstate_type is (`
119			`s_rxidle, -- s_rxidle: wait for ENA`
120			`s_rxcmd, -- s_rxcmd: wait cmd`
121			`s_rxcl, -- s_rxcl: wait cnt lsb`
122			`s_rxch, -- s_rxcl: wait cnt msb`
123			`s_rxbabo, -- s_rxbabo: wait babo`
124			`s_rxdcl, -- s_rxdcl: wait dcnt lsb`
125			`s_rxdch, -- s_rxdch: wait dcnt msb`
126			`s_rxdl, -- s_rxdl: wait data lsb`
127			`s_rxdh, -- s_rxdh: wait data msb`
128			`s_rxstat, -- s_rxstat: wait status`
129			`s_rxcrcl, -- s_rxcrcl: wait crc lsb`
130			`s_rxcrch, -- s_rxcrch: wait crc msb`
131			`s_rxapl, -- s_rxapl: wait attn pat lsb`
132			`s_rxaph, -- s_rxaph: wait attn pat msb`
133			`s_rxacl, -- s_rxapl: wait attn crc lsb`
134			`s_rxach -- s_rxaph: wait attn crc msb`
135			`);`
136
137			`type rxregs_type is record`
138			`state : rxstate_type; -- state`
139			`ccmd : slv3; -- current command`
140			`crc : slv16; -- crc`
141			`bwaddr : slv16; -- block write address`
142			`data : slv16; -- received data`
143			`dcnt : slv16; -- done count`
144			`tcnt : slv16; -- tcnt (down count for rblk)`
145			`ack : slbit; -- ack flag`
146			`err : slbit; -- crc error flag`
147			`stat : slv8; -- stat`
148			`apend : slbit; -- attn pending`
149			`ano : slbit; -- attn notify seen`
150			`apat : slv16; -- attn pat`
151			`end record rxregs_type;`
152
153			`constant rxregs_init : rxregs_type := (`
154			`s_rxidle, -- state`
155			`"000", -- ccmd`
156			`(others=>'0'), -- crc`
157			`(others=>'0'), -- bwaddr`
158			`(others=>'0'), -- data`
159			`(others=>'0'), -- dcnt`
160			`(others=>'0'), -- tcnt`
161			`'0','0', -- ack, err`
162			`(others=>'0'), -- stat`
163			`'0','0', -- apend, ano`
164			`(others=>'0') -- attn pat`
165			`);`
166
167			`signal R_TXREGS : txregs_type := txregs_init; -- TX state registers`
168			`signal N_TXREGS : txregs_type := txregs_init; -- TX next value state regs`
169
170			`signal R_RXREGS : rxregs_type := rxregs_init; -- RX state registers`
171			`signal N_RXREGS : rxregs_type := rxregs_init; -- RX next value state regs`
172
173			`signal TXBUSY : slbit := '0';`
174			`signal RXBUSY : slbit := '0';`
175
176			`signal STAT_L : rlink_tba_stat_type := rlink_tba_stat_init; -- local, readable`
177
178			`begin`
179
180			`proc_regs: process (CLK)`
181			`begin`
182
183			`if rising_edge(CLK) then`
184			`if RESET = '1' then`
185			`R_TXREGS <= txregs_init;`
186			`R_RXREGS <= rxregs_init;`
187			`else`
188			`R_TXREGS <= N_TXREGS;`
189			`R_RXREGS <= N_RXREGS;`
190			`end if;`
191			`end if;`
192
193			`end process proc_regs;`
194
195			`-- tx FSM ==================================================================`
196
197			`proc_txnext: process (R_TXREGS, CNTL, DI, RL_BUSY)`
198			`variable r : txregs_type := txregs_init;`
199			`variable n : txregs_type := txregs_init;`
200
201			`variable itxbusy : slbit := '0';`
202			`variable icpdi : slv9 := (others=>'0');`
203			`variable iena : slbit := '0';`
204			`variable ibre : slbit := '0';`
205			`variable do_crc : slbit := '0';`
206
207			`begin`
208
209			`r := R_TXREGS;`
210			`n := R_TXREGS;`
211
212			`itxbusy := '1';`
213			`icpdi := (others=>'0');`
214			`iena := '0';`
215			`ibre := '0';`
216			`do_crc := '0';`
217
218			`if CNTL.eop='1' and r.state/= s_txidle then -- if eop requested and busy`
219			`n.eoppend := '1'; -- queue it`
220			`end if;`
221
222			`case r.state is`
223			`when s_txidle => -- s_txidle: wait for ENA ------------`
224			`itxbusy := '0';`
225			`if CNTL.ena = '1' then -- cmd requested`
226			`n.ccmd := CNTL.cmd;`
227			`if CNTL.eop = '1' then -- if eop requested with ENA`
228			`n.eoppend := '1'; -- queue it, eop after this cmd`
229			`end if;`
230			`if r.sopdone = '0' then -- if not in active packet`
231			`n.snum := (others=>'0'); -- set snum=0`
232			`n.state := s_txsop; -- send sop`
233			`else`
234			`n.state := s_txcmd;`
235			`end if;`
236			`else -- no cmd requested`
237			`if CNTL.eop='1' and r.sopdone='1' then -- if eop req and in packet`
238			`n.state := s_txeop; -- send eop`
239			`end if;`
240			`end if;`
241
242			`when s_txsop => -- s_txsop: send sop -----------------`
243			`n.sopdone := '1';`
244			`icpdi := c_rlink_dat_sop;`
245			`iena := '1';`
246			`if RL_BUSY = '0' then`
247			`n.crc := (others=>'0');`
248			`n.state := s_txcmd;`
249			`end if;`
250
251			`when s_txeop => -- s_txeop: send eop -----------------`
252			`n.sopdone := '0';`
253			`n.eoppend := '0';`
254			`icpdi := c_rlink_dat_eop;`
255			`iena := '1';`
256			`if RL_BUSY = '0' then`
257			`n.crc := (others=>'0');`
258			`n.state := s_txidle;`
259			`end if;`
260
261			`when s_txcmd => -- s_txcmd: send cmd -----------------`
262			`n.tcnt := CNTL.cnt;`
263			`n.braddr := (others=>'0');`
264			`icpdi(c_rlink_cmd_rbf_seq) := r.snum;`
265			`icpdi(c_rlink_cmd_rbf_code) := r.ccmd;`
266			`iena := '1';`
267			`if RL_BUSY = '0' then`
268			`do_crc := '1';`
269			`n.snum := slv(unsigned(r.snum) + 1);-- otherwise just increment snum`
270			`case r.ccmd is`
271			`when c_rlink_cmd_labo => n.state := s_txcrcl2;`
272			`when c_rlink_cmd_attn => n.state := s_txcrcl2;`
273			`when others => n.state := s_txal;`
274			`end case;`
275			`end if;`
276
277			`when s_txal => -- s_txal: send addr lsb -------------`
278			`icpdi := '0' & CNTL.addr(f_byte0);`
279			`iena := '1';`
280			`if RL_BUSY = '0' then`
281			`do_crc := '1';`
282			`n.state := s_txah;`
283			`end if;`
284
285			`when s_txah => -- s_txah: send addr msb -------------`
286			`icpdi := '0' & CNTL.addr(f_byte1);`
287			`iena := '1';`
288			`if RL_BUSY = '0' then`
289			`do_crc := '1';`
290			`case r.ccmd is`
291			`when c_rlink_cmd_rreg => n.state := s_txcrcl2;`
292			`when c_rlink_cmd_rblk => n.state := s_txcl;`
293			`when c_rlink_cmd_wblk => n.state := s_txcl;`
294			`when others => n.state := s_txdl;`
295			`end case;`
296			`end if;`
297
298			`when s_txcl => -- s_txcl: send blk count lsb -------`
299			`icpdi := '0' & CNTL.cnt(f_byte0);`
300			`iena := '1';`
301			`if RL_BUSY = '0' then`
302			`do_crc := '1';`
303			`n.state := s_txch;`
304			`end if;`
305
306			`when s_txch => -- s_txch: send blk count msb -------`
307			`icpdi := '0' & CNTL.cnt(f_byte1);`
308			`iena := '1';`
309			`if RL_BUSY = '0' then`
310			`do_crc := '1';`
311			`if r.ccmd = c_rlink_cmd_wblk then`
312			`n.state := s_txcrcl1;`
313			`else`
314			`n.state := s_txcrcl2;`
315			`end if;`
316			`end if;`
317
318			`when s_txdl => -- s_txdl: send data lsb -------------`
319			`icpdi := '0' & DI(d_f_data);`
320			`iena := '1';`
321			`if RL_BUSY = '0' then`
322			`do_crc := '1';`
323			`n.state := s_txdh;`
324			`end if;`
325
326			`when s_txdh => -- s_txdh: send data msb -------------`
327			`icpdi := '0' & DI(f_byte1);`
328			`iena := '1';`
329			`if RL_BUSY = '0' then`
330			`do_crc := '1';`
331			`n.state := s_txcrcl2;`
332			`end if;`
333
334			`when s_txcrcl1 => -- s_txcrcl1: send cmd crc lsb in wblk`
335			`icpdi := '0' & r.crc(f_byte0);`
336			`iena := '1';`
337			`if RL_BUSY = '0' then`
338			`n.state := s_txcrch1;`
339			`end if;`
340
341			`when s_txcrch1 => -- s_txcrch1: send cmd crc msb in wblk`
342			`icpdi := '0' & r.crc(f_byte1);`
343			`iena := '1';`
344			`if RL_BUSY = '0' then`
345			`n.state := s_txwbld;`
346			`end if;`
347
348			`when s_txwbld => -- s_txwbld: wblk data load ----------`
349			`-- this state runs when s_wreg is`
350			`-- executed in rlink, thus doesn't cost`
351			`-- an extra cycle in 2nd+ iteration.`
352			`ibre := '1';`
353			`n.bdata := DI;`
354			`n.tcnt := slv(unsigned(r.tcnt) - 1);`
355			`n.braddr := slv(unsigned(r.braddr) + 1);`
356			`if unsigned(r.tcnt) = 1 then`
357			`n.bloop := '0';`
358			`else`
359			`n.bloop := '1';`
360			`end if;`
361			`n.state := s_txwbdl;`
362
363			`when s_txwbdl => -- s_txwbdl: wblk send data lsb ------`
364			`icpdi := '0' & r.bdata(f_byte0);`
365			`iena := '1';`
366			`if RL_BUSY = '0' then`
367			`do_crc := '1';`
368			`n.state := s_txwbdh;`
369			`end if;`
370
371			`when s_txwbdh => -- s_txwbdh: wblk send data msb ------`
372			`icpdi := '0' & r.bdata(f_byte1);`
373			`iena := '1';`
374			`if RL_BUSY = '0' then`
375			`do_crc := '1';`
376			`if r.bloop = '1' then`
377			`n.state := s_txwbld;`
378			`else`
379			`n.state := s_txcrcl2;`
380			`end if;`
381			`end if;`
382
383			`when s_txcrcl2 => -- s_txcrcl2: send final crc lsb -----`
384			`icpdi := '0' & r.crc(f_byte0);`
385			`iena := '1';`
386			`if RL_BUSY = '0' then`
387			`n.state := s_txcrch2;`
388			`end if;`
389
390			`when s_txcrch2 => -- s_txcrch2: send final crc msb -----`
391			`icpdi := '0' & r.crc(f_byte1);`
392			`iena := '1';`
393			`if RL_BUSY = '0' then`
394			`if r.eoppend = '1' or unsigned(r.snum)=31 then`
395			`n.state := s_txeop;`
396			`else`
397			`n.state := s_txidle;`
398			`end if;`
399			`end if;`
400
401			`when others => null; -- <> --------------------------------`
402			`end case;`
403
404			`if do_crc = '1' then`
405			`n.crc := crc16_update(r.crc, icpdi(d_f_data));`
406			`end if;`
407
408			`N_TXREGS <= n;`
409
410			`TXBUSY <= itxbusy;`
411
412			`STAT_L.braddr <= r.braddr;`
413			`STAT_L.bre <= ibre;`
414
415			`RL_DI <= icpdi;`
416			`RL_ENA <= iena;`
417
418			`end process proc_txnext;`
419
420			`-- rx FSM ==================================================================`
421
422			`proc_rxnext: process (R_RXREGS, CNTL, RL_DO, RL_VAL)`
423			`variable r : rxregs_type := rxregs_init;`
424			`variable n : rxregs_type := rxregs_init;`
425
426			`variable irxbusy : slbit := '0';`
427			`variable ibwe : slbit := '0';`
428			`variable do_crc : slbit := '0';`
429			`variable ido : slv16 := (others=>'0');`
430
431			`begin`
432
433			`r := R_RXREGS;`
434			`n := R_RXREGS;`
435
436			`n.ack := '0';`
437			`n.ano := '0';`
438
439			`irxbusy := '1';`
440			`ibwe := '0';`
441			`do_crc := '0';`
442			`ido := r.data;`
443
444			`case r.state is`
445			`when s_rxidle => -- s_rxidle: wait --------------------`
446			`n.crc := (others=>'0');`
447			`n.err := '0';`
448
449			`if RL_VAL = '1' then`
450			`if RL_DO = c_rlink_dat_attn then -- attn seen ?`
451			`n.state := s_rxapl;`
452			`elsif RL_DO = c_rlink_dat_sop then`
453			`n.state := s_rxcmd;`
454			`end if;`
455			`else`
456			`irxbusy := '0'; -- signal rx not busy`
457			`end if;`
458
459			`when s_rxcmd => -- s_rxcmd: wait cmd ----------------`
460			`if RL_VAL = '1' then`
461			`if RL_DO = c_rlink_dat_eop then`
462			`n.state := s_rxidle;`
463			`else`
464			`n.bwaddr := (others=>'0');`
465			`do_crc := '1';`
466			`n.ccmd := RL_DO(n.ccmd'range);`
467			`case RL_DO(n.ccmd'range) is`
468			`when c_rlink_cmd_rreg => n.state := s_rxdl;`
469			`when c_rlink_cmd_rblk => n.state := s_rxcl;`
470			`when c_rlink_cmd_wreg => n.state := s_rxstat;`
471			`when c_rlink_cmd_wblk => n.state := s_rxdcl;`
472			`when c_rlink_cmd_labo => n.state := s_rxbabo;`
473			`when c_rlink_cmd_attn => n.state := s_rxdl;`
474			`when c_rlink_cmd_init => n.state := s_rxstat;`
475			`when others => null;`
476			`end case;`
477			`end if;`
478			`else`
479			`irxbusy := '0'; -- signal rx not busy`
480			`end if;`
481
482			`when s_rxcl => -- s_rxcl: wait cnt lsb --------------`
483			`if RL_VAL = '1' then`
484			`do_crc := '1';`
485			`n.tcnt(f_byte0) := RL_DO(d_f_data);`
486			`n.state := s_rxch;`
487			`end if;`
488
489			`when s_rxch => -- s_rxch: wait cnt msb --------------`
490			`if RL_VAL = '1' then`
491			`do_crc := '1';`
492			`n.tcnt(f_byte1) := RL_DO(d_f_data);`
493			`n.state := s_rxdl;`
494			`end if;`
495
496			`when s_rxbabo => -- s_rxbabo: wait babo ---------------`
497			`if RL_VAL = '1' then`
498			`do_crc := '1';`
499			`n.data(15 downto 0) := (others=>'0');`
500			`n.data(f_byte0) := RL_DO(d_f_data);`
501			`n.state := s_rxstat;`
502			`end if;`
503
504			`when s_rxdl => -- s_rxdl: wait data lsb -------------`
505			`if RL_VAL = '1' then`
506			`do_crc := '1';`
507			`n.data(f_byte0) := RL_DO(d_f_data);`
508			`n.state := s_rxdh;`
509			`end if;`
510
511			`when s_rxdh => -- s_rxdh: wait data msb -------------`
512			`if RL_VAL = '1' then`
513			`do_crc := '1';`
514			`n.data(f_byte1) := RL_DO(d_f_data);`
515			`n.tcnt := slv(unsigned(r.tcnt) - 1);`
516			`n.bwaddr := slv(unsigned(r.bwaddr) + 1);`
517			`if r.ccmd = c_rlink_cmd_rblk then`
518			`ido(f_byte1) := RL_DO(d_f_data);`
519			`ibwe := '1';`
520			`end if;`
521			`if r.ccmd /= c_rlink_cmd_rblk then`
522			`n.state := s_rxstat;`
523			`elsif unsigned(r.tcnt) = 1 then`
524			`n.state := s_rxdcl;`
525			`else`
526			`n.state := s_rxdl;`
527			`end if;`
528			`end if;`
529
530			`when s_rxdcl => -- s_rxdcl: wait dcnt lsb ------------`
531			`if RL_VAL = '1' then`
532			`do_crc := '1';`
533			`n.dcnt(f_byte0) := RL_DO(d_f_data);`
534			`n.state := s_rxdch;`
535			`end if;`
536
537			`when s_rxdch => -- s_rxdch: wait dcnt msb ------------`
538			`if RL_VAL = '1' then`
539			`do_crc := '1';`
540			`n.dcnt(f_byte1) := RL_DO(d_f_data);`
541			`n.state := s_rxstat;`
542			`end if;`
543
544			`when s_rxstat => -- s_rxstat: wait status -------------`
545			`if RL_VAL = '1' then`
546			`do_crc := '1';`
547			`n.stat := RL_DO(d_f_data);`
548			`n.apend := RL_DO(c_rlink_stat_rbf_attn); -- update attn status`
549			`n.state := s_rxcrcl;`
550			`end if;`
551
552			`when s_rxcrcl => -- s_rxcrcl: wait crc lsb ------------`
553			`if RL_VAL = '1' then`
554			`if r.crc(f_byte0) /= RL_DO(d_f_data) then`
555			`n.err := '1';`
556			`end if;`
557			`n.state := s_rxcrch;`
558			`end if;`
559
560			`when s_rxcrch => -- s_rxcrch: wait crc msb ------------`
561			`if RL_VAL = '1' then`
562			`if r.crc(f_byte1) /= RL_DO(d_f_data) then`
563			`n.err := '1';`
564			`end if;`
565			`n.ack := '1';`
566			`n.state := s_rxcmd;`
567			`end if;`
568
569			`when s_rxapl => -- s_rxapl: wait attn pat lsb --------`
570			`if RL_VAL = '1' then`
571			`do_crc := '1';`
572			`n.apat(f_byte0) := RL_DO(d_f_data);`
573			`n.state := s_rxaph;`
574			`end if;`
575
576			`when s_rxaph => -- s_rxaph: wait attn pat msb --------`
577			`if RL_VAL = '1' then`
578			`do_crc := '1';`
579			`n.apat(f_byte1) := RL_DO(d_f_data);`
580			`n.state := s_rxacl;`
581			`end if;`
582
583			`when s_rxacl => -- s_rxacl: wait attn crc lsb --------`
584			`if RL_VAL = '1' then`
585			`if r.crc(f_byte0) /= RL_DO(d_f_data) then`
586			`n.err := '1';`
587			`end if;`
588			`n.state := s_rxach;`
589			`end if;`
590
591			`when s_rxach => -- s_rxach: wait attn crc msb --------`
592			`if RL_VAL = '1' then`
593			`if r.crc(f_byte1) /= RL_DO(d_f_data) then`
594			`n.err := '1';`
595			`end if;`
596			`n.ano := '1';`
597			`n.state := s_rxidle;`
598			`end if;`
599
600			`when others => null; -- <> --------------------------------`
601			`end case;`
602
603			`if do_crc = '1' then`
604			`n.crc := crc16_update(r.crc, RL_DO(d_f_data));`
605			`end if;`
606
607			`N_RXREGS <= n;`
608
609			`RXBUSY <= irxbusy;`
610
611			`DO <= ido;`
612			`STAT_L.stat <= r.stat;`
613			`STAT_L.ack <= r.ack;`
614			`STAT_L.err <= r.err;`
615			`STAT_L.bwaddr <= r.bwaddr;`
616			`STAT_L.bwe <= ibwe;`
617			`STAT_L.dcnt <= r.dcnt;`
618			`STAT_L.apend <= r.apend;`
619			`STAT_L.ano <= r.ano;`
620			`STAT_L.apat <= r.apat;`
621
622			`RL_HOLD <= '0';`
623
624			`end process proc_rxnext;`
625
626			`STAT_L.busy <= RXBUSY or TXBUSY;`
627			`STAT <= STAT_L;`
628
629			`end syn;`