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-- $Id: serport_uart_rx.vhd 784 2016-07-09 22:17:01Z mueller $
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--
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-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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-- The uart expects CLKDIV+1 wide input bit symbols.
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-- This implementation counts the number of 1's in the first CLKDIV clock
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-- cycles, and checks in the last cycle of the symbol time whether the
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-- number of 1's was > CLKDIV/2. This supresses short glitches nicely,
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-- especially for larger clock dividers.
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--
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------------------------------------------------------------------------------
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-- Module Name: serport_uart_rx - syn
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-- Description: serial port UART - receiver
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--
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-- Dependencies: -
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-- Test bench: tb/tb_serport_uart_rxtx
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-- Target Devices: generic
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-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.2; ghdl 0.18-0.33
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-- Revision History:
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-- Date Rev Version Comment
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-- 2016-05-22 767 2.0.4 don't init N_REGS (vivado fix for fsm inference)
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-- 2011-10-22 417 2.0.3 now numeric_std clean
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-- 2009-07-12 233 2.0.2 remove snoopers
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-- 2008-03-02 121 2.0.1 comment out snoopers
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-- 2007-10-21 91 2.0 re-designed and -implemented with state machine.
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-- allow CLKDIV=0 with 1 stop bit; allow max. CLKDIV
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-- (all 1's); aborts bad start bit after 1/2 cell;
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-- accepts stop bit after 1/2 cell, permits tx clock
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-- be ~3 percent faster than rx clock.
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-- for 3s1000ft256: 50 -> 58 slices for CDWIDTH=13
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-- 2007-10-14 89 1.1 almost full rewrite, handles now CLKDIV=0 properly
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-- for 3s1000ft256: 43 -> 50 slices for CDWIDTH=13
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-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
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-- 2007-06-30 62 1.0 Initial version
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------------------------------------------------------------------------------
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-- NOTE: for test bench usage a copy of all serport_* entities, with _tb
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-- !!!! appended to the name, has been created in the /tb sub folder.
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-- !!!! Ensure to update the copy when this file is changed !!
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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entity serport_uart_rx is -- serial port uart: receive part
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generic (
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CDWIDTH : positive := 13); -- clk divider width
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
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RXSD : in slbit; -- receive serial data (uart view)
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RXDATA : out slv8; -- receiver data out
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RXVAL : out slbit; -- receiver data valid
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RXERR : out slbit; -- receiver data error (frame error)
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RXACT : out slbit -- receiver active
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);
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end serport_uart_rx;
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architecture syn of serport_uart_rx is
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type state_type is (
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s_idle, -- s_idle: idle
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s_colb0, -- s_colb0: collect b0 (start bit)
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s_endb0, -- s_endb0: finish b0 (start bit)
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s_colbx, -- s_colbx: collect bx
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s_endbx, -- s_endbx: finish bx
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s_colb9, -- s_colb9: collect bx (stop bit)
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s_endb9 -- s_endb9: finish bx (stop bit)
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);
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type regs_type is record
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state : state_type; -- state
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ccnt : slv(CDWIDTH-1 downto 0); -- clock divider counter
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dcnt : slv(CDWIDTH downto 0); -- data '1' counter
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bcnt : slv4; -- bit counter
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sreg : slv8; -- input shift register
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end record regs_type;
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constant ccntzero : slv(CDWIDTH-1 downto 0) := (others=>'0');
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constant dcntzero : slv(CDWIDTH downto 0) := (others=>'0');
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constant regs_init : regs_type := (
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s_idle, -- state
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ccntzero, -- ccnt
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dcntzero, -- dcnt
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(others=>'0'), -- bcnt
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(others=>'0') -- sreg
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);
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signal R_REGS : regs_type := regs_init;
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signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
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begin
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proc_regs: process (CLK)
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begin
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if rising_edge(CLK) then
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R_REGS <= N_REGS;
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end if;
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end process proc_regs;
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proc_next: process (R_REGS, RESET, CLKDIV, RXSD)
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variable r : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable dbit : slbit := '0';
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variable ld_ccnt : slbit := '0';
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variable tc_ccnt : slbit := '0';
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variable tc_bcnt : slbit := '0';
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variable ld_dcnt : slbit := '0';
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variable ld_bcnt : slbit := '0';
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variable ce_bcnt : slbit := '0';
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variable iact : slbit := '0';
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variable ival : slbit := '0';
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variable ierr : slbit := '0';
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begin
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r := R_REGS;
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n := R_REGS;
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dbit := '0';
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ld_ccnt := '0';
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tc_ccnt := '0';
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tc_bcnt := '0';
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ld_dcnt := '0';
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ld_bcnt := '0';
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ce_bcnt := '0';
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iact := '1';
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ival := '0';
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ierr := '0';
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if unsigned(r.ccnt) = 0 then
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tc_ccnt := '1';
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end if;
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if unsigned(r.bcnt) = 9 then
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tc_bcnt := '1';
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end if;
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if unsigned(r.dcnt) > unsigned("00" & CLKDIV(CDWIDTH-1 downto 1)) then
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dbit := '1';
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end if;
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case r.state is
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when s_idle => -- s_idle: idle ----------------------
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iact := '0';
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ld_dcnt := '1'; -- always keep dcnt in reset
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if RXSD = '0' then -- if start bit seen
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if tc_ccnt = '1' then
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n.state := s_endb0; -- finish b0
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ld_ccnt := '1'; -- start next bit
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ce_bcnt := '1';
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else
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n.state := s_colb0; -- collect b0
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end if;
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else -- otherwise
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ld_ccnt := '1'; -- keep all counters in reset
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ld_bcnt := '1';
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end if;
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when s_colb0 => -- s_colb0: collect b0 (start bit) ---
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if tc_ccnt = '1' then -- last cycle of b0 ?
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n.state := s_endb0; -- finish b0
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ld_ccnt := '1'; -- "
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ce_bcnt := '1';
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else -- continue in b0 ?
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if dbit='1' and RXSD='1' then -- too many 1's ?
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n.state := s_idle; -- abort to idle
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ld_dcnt := '1'; -- put counters in reset
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ld_ccnt := '1';
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ld_bcnt := '1';
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end if;
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end if;
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when s_endb0 => -- s_endb0: finish b0 (start bit) ---
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ld_dcnt := '1'; -- start next bit
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if dbit = '1' then -- was it a 1 ?
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n.state := s_idle; -- abort to idle
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ld_ccnt := '1'; -- put counters in reset
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ld_bcnt := '1';
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else
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if tc_ccnt = '1' then -- last cycle of bx ?
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n.state := s_endbx; -- finish bx
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ld_ccnt := '1';
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ce_bcnt := '1';
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else -- continue in b0 ?
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n.state := s_colbx; -- collect bx
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end if;
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end if;
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when s_colbx => -- s_colbx: collect bx ---------------
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if tc_ccnt = '1' then -- last cycle of bx ?
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n.state := s_endbx; -- finish bx
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ld_ccnt := '1';
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ce_bcnt := '1';
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end if;
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when s_endbx => -- s_endbx: finish bx ---------------
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ld_dcnt := '1'; -- start next bit
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n.sreg := dbit & r.sreg(7 downto 1);
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if tc_ccnt = '1' then -- last cycle of bx ?
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if tc_bcnt = '1' then
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n.state := s_endb9; -- finish b9
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ld_bcnt := '1'; -- and wrap bcnt
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else
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n.state := s_endbx; -- finish bx
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ce_bcnt := '1';
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end if;
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ld_ccnt := '1';
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else -- continue in bx ?
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if tc_bcnt = '1' then
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n.state := s_colb9; -- collect b9
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else
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n.state := s_colbx; -- collect bx
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end if;
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end if;
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when s_colb9 => -- s_colb9: collect bx (stop bit) ----
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if tc_ccnt = '1' then -- last cycle of b9 ?
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n.state := s_endb9; -- finish b9
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ld_ccnt := '1'; -- "
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ld_bcnt := '1'; -- and wrap bcnt
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else -- continue in b9 ?
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if dbit='1' and RXSD='1' then -- already enough 1's ?
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n.state := s_idle; -- finish to idle
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ld_dcnt := '1'; -- put counters in reset
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ld_ccnt := '1';
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ld_bcnt := '1';
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ival := '1';
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end if;
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end if;
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when s_endb9 => -- s_endb9: finish bx (stop bit) ----
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ld_dcnt := '1'; -- start next bit
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if dbit = '1' then -- was it a valid stop bit ?
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ival := '1';
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else
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ierr := '1';
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end if;
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if RXSD = '1' then -- line in idle state ?
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n.state := s_idle; -- finish to idle state
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ld_ccnt := '1'; -- and put counters in reset
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ld_bcnt := '1'; -- "
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else
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if tc_ccnt = '1' then -- last cycle of b9 ?
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n.state := s_endb0; -- finish b0
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ld_ccnt := '1'; -- "
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ce_bcnt := '1';
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else -- continue in b0 ?
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n.state := s_colb0; -- collect bx
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end if;
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end if;
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when others => null; -- -----------------------------------
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end case;
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if RESET = '1' then -- RESET seen
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ld_ccnt := '1'; -- keep all counters in reset
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ld_dcnt := '1';
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ld_bcnt := '1';
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n.state := s_idle;
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end if;
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if ld_ccnt = '1' then -- implement ccnt
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n.ccnt := CLKDIV;
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else
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n.ccnt := slv(unsigned(r.ccnt) - 1);
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end if;
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if ld_dcnt = '1' then -- implement dcnt
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n.dcnt(CDWIDTH downto 1) := (others=>'0');
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n.dcnt(0) := RXSD;
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else
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if RXSD = '1' then
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n.dcnt := slv(unsigned(r.dcnt) + 1);
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end if;
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end if;
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if ld_bcnt = '1' then -- implement bcnt
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n.bcnt := (others=>'0');
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else
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if ce_bcnt = '1' then
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n.bcnt := slv(unsigned(r.bcnt) + 1);
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end if;
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end if;
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N_REGS <= n;
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RXDATA <= r.sreg;
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RXACT <= iact;
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RXVAL <= ival;
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RXERR <= ierr;
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end process proc_next;
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end syn;
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