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-- $Id: s7_cmt_sfs_gsim.vhd 799 2016-08-21 09:20:19Z mueller $
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--
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-- Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: s7_cmt_sfs - sim
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-- Description: Series-7 CMT for simple frequency synthesis
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-- simple vhdl model, without Xilinx UNISIM primitives
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--
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-- Dependencies: -
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-- Test bench: -
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-- Target Devices: generic Series-7
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-- Tool versions: xst 14.5-14.7; viv 2014.4-2016.2; ghdl 0.29-0.33
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2016-08-18 799 1.1.1 remove 'assert false' from report statements
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-- 2016-04-09 760 1.1 BUGFIX: correct mmcm range check boundaries
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-- 2013-09-28 535 1.0 Initial version (derived from dcm_sfs_gsim)
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------------------------------------------------------------------------------
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-- Note: for test bench usage a copy of s7_cmt_sfs_gsim, with _tb instead
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-- of _gsim in file name, has been created in the /tb sub folder.
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-- Ensure to update the copy when this file is changed !!
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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entity s7_cmt_sfs is -- 7-Series CMT for simple freq. synth.
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generic (
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VCO_DIVIDE : positive := 1; -- vco clock divide
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VCO_MULTIPLY : positive := 1; -- vco clock multiply
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OUT_DIVIDE : positive := 1; -- output divide
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CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
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CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
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STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
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GEN_TYPE : string := "PLL"); -- PLL or MMCM
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port (
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CLKIN : in slbit; -- clock input
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CLKFX : out slbit; -- clock output (synthesized freq.)
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LOCKED : out slbit -- pll/mmcm locked
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);
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end s7_cmt_sfs;
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architecture sim of s7_cmt_sfs is
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signal CLK_DIVPULSE : slbit := '0';
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signal CLKOUT_PERIOD : Delay_length := 0 ns;
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signal R_CLKOUT : slbit := '0';
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signal R_LOCKED : slbit := '0';
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begin
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proc_init : process
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-- currently frequency limits taken from Artix-7 speed grade -1
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constant f_vcomin_pll : integer := 800;
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constant f_vcomax_pll : integer := 1600;
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constant f_pdmin_pll : integer := 19;
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constant f_pdmax_pll : integer := 450;
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constant f_vcomin_mmcm : integer := 600;
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constant f_vcomax_mmcm : integer := 1200;
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constant f_pdmin_mmcm : integer := 10;
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constant f_pdmax_mmcm : integer := 450;
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variable t_vco : Delay_length := 0 ns;
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variable t_vcomin : Delay_length := 0 ns;
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variable t_vcomax : Delay_length := 0 ns;
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variable t_pd : Delay_length := 0 ns;
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variable t_pdmin : Delay_length := 0 ns;
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variable t_pdmax : Delay_length := 0 ns;
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begin
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-- validate generics
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if not (GEN_TYPE = "PLL" or GEN_TYPE = "MMCM") then
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report "assert(GEN_TYPE='PLL' or GEN_TYPE='MMCM')"
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severity failure;
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end if;
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if VCO_DIVIDE/=1 or VCO_MULTIPLY/=1 or OUT_DIVIDE/=1 then
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if GEN_TYPE = "PLL" then
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-- check DIV/MULT parameter range
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if VCO_DIVIDE<1 or VCO_DIVIDE>56 or
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VCO_MULTIPLY<2 or VCO_MULTIPLY>64 or
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OUT_DIVIDE<1 or OUT_DIVIDE>128
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then
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report
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"assert(VCO_DIVIDE in 1:56 VCO_MULTIPLY in 2:64 OUT_DIVIDE in 1:128)"
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severity failure;
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end if;
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-- setup VCO and PD range check boundaries
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t_vcomin := (1000 ns / f_vcomax_pll) - 1 ps;
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t_vcomax := (1000 ns / f_vcomin_pll) + 1 ps;
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t_pdmin := (1000 ns / f_pdmax_pll) - 1 ps;
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t_pdmax := (1000 ns / f_pdmin_pll) + 1 ps;
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end if; -- GEN_TYPE = "PLL"
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if GEN_TYPE = "MMCM" then
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-- check DIV/MULT parameter range
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if VCO_DIVIDE<1 or VCO_DIVIDE>106 or
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VCO_MULTIPLY<2 or VCO_MULTIPLY>64 or
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OUT_DIVIDE<1 or OUT_DIVIDE>128
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then
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report
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"assert(VCO_DIVIDE in 1:106 VCO_MULTIPLY in 2:64 OUT_DIVIDE in 1:128)"
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severity failure;
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end if;
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-- setup VCO and PD range check boundaries
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t_vcomin := (1000 ns / f_vcomax_mmcm) - 1 ps;
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t_vcomax := (1000 ns / f_vcomin_mmcm) + 1 ps;
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t_pdmin := (1000 ns / f_pdmax_mmcm) - 1 ps;
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t_pdmax := (1000 ns / f_pdmin_mmcm) + 1 ps;
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end if; -- GEN_TYPE = "MMCM"
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-- now common check whether VCO and PD frequency is in range
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t_pd := (1 ps * (1000.0*CLKIN_PERIOD)) * VCO_DIVIDE;
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t_vco := t_pd / VCO_MULTIPLY;
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if t_vco<t_vcomin or t_vco>t_vcomax then
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report "assert(VCO frequency out of range)"
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severity failure;
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end if;
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if t_pd<t_pdmin or t_pd>t_pdmax then
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report "assert(PD frequency out of range)"
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severity failure;
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end if;
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end if; -- one factor /= 1
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wait;
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end process proc_init;
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proc_clkin : process (CLKIN)
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variable t_lastclkin : time := 0 ns;
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variable t_lastperiod : Delay_length := 0 ns;
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variable t_period : Delay_length := 0 ns;
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variable nclkin : integer := 1;
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begin
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if CLKIN'event then
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if CLKIN = '1' then -- if CLKIN rising edge
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if t_lastclkin > 0 ns then
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t_lastperiod := t_period;
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t_period := now - t_lastclkin;
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CLKOUT_PERIOD <= (t_period * VCO_DIVIDE * OUT_DIVIDE) / VCO_MULTIPLY;
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if t_lastperiod > 0 ns and abs(t_period-t_lastperiod) > 1 ps then
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report "s7_cmt_sp_sfs: CLKIN unstable" severity warning;
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end if;
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end if;
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t_lastclkin := now;
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if t_period > 0 ns then
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nclkin := nclkin - 1;
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if nclkin <= 0 then
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nclkin := VCO_DIVIDE * OUT_DIVIDE;
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CLK_DIVPULSE <= '1';
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R_LOCKED <= '1';
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end if;
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end if;
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else -- if CLKIN falling edge
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CLK_DIVPULSE <= '0';
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end if;
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end if;
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end process proc_clkin;
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proc_clkout : process
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variable t_lastclkin : time := 0 ns;
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variable t_lastperiod : Delay_length := 0 ns;
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variable t_period : Delay_length := 0 ns;
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variable nclkin : integer := 1;
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begin
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loop
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wait until CLK_DIVPULSE = '1';
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for i in 1 to VCO_MULTIPLY loop
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R_CLKOUT <= '1';
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wait for CLKOUT_PERIOD/2;
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R_CLKOUT <= '0';
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if i /= VCO_MULTIPLY then
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wait for CLKOUT_PERIOD/2;
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end if;
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end loop; -- i
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end loop;
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end process proc_clkout;
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CLKFX <= R_CLKOUT;
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LOCKED <= R_LOCKED;
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end sim;
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