OpenCores
URL https://opencores.org/ocsvn/w11/w11/trunk

Subversion Repositories w11

[/] [w11/] [tags/] [w11a_V0.74/] [rtl/] [w11a/] [pdp11.vhd] - Blame information for rev 38

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 36 wfjm
-- $Id: pdp11.vhd 750 2016-03-24 23:11:51Z mueller $
2 2 wfjm
--
3 30 wfjm
-- Copyright 2006-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4 2 wfjm
--
5
-- This program is free software; you may redistribute and/or modify it under
6
-- the terms of the GNU General Public License as published by the Free
7
-- Software Foundation, either version 2, or at your option any later version.
8
--
9
-- This program is distributed in the hope that it will be useful, but
10
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
11
-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
12
-- for complete details.
13
--
14
------------------------------------------------------------------------------
15
-- Package Name:   pdp11
16
-- Description:    Definitions for pdp11 components
17
--
18
-- Dependencies:   -
19 29 wfjm
-- Tool versions:  ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
20 25 wfjm
--
21 2 wfjm
-- Revision History: 
22
-- Date         Rev Version  Comment
23 34 wfjm
-- 2015-11-01   712   1.6.5  define sbcntl_sbf_tmu := 12; use for pdp11_tmu_sb
24
-- 2015-07-19   702   1.6.4  change DM_STAT_(DP|CO); add DM_STAT_SE
25
-- 2015-07-10   700   1.6.3  define c_cpurust_hbpt;
26
-- 2015-07-04   697   1.6.2  add pdp11_dm(hbpt|cmon); change DM_STAT_(SY|VM|CO)
27
-- 2015-06-26   695   1.6.1  add pdp11_dmscnt (add support)
28 30 wfjm
-- 2015-05-09   677   1.6    start/stop/suspend overhaul; reset overhaul
29
-- 2015-05-01   672   1.5.5  add pdp11_sys70, sys_hio70
30
-- 2015-04-30   670   1.5.4  rename pdp11_sys70 -> pdp11_reg70
31 29 wfjm
-- 2015-02-20   649   1.5.3  add pdp11_statleds
32
-- 2015-02-08   644   1.5.2  add pdp11_bram_memctl
33 27 wfjm
-- 2014-08-28   588   1.5.1  use new rlink v4 iface and 4 bit STAT
34
-- 2014-08-15   583   1.5    rb_mreq addr now 16 bit
35
-- 2014-08-10:  581   1.4.10 add c_cc_f_* field defs for condition code array
36 25 wfjm
-- 2014-07-12   569   1.4.9  dpath_stat_type: merge div_zero+div_ovfl to div_quit
37
--                           dpath_cntl_type: add munit_s_div_sr
38 13 wfjm
-- 2011-11-18   427   1.4.8  now numeric_std clean
39 9 wfjm
-- 2010-12-30   351   1.4.7  rename pdp11_core_rri->pdp11_core_rbus; use rblib
40 8 wfjm
-- 2010-10-23   335   1.4.6  rename RRI_LAM->RB_LAM;
41
-- 2010-10-16   332   1.4.5  renames of pdp11_du_drv port names
42
-- 2010-09-18   330   1.4.4  rename (adlm)box->(oalm)unit
43 2 wfjm
-- 2010-06-20   308   1.4.3  add c_ibrb_ibf_ def's
44
-- 2010-06-20   307   1.4.2  rename cpacc to cacc in vm_cntl_type, mmu_cntl_type
45
-- 2010-06-18   306   1.4.1  add racc, be to cp_addr_type; rm pdp11_ibdr_rri
46
-- 2010-06-13   305   1.4    add rnum to cp_cntl_type, cprnum to cpustat_type;
47
--                           reassign cp command codes and rename: c_cp_func_...
48
--                           -> c_cpfunc_...; remove  cpaddr_(lal|lah|inc) from
49
--                           dpath_cntl_type; add cpdout_we to dpath_cntl_type;
50
--                           reassign rbus adresses and rename: c_rb_addr_...
51
--                           -> c_rbaddr_...; rename rbus fields: c_rb_statf_...
52
--                           -> c_stat_rbf_...
53
-- 2010-06-12   304   1.3.3  add cpuwait to cp_stat_type and cpustat_type
54
-- 2010-06-11   303   1.3.2  use IB_MREQ.racc instead of RRI_REQ
55
-- 2010-05-02   287   1.3.1  rename RP_STAT->RB_STAT
56
-- 2010-05-01   285   1.3    port to rri V2 interface; drop pdp11_rri_2rp;
57
--                           rename c_rp_addr_* -> c_rb_addr_*
58
-- 2010-03-21   270   1.2.6  add pdp11_du_drv
59
-- 2009-05-30   220   1.2.5  final removal of snoopers (were already commented)
60
-- 2009-05-10   214   1.2.4  add ENA (trace enable) for _tmu; add _pdp11_tmu_sb
61
-- 2009-05-09   213   1.2.3  BUGFIX: default for inst_compl now '0'
62
-- 2008-12-14   177   1.2.2  add gpr_* fields to DM_STAT_DP
63
-- 2008-11-30   174   1.2.1  BUGFIX: add updt_dstadsrc;
64
-- 2008-08-22   161   1.2    move slvnn_m subtypes to slvtypes;
65
--                           move (and rename) intbus defs to iblib package;
66
--                           move intbus devices to ibdlib package;
67
--                           rename ubf_ --> ibf_;
68
-- 2008-05-09   144   1.1.17 use EI_ACK with _kw11l, _dl11
69
-- 2008-05-03   143   1.1.16 rename _cpursta->_cpurust
70
-- 2008-04-27   140   1.1.15 add c_cpursta_xxx defs; cpufail->cpursta in cp_stat
71
-- 2008-04-25   138   1.1.14 add BRESET port to _mmu, _vmbox, use in _irq
72
-- 2008-04-19   137   1.1.13 add _tmu,_sys70 entity, dm_stat_** types and ports
73
-- 2008-04-18   136   1.1.12 ibdr_sdreg: use RESET; ibdr_minisys: add RESET
74
-- 2008-03-02   121   1.1.11 remove snoopers; add waitsusp in cpustat_type
75
-- 2008-02-24   119   1.1.10 add lah,rps,wps commands, cp_addr_type.
76
--                           _vmbox,_mmu interface changed
77
-- 2008-02-17   117   1.1.9  add em_(mreq|sres)_type, pdp11_cache, pdp11_bram
78
-- 2008-01-27   115   1.1.8  add pdp11_ubmap, pdp11_mem70
79
-- 2008-01-26   114   1.1.7  add c_rp_addr_ibr(b) defs (for ibr addresses)
80
-- 2008-01-20   113   1.1.6  _core_rri: use RRI_LAM; _minisys: RRI_LAM vector
81
-- 2008-01-20   112   1.1.5  added ibdr_minisys; _ibdr_rri
82
-- 2008-01-06   111   1.1.4  rename ibdr_kw11l->ibd_kw11l; add ibdr_(dl11|rk11)
83
--                           mod pdp11_intmap;
84
-- 2008-01-05   110   1.1.3  delete _mmu_regfile; rename _mmu_regs->_mmu_sadr
85
--                           rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
86
--                           add ibdr_kw11l.
87
-- 2008-01-01   109   1.1.2  _vmbox w/ IB_SRES_(CPU|EXT); remove vm_regs_type
88
-- 2007-12-30   108   1.1.1  add ibdr_sdreg, ubf_byte[01]
89
-- 2007-12-30   107   1.1    use IB_MREQ/IB_SRES interface now; remove DMA port
90
-- 2007-08-16    74   1.0.6  add AP_LAM interface to pdp11_core_rri
91
-- 2007-08-12    73   1.0.5  add c_rp_addr_xxx and c_rp_statf_xxx def's
92
-- 2007-08-10    72   1.0.4  added c_cp_func_xxx constant def's for commands
93
-- 2007-07-15    66   1.0.3  rename pdp11_top -> pdp11_core
94
-- 2007-07-02    63   1.0.2  reordered ports on pdp11_top (by function, not i/o)
95
-- 2007-06-14    56   1.0.1  Use slvtypes.all
96
-- 2007-05-12    26   1.0    Initial version 
97
------------------------------------------------------------------------------
98
 
99
library ieee;
100
use ieee.std_logic_1164.all;
101 13 wfjm
use ieee.numeric_std.all;
102 2 wfjm
 
103
use work.slvtypes.all;
104
use work.iblib.all;
105 9 wfjm
use work.rblib.all;
106 2 wfjm
 
107
package pdp11 is
108
 
109
  type psw_type is record               -- processor status
110
    cmode : slv2;                       -- current mode
111
    pmode : slv2;                       -- previous mode
112
    rset : slbit;                       -- register set
113
    pri : slv3;                         -- processor priority
114
    tflag : slbit;                      -- trace flag
115
    cc : slv4;                          -- condition codes (NZVC).
116
  end record psw_type;
117
 
118 27 wfjm
  constant c_cc_f_n: integer := 3;      -- condition code: n
119
  constant c_cc_f_z: integer := 2;      -- condition code: z
120
  constant c_cc_f_v: integer := 1;      -- condition code: v
121
  constant c_cc_f_c: integer := 0;      -- condition code: c
122
 
123 2 wfjm
  constant psw_init : psw_type := (
124
    "00","00",                          -- cmode, pmode  (=kernel)
125
    '0',"111",'0',                      -- rset, pri (=7), tflag
126
    "0000"                              -- cc     NZVC=0
127
  );
128
 
129
  constant c_psw_kmode : slv2 := "00";  -- processor mode: kernel
130
  constant c_psw_smode : slv2 := "01";  -- processor mode: supervisor
131
  constant c_psw_umode : slv2 := "11";  -- processor mode: user
132
 
133
  subtype  psw_ibf_cmode  is integer range 15 downto 14;
134
  subtype  psw_ibf_pmode  is integer range 13 downto 12;
135
  constant psw_ibf_rset:  integer := 11;
136
  subtype  psw_ibf_pri    is integer range  7 downto  5;
137
  constant psw_ibf_tflag: integer :=  4;
138
  subtype  psw_ibf_cc     is integer range  3 downto  0;
139
 
140
  type sarsdr_type is record            -- combined SAR/SDR MMU status
141
    saf : slv16;                        -- segment address field
142
    slf : slv7;                         -- segment length field
143
    ed : slbit;                         -- expansion direction
144
    acf : slv3;                         -- access control field
145
  end record sarsdr_type;
146
 
147
  constant sarsdr_init : sarsdr_type := (
148
    (others=>'0'),                      -- saf
149
    "0000000",'0',"000"                 -- slf, ed, acf
150
  );
151
 
152
  type dpath_cntl_type is record        -- data path control
153
    gpr_asrc : slv3;                    -- src register address
154
    gpr_adst : slv3;                    -- dst register address
155
    gpr_mode : slv2;                    -- psw mode for gpr access
156
    gpr_rset : slbit;                   -- register set
157
    gpr_we : slbit;                     -- gpr write enable
158
    gpr_bytop : slbit;                  -- gpr high byte enable
159
    gpr_pcinc : slbit;                  -- pc increment enable
160
    psr_ccwe : slbit;                   -- enable update cc
161
    psr_we: slbit;                      -- write enable psw (from DIN)
162
    psr_func : slv3;                    -- write function psw (from DIN)
163
    dsrc_sel : slbit;                   -- src data register source select
164
    dsrc_we : slbit;                    -- src data register write enable
165
    ddst_sel : slbit;                   -- dst data register source select
166
    ddst_we : slbit;                    -- dst data register write enable
167
    dtmp_sel : slv2;                    -- tmp data register source select
168
    dtmp_we : slbit;                    -- tmp data register write enable
169 8 wfjm
    ounit_asel : slv2;                  -- ounit a port selector
170
    ounit_azero : slbit;                -- ounit a port force zero
171
    ounit_const : slv9;                 -- ounit b port const
172
    ounit_bsel : slv2;                  -- ounit b port selector
173
    ounit_opsub : slbit;                -- ounit operation
174
    aunit_srcmod : slv2;                -- aunit src port modifier
175
    aunit_dstmod : slv2;                -- aunit dst port modifier
176
    aunit_cimod : slv2;                 -- aunit ci port modifier
177
    aunit_cc1op : slbit;                -- aunit use cc modes (1 op instruction)
178
    aunit_ccmode : slv3;                -- aunit cc port mode
179
    aunit_bytop : slbit;                -- aunit byte operation
180
    lunit_func : slv4;                  -- lunit function
181
    lunit_bytop : slbit;                -- lunit byte operation
182
    munit_func : slv2;                  -- munit function
183
    munit_s_div : slbit;                -- munit s_opg_div state
184
    munit_s_div_cn : slbit;             -- munit s_opg_div_cn state
185
    munit_s_div_cr : slbit;             -- munit s_opg_div_cr state
186 25 wfjm
    munit_s_div_sr : slbit;             -- munit s_opg_div_sr state
187 8 wfjm
    munit_s_ash : slbit;                -- munit s_opg_ash state
188
    munit_s_ash_cn : slbit;             -- munit s_opg_ash_cn state
189
    munit_s_ashc : slbit;               -- munit s_opg_ashc state
190
    munit_s_ashc_cn : slbit;            -- munit s_opg_ashc_cn state
191 2 wfjm
    ireg_we : slbit;                    -- ireg register write enable
192
    cres_sel : slv3;                    -- result bus (cres) select
193
    dres_sel : slv3;                    -- result bus (dres) select
194
    vmaddr_sel : slv2;                  -- virtual address select
195
    cpdout_we : slbit;                  -- capture dres for cpdout
196
  end record dpath_cntl_type;
197
 
198
  constant dpath_cntl_init : dpath_cntl_type := (
199
    "000","000","00",'0','0','0','0',   -- gpr
200
    '0','0',"000",                      -- psr
201
    '0','0','0','0',"00",'0',           -- dsrc,..,dtmp
202 8 wfjm
    "00",'0',"000000000","00",'0',      -- ounit
203
    "00","00","00",'0',"000",'0',       -- aunit
204
    "0000",'0',                         -- lunit
205 25 wfjm
    "00",'0','0','0','0','0','0','0','0',-- munit
206 2 wfjm
    '0',"000","000","00",'0'            -- rest
207
  );
208
 
209
  constant c_dpath_dsrc_src  : slbit := '0'; -- DSRC = R(SRC)
210
  constant c_dpath_dsrc_res  : slbit := '1'; -- DSRC = DRES
211
  constant c_dpath_ddst_dst  : slbit := '0'; -- DDST = R(DST)
212
  constant c_dpath_ddst_res  : slbit := '1'; -- DDST = DRES
213
 
214
  constant c_dpath_dtmp_dsrc  : slv2 := "00"; -- DTMP = DSRC
215
  constant c_dpath_dtmp_psw   : slv2 := "01"; -- DTMP = PSW
216
  constant c_dpath_dtmp_dres  : slv2 := "10"; -- DTMP = DRES
217
  constant c_dpath_dtmp_drese : slv2 := "11"; -- DTMP = DRESE
218
 
219 8 wfjm
  constant c_dpath_res_ounit  : slv3 := "000"; -- D/CRES = OUNIT
220
  constant c_dpath_res_aunit  : slv3 := "001"; -- D/CRES = AUNIT
221
  constant c_dpath_res_lunit  : slv3 := "010"; -- D/CRES = LUNIT
222
  constant c_dpath_res_munit  : slv3 := "011"; -- D/CRES = MUNIT
223 2 wfjm
  constant c_dpath_res_vmdout : slv3 := "100"; -- D/CRES = VMDOUT
224
  constant c_dpath_res_fpdout : slv3 := "101"; -- D/CRES = FPDOUT
225
  constant c_dpath_res_ireg   : slv3 := "110"; -- D/CRES = IREG
226
  constant c_dpath_res_cpdin  : slv3 := "111"; -- D/CRES = CPDIN
227
 
228
  constant c_dpath_vmaddr_dsrc : slv2 := "00"; -- VMADDR = DSRC
229
  constant c_dpath_vmaddr_ddst : slv2 := "01"; -- VMADDR = DDST
230
  constant c_dpath_vmaddr_pc   : slv2 := "10"; -- VMADDR = PC
231
  constant c_dpath_vmaddr_dtmp : slv2 := "11"; -- VMADDR = DTMP
232
 
233
  type dpath_stat_type is record        -- data path status
234
    ccout_z : slbit;                    -- current effective Z cc flag
235
    shc_tc : slbit;                     -- last shc cycle (shc==0)
236 25 wfjm
    div_cr : slbit;                     -- division: remainder correction needed
237 2 wfjm
    div_cq : slbit;                     -- division: quotient correction needed
238 25 wfjm
    div_quit : slbit;                   -- division: abort (0/ or /0 or V=1)
239 2 wfjm
  end record dpath_stat_type;
240
 
241
  constant dpath_stat_init : dpath_stat_type := (others=>'0');
242
 
243
  type decode_stat_type is record       -- decode status
244
    is_dstmode0 : slbit;                -- dest. is register mode
245
    is_srcpc : slbit;                   -- source is pc
246
    is_srcpcmode1 : slbit;              -- source is pc and mode=1
247
    is_dstpc : slbit;                   -- dest. is pc
248
    is_dstw_reg : slbit;                -- dest. register to be written
249
    is_dstw_pc  : slbit;                -- pc register to be written
250
    is_rmwop : slbit;                   -- read-modify-write operation
251
    is_bytop : slbit;                   -- byte operation
252
    is_res : slbit;                     -- reserved operation code
253
    op_rtt : slbit;                     -- RTT instruction
254
    op_mov : slbit;                     -- MOV instruction
255
    trap_vec : slv3;                    -- trap vector addr bits 4:2
256
    force_srcsp : slbit;                -- force src register to be sp
257
    updt_dstadsrc : slbit;              -- update dsrc in dsta flow
258 8 wfjm
    aunit_srcmod : slv2;                -- aunit src port modifier
259
    aunit_dstmod : slv2;                -- aunit dst port modifier
260
    aunit_cimod : slv2;                 -- aunit ci port modifier
261
    aunit_cc1op : slbit;                -- aunit use cc modes (1 op instruction)
262
    aunit_ccmode : slv3;                -- aunit cc port mode
263
    lunit_func : slv4;                  -- lunit function
264
    munit_func : slv2;                  -- munit function
265 2 wfjm
    res_sel : slv3;                     -- result bus (cres/dres) select
266
    fork_op : slv4;                     -- op fork after idecode state
267
    fork_srcr : slv2;                   -- src-read fork after idecode state
268
    fork_dstr : slv2;                   -- dst-read fork after src read state
269
    fork_dsta : slv2;                   -- dst-addr fork after idecode state
270
    fork_opg : slv4;                    -- opg fork
271
    fork_opa : slv3;                    -- opa fork
272
    do_fork_op : slbit;                 -- execute fork_op
273
    do_fork_srcr : slbit;               -- execute fork_srcr
274
    do_fork_dstr : slbit;               -- execute fork_dstr
275
    do_fork_dsta : slbit;               -- execute fork_dsta
276
    do_fork_opg : slbit;                -- execute fork_opg
277
    do_pref_dec : slbit;                -- can do prefetch at decode phase
278
  end record decode_stat_type;
279
 
280
  constant decode_stat_init : decode_stat_type := (
281
    '0','0','0','0','0','0','0','0','0', -- is_
282
    '0','0',"000",'0','0',               -- op_, trap_, force_, updt_
283 8 wfjm
    "00","00","00",'0',"000",            -- aunit_
284
    "0000","00","000",                   -- lunit_, munit_, res_
285 2 wfjm
    "0000","00","00","00","0000","000",  -- fork_
286
    '0','0','0','0','0',                 -- do_fork_
287
    '0'                                  -- do_pref_
288
  );
289
 
290
  constant c_fork_op_halt : slv4 := "0000";
291
  constant c_fork_op_wait : slv4 := "0001";
292
  constant c_fork_op_rtti : slv4 := "0010";
293
  constant c_fork_op_trap : slv4 := "0011";
294
  constant c_fork_op_reset: slv4 := "0100";
295
  constant c_fork_op_rts :  slv4 := "0101";
296
  constant c_fork_op_spl :  slv4 := "0110";
297
  constant c_fork_op_mcc :  slv4 := "0111";
298
  constant c_fork_op_br :   slv4 := "1000";
299
  constant c_fork_op_mark : slv4 := "1001";
300
  constant c_fork_op_sob :  slv4 := "1010";
301
  constant c_fork_op_mtp :  slv4 := "1011";
302
 
303
  constant c_fork_srcr_def : slv2:= "00";
304
  constant c_fork_srcr_inc : slv2:= "01";
305
  constant c_fork_srcr_dec : slv2:= "10";
306
  constant c_fork_srcr_ind : slv2:= "11";
307
 
308
  constant c_fork_dstr_def : slv2:= "00";
309
  constant c_fork_dstr_inc : slv2:= "01";
310
  constant c_fork_dstr_dec : slv2:= "10";
311
  constant c_fork_dstr_ind : slv2:= "11";
312
 
313
  constant c_fork_dsta_def : slv2:= "00";
314
  constant c_fork_dsta_inc : slv2:= "01";
315
  constant c_fork_dsta_dec : slv2:= "10";
316
  constant c_fork_dsta_ind : slv2:= "11";
317
 
318
  constant c_fork_opg_gen  : slv4 := "0000";
319
  constant c_fork_opg_wdef : slv4 := "0001";
320
  constant c_fork_opg_winc : slv4 := "0010";
321
  constant c_fork_opg_wdec : slv4 := "0011";
322
  constant c_fork_opg_wind : slv4 := "0100";
323
  constant c_fork_opg_mul  : slv4 := "0101";
324
  constant c_fork_opg_div  : slv4 := "0110";
325
  constant c_fork_opg_ash  : slv4 := "0111";
326
  constant c_fork_opg_ashc : slv4 := "1000";
327
 
328
  constant c_fork_opa_jsr :     slv3 := "000";
329
  constant c_fork_opa_jmp :     slv3 := "001";
330
  constant c_fork_opa_mtp :     slv3 := "010";
331
  constant c_fork_opa_mfp_reg : slv3 := "011";
332
  constant c_fork_opa_mfp_mem : slv3 := "100";
333
 
334
  -- Note: MSB=0 are 'normal' states, MSB=1 are fatal errors
335
  constant c_cpurust_init   : slv4 := "0000";  -- cpu in init state
336
  constant c_cpurust_halt   : slv4 := "0001";  -- cpu executed HALT
337
  constant c_cpurust_reset  : slv4 := "0010";  -- cpu was reset    
338
  constant c_cpurust_stop   : slv4 := "0011";  -- cpu was stopped
339
  constant c_cpurust_step   : slv4 := "0100";  -- cpu was stepped
340
  constant c_cpurust_susp   : slv4 := "0101";  -- cpu was suspended
341 34 wfjm
  constant c_cpurust_hbpt   : slv4 := "0110";  -- cpu had hardware bpt
342 2 wfjm
  constant c_cpurust_runs   : slv4 := "0111";  -- cpu running
343
  constant c_cpurust_vecfet : slv4 := "1000";  -- vector fetch error halt
344
  constant c_cpurust_recrsv : slv4 := "1001";  -- recursive red-stack halt
345
  constant c_cpurust_sfail  : slv4 := "1100";  -- sequencer failure
346
  constant c_cpurust_vfail  : slv4 := "1101";  -- vmbox failure
347
 
348
  type cpustat_type is record           -- CPU status
349
    cmdbusy : slbit;                    -- command busy
350
    cmdack  : slbit;                    -- command acknowledge
351
    cmderr  : slbit;                    -- command error
352
    cmdmerr : slbit;                    -- command memory access error
353
    cpugo   : slbit;                    -- CPU go state
354
    cpustep : slbit;                    -- CPU step flag
355 30 wfjm
    cpususp : slbit;                    -- CPU susp flag
356 2 wfjm
    cpuwait : slbit;                    -- CPU wait flag
357
    cpurust : slv4;                     -- CPU run status
358 30 wfjm
    suspint : slbit;                    -- internal suspend flag
359
    suspext : slbit;                    -- external suspend flag
360 2 wfjm
    cpfunc  : slv5;                     -- current control port function
361
    cprnum  : slv3;                     -- current control port register number
362
    waitsusp : slbit;                   -- WAIT instruction suspended
363 30 wfjm
    itimer : slbit;                     -- ITIMER pulse
364
    creset : slbit;                     -- CRESET pulse
365
    breset : slbit;                     -- BRESET pulse
366
    intack : slbit;                     -- INT_ACK pulse
367 2 wfjm
    intvect  : slv9_2;                  -- current interrupt vector
368
    trap_mmu : slbit;                   -- mmu trace trap pending
369
    trap_ysv : slbit;                   -- ysv trap pending
370
    prefdone : slbit;                   -- prefetch done
371
    do_gprwe : slbit;                   -- pending gpr_we
372
    do_intrsv : slbit;                  -- active rsv interrupt sequence
373
  end record cpustat_type;
374
 
375
  constant cpustat_init : cpustat_type := (
376 30 wfjm
    '0','0','0','0',                    -- cmdbusy,cmdack,cmderr,cmdmerr
377
    '0','0','0','0',                    -- cpugo,cpustep,cpususp,cpuwait
378 2 wfjm
    c_cpurust_init,                     -- cpurust
379 30 wfjm
    '0','0',                            -- suspint,suspext
380 2 wfjm
    "00000","000",                      -- cpfunc, cprnum
381
    '0',                                -- waitsusp
382 30 wfjm
    '0','0','0','0',                    -- itimer,creset,breset,intack
383 2 wfjm
    (others=>'0'),                      -- intvect 
384
    '0','0','0',                        -- trap_(mmu|ysv), prefdone
385
    '0','0'                             -- do_gprwe, do_intrsv
386
  );
387
 
388
  type cpuerr_type is record            -- CPU error register
389
    illhlt : slbit;                     -- illegal halt (in non-kernel mode)
390
    adderr : slbit;                     -- address error (odd, jmp/jsr reg)
391
    nxm : slbit;                        -- non-existent memory
392
    iobto : slbit;                      -- I/O bus timeout (non-exist UB)
393
    ysv : slbit;                        -- yellow stack violation
394
    rsv : slbit;                        -- red stack violation
395
  end record cpuerr_type;
396
 
397
  constant cpuerr_init : cpuerr_type := (others=>'0');
398
 
399
  type vm_cntl_type is record           -- virt memory control port
400
    req : slbit;                        -- request
401
    wacc : slbit;                       -- write access
402
    macc : slbit;                       -- modify access (r-m-w sequence)
403
    cacc : slbit;                       -- console access
404
    bytop : slbit;                      -- byte operation
405
    dspace : slbit;                     -- dspace operation
406
    kstack : slbit;                     -- access through kernel stack
407
    intrsv : slbit;                     -- active rsv interrupt sequence
408
    mode : slv2;                        -- mode
409
    trap_done : slbit;                  -- mmu trap taken (to set ssr0 bit)
410
  end record vm_cntl_type;
411
 
412
  constant vm_cntl_init : vm_cntl_type := (
413
    '0','0','0','0',                    -- req, wacc, macc,cacc
414
    '0','0','0',                        -- bytop, dspace, kstack
415
    '0',"00",'0'                        -- intrsv, mode, trap_done
416
  );
417
 
418
  type vm_stat_type is record           -- virt memory status port
419
    ack : slbit;                        -- acknowledge
420
    err : slbit;                        -- error (see err_xxx for reason)
421
    fail : slbit;                       -- failure (machine check)
422
    err_odd : slbit;                    -- abort: odd address error
423
    err_mmu : slbit;                    -- abort: mmu reject
424
    err_nxm : slbit;                    -- abort: non-existing memory
425
    err_iobto : slbit;                  -- abort: non-existing I/O resource
426
    err_rsv : slbit;                    -- abort: red stack violation
427
    trap_ysv : slbit;                   -- trap: yellow stack violation
428
    trap_mmu : slbit;                   -- trap: mmu trace trap
429
  end record vm_stat_type;
430
 
431
  constant vm_stat_init : vm_stat_type := (others=>'0');
432
 
433
  type em_mreq_type is record           -- external memory - master request
434
    req : slbit;                        -- request
435
    we : slbit;                         -- write enable
436
    be : slv2;                          -- byte enables
437
    cancel : slbit;                     -- cancel request
438
    addr : slv22_1;                     -- address
439
    din : slv16;                        -- data in (input to memory)
440
  end record em_mreq_type;
441
 
442
  constant em_mreq_init : em_mreq_type := (
443
    '0','0',"00",'0',                   -- req, we, be, cancel
444
    (others=>'0'),(others=>'0')         -- addr, din
445
  );
446
 
447
  type em_sres_type is record           -- external memory - slave response
448
    ack_r  : slbit;                     -- acknowledge read
449
    ack_w  : slbit;                     -- acknowledge write
450
    dout : slv16;                       -- data out (output from memory)
451
  end record em_sres_type;
452
 
453
  constant em_sres_init : em_sres_type := (
454
    '0','0',                            -- ack_r, ack_w
455
    (others=>'0')                       -- dout
456
  );
457
 
458
  type mmu_cntl_type is record          -- mmu control port
459
    req : slbit;                        -- translate request
460
    wacc : slbit;                       -- write access
461
    macc : slbit;                       -- modify access (r-m-w sequence)
462
    cacc : slbit;                       -- console access (bypass mmu)
463
    dspace : slbit;                     -- dspace access
464
    mode : slv2;                        -- processor mode
465
    trap_done : slbit;                  -- mmu trap taken (set ssr0 bit)
466
  end record mmu_cntl_type;
467
 
468
  constant mmu_cntl_init : mmu_cntl_type := (
469
    '0','0','0','0',                    -- req, wacc, macc, cacc
470
    '0',"00",'0'                        -- dspace, mode, trap_done
471
  );
472
 
473
  type mmu_stat_type is record          -- mmu status port
474
    vaok : slbit;                       -- virtual address valid
475
    trap : slbit;                       -- mmu trap request
476
    ena_mmu : slbit;                    -- mmu enable (ssr0 bit 0)
477
    ena_22bit : slbit;                  -- mmu in 22 bit mode (ssr3 bit 4)
478
    ena_ubmap : slbit;                  -- ubmap enable (ssr3 bit 5)
479
  end record mmu_stat_type;
480
 
481
  constant mmu_stat_init : mmu_stat_type := (others=>'0');
482
 
483
  type mmu_moni_type is record          -- mmu monitor port
484
    istart : slbit;                     -- instruction start
485
    idone : slbit;                      -- instruction done
486
    pc : slv16;                         -- PC of new instruction
487
    regmod : slbit;                     -- register modified
488
    regnum : slv3;                      -- register number
489
    delta : slv4;                       -- register offset
490
    isdec : slbit;                      -- offset to be subtracted
491
    trace_prev : slbit;                 -- use ssr12 trace state of prev. state
492
  end record mmu_moni_type;
493
 
494
  constant mmu_moni_init : mmu_moni_type := (
495
    '0','0',(others=>'0'),              -- istart, idone, pc
496
    '0',"000","0000",                   -- regmod, regnum, delta
497
    '0','0'                             -- isdec, trace_prev
498
  );
499
 
500
  type mmu_ssr0_type is record          -- MMU ssr0
501
    abo_nonres : slbit;                 -- abort non resident
502
    abo_length : slbit;                 -- abort segment length
503
    abo_rdonly : slbit;                 -- abort read-only
504
    trap_mmu : slbit;                   -- trap management
505
    ena_trap : slbit;                   -- enable traps
506
    inst_compl : slbit;                 -- instruction complete
507
    seg_mode : slv2;                    -- segement mode
508
    dspace : slbit;                     -- address space (D=1, I=0)
509
    seg_num : slv3;                     -- segment number
510
    ena_mmu : slbit;                    -- enable memory management
511
    trace_prev : slbit;                 -- ssr12 trace status in prev. state
512
  end record mmu_ssr0_type;
513
 
514
  constant mmu_ssr0_init : mmu_ssr0_type := (
515
    inst_compl=>'0', seg_mode=>"00", seg_num=>"000",
516
    others=>'0'
517
  );
518
 
519
  type mmu_ssr1_type is record          -- MMU ssr1
520
    rb_delta : slv5;                    -- RB: amount change
521
    rb_num : slv3;                      -- RB: register number
522
    ra_delta : slv5;                    -- RA: amount change
523
    ra_num : slv3;                      -- RA: register number
524
  end record mmu_ssr1_type;
525
 
526
  constant mmu_ssr1_init : mmu_ssr1_type := (
527
    "00000","000",                      -- rb_...
528
    "00000","000"                       -- ra_...
529
  );
530
 
531
  type mmu_ssr3_type is record          -- MMU ssr3
532
    ena_ubmap : slbit;                  -- enable unibus mapping
533
    ena_22bit : slbit;                  -- enable 22 bit mapping
534
    dspace_km : slbit;                  -- enable dspace kernel
535
    dspace_sm : slbit;                  -- enable dspace supervisor
536
    dspace_um : slbit;                  -- enable dspace user
537
  end record mmu_ssr3_type;
538
 
539
  constant mmu_ssr3_init : mmu_ssr3_type := (others=>'0');
540
 
541
-- control port definitions --------------------------------------------------
542
 
543
  type cp_cntl_type is record           -- control port control
544
    req : slbit;                        -- request
545
    func : slv5;                        -- function
546
    rnum : slv3;                        -- register number
547
  end record cp_cntl_type;
548
 
549 30 wfjm
  constant c_cpfunc_noop    : slv5 := "00000";  -- noop : no operation
550
  constant c_cpfunc_start   : slv5 := "00001";  -- sta  : cpu start
551
  constant c_cpfunc_stop    : slv5 := "00010";  -- sto  : cpu stop 
552
  constant c_cpfunc_step    : slv5 := "00011";  -- cont : cpu step
553
  constant c_cpfunc_creset  : slv5 := "00100";  -- step : cpu cpu reset
554
  constant c_cpfunc_breset  : slv5 := "00101";  -- rst  : cpu bus reset
555
  constant c_cpfunc_suspend : slv5 := "00110";  -- rst  : cpu suspend
556
  constant c_cpfunc_resume  : slv5 := "00111";  -- rst  : cpu resume
557 2 wfjm
 
558 30 wfjm
  constant c_cpfunc_rreg    : slv5 := "10000";  -- rreg : read register
559
  constant c_cpfunc_wreg    : slv5 := "10001";  -- wreg : write register
560
  constant c_cpfunc_rpsw    : slv5 := "10010";  -- rpsw : read psw
561
  constant c_cpfunc_wpsw    : slv5 := "10011";  -- wpsw : write psw
562
  constant c_cpfunc_rmem    : slv5 := "10100";  -- rmem : read memory
563
  constant c_cpfunc_wmem    : slv5 := "10101";  -- wmem : write memory
564
 
565 2 wfjm
  constant cp_cntl_init : cp_cntl_type := ('0',c_cpfunc_noop,"000");
566
 
567
  type cp_stat_type is record           -- control port status
568
    cmdbusy : slbit;                    -- command busy
569
    cmdack : slbit;                     -- command acknowledge
570
    cmderr : slbit;                     -- command error
571
    cmdmerr : slbit;                    -- command memory access error
572
    cpugo : slbit;                      -- CPU go state
573
    cpustep : slbit;                    -- CPU step flag
574
    cpuwait : slbit;                    -- CPU wait flag
575 30 wfjm
    cpususp : slbit;                    -- CPU susp flag
576 2 wfjm
    cpurust : slv4;                     -- CPU run status
577 30 wfjm
    suspint : slbit;                    -- internal suspend
578
    suspext : slbit;                    -- external suspend
579 2 wfjm
  end record cp_stat_type;
580
 
581
  constant cp_stat_init : cp_stat_type := (
582
    '0','0','0','0',                    -- cmd...
583
    '0','0','0','0',                    -- cpu...
584 30 wfjm
    (others=>'0'),                      -- cpurust
585
    '0','0'                             -- susp...
586 2 wfjm
  );
587
 
588
  type cp_addr_type is record           -- control port address
589
    addr : slv22_1;                     -- address
590 28 wfjm
    racc : slbit;                       -- ibus remote access
591 2 wfjm
    be : slv2;                          -- byte enables
592
    ena_22bit : slbit;                  -- enable 22 bit mode
593
    ena_ubmap : slbit;                  -- enable unibus mapper
594
  end record cp_addr_type;
595
 
596
  constant cp_addr_init : cp_addr_type := (
597
    (others=>'0'),                      -- addr
598
    '0',"00",                           -- racc, be
599
    '0','0'                             -- ena_...
600
  );
601
 
602
-- debug and monitoring port definitions -------------------------------------
603
 
604 34 wfjm
  type dm_stat_se_type is record        -- debug and monitor status - sequencer
605
    istart : slbit;                     -- instruction start
606
    idone  : slbit;                     -- instruction done
607
    vfetch : slbit;                     -- vector fetch
608
    snum : slv8;                        -- current state number
609
  end record dm_stat_se_type;
610 2 wfjm
 
611 34 wfjm
  constant dm_stat_se_init : dm_stat_se_type := (
612
    '0','0','0',                        -- istart,idone,vfetch
613
    (others=>'0')                       -- snum
614
  );
615
 
616 2 wfjm
  type dm_stat_dp_type is record        -- debug and monitor status - dpath
617
    pc : slv16;                         -- pc
618
    psw : psw_type;                     -- psw
619 34 wfjm
    psr_we: slbit;                      -- psr_we
620 2 wfjm
    ireg : slv16;                       -- ireg
621
    ireg_we : slbit;                    -- ireg we
622
    dsrc : slv16;                       -- dsrc register
623 34 wfjm
    dsrc_we: slbit;                     -- dsrc we
624 2 wfjm
    ddst : slv16;                       -- ddst register
625 34 wfjm
    ddst_we : slbit;                    -- ddst we
626 2 wfjm
    dtmp : slv16;                       -- dtmp register
627 34 wfjm
    dtmp_we : slbit;                    -- dtmp we
628 2 wfjm
    dres : slv16;                       -- dres bus
629 34 wfjm
    cpdout_we : slbit;                  -- cpdout we
630 2 wfjm
    gpr_adst : slv3;                    -- gpr dst regsiter
631
    gpr_mode : slv2;                    -- gpr mode
632
    gpr_bytop : slbit;                  -- gpr bytop
633
    gpr_we : slbit;                     -- gpr we
634
  end record dm_stat_dp_type;
635
 
636
  constant dm_stat_dp_init : dm_stat_dp_type := (
637
    (others=>'0'),                      -- pc
638 34 wfjm
    psw_init,'0',                       -- psw,psr_we
639
    (others=>'0'),'0',                  -- ireg,ireg_we
640
    (others=>'0'),'0',                  -- dsrc,dsrc_we
641
    (others=>'0'),'0',                  -- ddst,ddst_we
642
    (others=>'0'),'0',                  -- dtmp,dtmp_we
643
    (others=>'0'),                      -- dres
644
    '0',                                -- cpdout_we
645 2 wfjm
    (others=>'0'),(others=>'0'),        -- gpr_adst, gpr_mode
646
    '0','0'                             -- gpr_bytop, gpr_we
647
  );
648
 
649
  type dm_stat_vm_type is record        -- debug and monitor status - vmbox
650 34 wfjm
    vmcntl : vm_cntl_type;              -- vmbox: control
651
    vmaddr : slv16;                     -- vmbox: address
652
    vmdin  : slv16;                     -- vmbox: data in
653
    vmstat : vm_stat_type;              -- vmbox: status
654
    vmdout : slv16;                     -- vmbox: data out
655
    ibmreq : ib_mreq_type;              -- ibus: request
656
    ibsres : ib_sres_type;              -- ibus: response
657
    emmreq : em_mreq_type;              -- external memory: request
658
    emsres : em_sres_type;              -- external memory: response
659 2 wfjm
  end record dm_stat_vm_type;
660
 
661 34 wfjm
  constant dm_stat_vm_init : dm_stat_vm_type := (
662
    vm_cntl_init,                       -- vmcntl
663
    (others=>'0'),                      -- vmaddr
664
    (others=>'0'),                      -- vmdin
665
    vm_stat_init,                       -- vmstat
666
    (others=>'0'),                      -- vmdout
667
    ib_mreq_init,                       -- ibmreq
668
    ib_sres_init,                       -- ibsres
669
    em_mreq_init,                       -- emmreq
670
    em_sres_init                        -- emsres
671
    );
672 2 wfjm
 
673
  type dm_stat_co_type is record        -- debug and monitor status - core
674
    cpugo : slbit;                      -- cpugo state flag
675 34 wfjm
    cpustep : slbit;                    -- cpustep state flag
676 30 wfjm
    cpususp : slbit;                    -- cpususp state flag
677
    suspint : slbit;                    -- suspint state flag
678
    suspext : slbit;                    -- suspext state flag
679 2 wfjm
  end record dm_stat_co_type;
680
 
681 30 wfjm
  constant dm_stat_co_init : dm_stat_co_type := (
682 34 wfjm
    '0','0','0',                        -- cpu...
683 30 wfjm
    '0','0'                             -- susp...
684
  );
685 2 wfjm
 
686
  type dm_stat_sy_type is record        -- debug and monitor status - system
687
    chit : slbit;                       -- cache hit
688 34 wfjm
    dummy : slbit;                      -- ... sorry records must have two ...
689 2 wfjm
  end record dm_stat_sy_type;
690
 
691 30 wfjm
  constant dm_stat_sy_init : dm_stat_sy_type := (
692 34 wfjm
    '0',                                -- chit
693
    '0'
694 30 wfjm
  );
695 2 wfjm
 
696
-- rbus interface definitions ------------------------------------------------
697
 
698
  constant c_rbaddr_conf : slv5 := "00000"; -- R/W configuration reg
699
  constant c_rbaddr_cntl : slv5 := "00001"; -- -/F  control reg
700
  constant c_rbaddr_stat : slv5 := "00010"; -- R/- status reg
701
  constant c_rbaddr_psw  : slv5 := "00011"; -- R/W psw access
702
  constant c_rbaddr_al   : slv5 := "00100"; -- R/W address low reg
703
  constant c_rbaddr_ah   : slv5 := "00101"; -- R/W address high reg
704
  constant c_rbaddr_mem  : slv5 := "00110"; -- R/W memory access
705
  constant c_rbaddr_memi : slv5 := "00111"; -- R/W memory access; inc addr
706
 
707
  constant c_rbaddr_r0   : slv5 := "01000"; -- R/W gpr 0
708
  constant c_rbaddr_r1   : slv5 := "01001"; -- R/W gpr 1
709
  constant c_rbaddr_r2   : slv5 := "01010"; -- R/W gpr 2
710
  constant c_rbaddr_r3   : slv5 := "01011"; -- R/W gpr 3
711
  constant c_rbaddr_r4   : slv5 := "01100"; -- R/W gpr 4
712
  constant c_rbaddr_r5   : slv5 := "01101"; -- R/W gpr 5
713
  constant c_rbaddr_sp   : slv5 := "01110"; -- R/W gpr 6 (sp)
714
  constant c_rbaddr_pc   : slv5 := "01111"; -- R/W gpr 7 (pc)
715
 
716 28 wfjm
  constant c_rbaddr_membe: slv5 := "10000"; -- R/W memory write byte enables
717 2 wfjm
 
718 28 wfjm
  subtype  c_al_rbf_addr        is integer range 15 downto 1;  -- al: address
719
  constant c_ah_rbf_ena_ubmap:  integer :=  7;                 -- ah: ubmap
720
  constant c_ah_rbf_ena_22bit:  integer :=  6;                 -- ah: 22bit
721
  subtype  c_ah_rbf_addr        is integer range  5 downto 0;  -- ah: address
722 2 wfjm
 
723 30 wfjm
  constant c_stat_rbf_suspext:  integer := 9;  -- stat field: suspext
724
  constant c_stat_rbf_suspint:  integer := 8;  -- stat field: suspint
725
  subtype  c_stat_rbf_cpurust   is integer range  7 downto  4;  -- cpurust
726
  constant c_stat_rbf_cpususp:  integer := 3;  -- stat field: cpususp
727
  constant c_stat_rbf_cpugo:    integer := 2;  -- stat field: cpugo
728
  constant c_stat_rbf_cmdmerr:  integer := 1;  -- stat field: cmdmerr
729 2 wfjm
  constant c_stat_rbf_cmderr:   integer := 0;  -- stat field: cmderr
730
 
731 28 wfjm
  subtype  c_membe_rbf_be       is integer range  1 downto 0; -- membe: be's
732
  constant c_membe_rbf_stick:   integer := 2;  -- membe: sticky flag
733
 
734 2 wfjm
-- -------------------------------------
735
 
736
component pdp11_gpr is                  -- general purpose registers
737
  port (
738
    CLK : in slbit;                     -- clock
739
    DIN : in slv16;                     -- input data
740
    ASRC : in slv3;                     -- source register number
741
    ADST : in slv3;                     -- destination register number
742
    MODE : in slv2;                     -- processor mode (k=>00,s=>01,u=>11)
743
    RSET : in slbit;                    -- register set
744
    WE : in slbit;                      -- write enable
745
    BYTOP : in slbit;                   -- byte operation (write low byte only)
746
    PCINC : in slbit;                   -- increment PC
747
    DSRC : out slv16;                   -- source register data
748
    DDST : out slv16;                   -- destination register data
749
    PC : out slv16                      -- current PC value
750
  );
751
end component;
752
 
753
constant c_gpr_r5 : slv3 := "101";      -- register number of r5
754
constant c_gpr_sp : slv3 := "110";      -- register number of SP
755
constant c_gpr_pc : slv3 := "111";      -- register number of PC
756
 
757
component pdp11_psr is                  -- processor status word register
758
  port (
759
    CLK : in slbit;                     -- clock
760 30 wfjm
    CRESET : in slbit;                  -- cpu reset
761 2 wfjm
    DIN : in slv16;                     -- input data
762
    CCIN : in slv4;                     -- cc input
763
    CCWE : in slbit;                    -- enable update cc
764
    WE : in slbit;                      -- write enable (from DIN)
765
    FUNC : in slv3;                     -- write function (from DIN)
766
    PSW : out psw_type;                 -- current psw
767
    IB_MREQ : in ib_mreq_type;          -- ibus request
768
    IB_SRES : out ib_sres_type          -- ibus response
769
  );
770
end component;
771
 
772
constant c_psr_func_wspl : slv3 := "000"; -- SPL mode: set pri
773
constant c_psr_func_wcc  : slv3 := "001"; -- CC mode: set/clear cc
774
constant c_psr_func_wint : slv3 := "010"; -- interupt mode: pmode=cmode
775
constant c_psr_func_wrti : slv3 := "011"; -- rti mode: protect modes
776
constant c_psr_func_wall : slv3 := "100"; -- write all fields
777
 
778 8 wfjm
component pdp11_ounit is                -- offset adder for addresses (ounit)
779 2 wfjm
  port (
780
    DSRC : in slv16;                    -- 'src' data for port A
781
    DDST : in slv16;                    -- 'dst' data for port A
782
    DTMP : in slv16;                    -- 'tmp' data for port A
783
    PC : in slv16;                      -- PC data for port A
784
    ASEL : in slv2;                     -- selector for port A
785
    AZERO : in slbit;                   -- force zero for port A
786
    IREG8 : in slv8;                    -- 'ireg' data for port B
787
    VMDOUT : in slv16;                  -- virt. memory data for port B
788
    CONST : in slv9;                    -- sequencer const data for port B
789
    BSEL : in slv2;                     -- selector for port B
790
    OPSUB : in slbit;                   -- operation: 0 add, 1 sub
791
    DOUT : out slv16;                   -- data output
792
    NZOUT : out slv2                    -- NZ condition codes out
793
  );
794
end component;
795
 
796 8 wfjm
constant c_ounit_asel_ddst : slv2 := "00";   -- A = DDST
797
constant c_ounit_asel_dsrc : slv2 := "01";   -- A = DSRC
798
constant c_ounit_asel_pc   : slv2 := "10";   -- A = PC  
799
constant c_ounit_asel_dtmp : slv2 := "11";   -- A = DTMP
800 2 wfjm
 
801 8 wfjm
constant c_ounit_bsel_const  : slv2 := "00"; -- B = CONST
802
constant c_ounit_bsel_vmdout : slv2 := "01"; -- B = VMDOUT
803
constant c_ounit_bsel_ireg6  : slv2 := "10"; -- B = 2*IREG(6bit)
804
constant c_ounit_bsel_ireg8  : slv2 := "11"; -- B = 2*IREG(8bit,sign-extend)
805 2 wfjm
 
806 8 wfjm
component pdp11_aunit is                -- arithmetic unit for data (aunit)
807 2 wfjm
  port (
808
    DSRC : in slv16;                    -- 'src' data in
809
    DDST : in slv16;                    -- 'dst' data in
810
    CI : in slbit;                      -- carry flag in
811
    SRCMOD : in slv2;                   -- src modifier mode
812
    DSTMOD : in slv2;                   -- dst modifier mode
813
    CIMOD : in slv2;                    -- ci modifier mode
814
    CC1OP : in slbit;                   -- use cc modes (1 op instruction)
815
    CCMODE : in slv3;                   -- cc mode
816
    BYTOP : in slbit;                   -- byte operation
817
    DOUT : out slv16;                   -- data output
818
    CCOUT : out slv4                    -- condition codes out
819
  );
820
end component;
821
 
822 8 wfjm
constant c_aunit_mod_pass : slv2 := "00"; -- pass data
823
constant c_aunit_mod_inv  : slv2 := "01"; -- invert data
824
constant c_aunit_mod_zero : slv2 := "10"; -- set to 0
825
constant c_aunit_mod_one  : slv2 := "11"; -- set to 1
826 2 wfjm
 
827 8 wfjm
-- the c_aunit_ccmode codes follow exactly the opcode format (bit 8:6)
828
constant c_aunit_ccmode_clr : slv3 := "000"; -- do clr instruction
829
constant c_aunit_ccmode_com : slv3 := "001"; -- do com instruction
830
constant c_aunit_ccmode_inc : slv3 := "010"; -- do inc instruction
831
constant c_aunit_ccmode_dec : slv3 := "011"; -- do dec instruction
832
constant c_aunit_ccmode_neg : slv3 := "100"; -- do neg instruction
833
constant c_aunit_ccmode_adc : slv3 := "101"; -- do adc instruction
834
constant c_aunit_ccmode_sbc : slv3 := "110"; -- do sbc instruction
835
constant c_aunit_ccmode_tst : slv3 := "111"; -- do tst instruction
836 2 wfjm
 
837 8 wfjm
component pdp11_lunit is                -- logic unit for data (lunit)
838 2 wfjm
  port (
839
    DSRC : in slv16;                    -- 'src' data in
840
    DDST : in slv16;                    -- 'dst' data in
841
    CCIN : in slv4;                     -- condition codes in
842
    FUNC : in slv4;                     -- function
843
    BYTOP : in slbit;                   -- byte operation
844
    DOUT : out slv16;                   -- data output
845
    CCOUT : out slv4                    -- condition codes out
846
  );
847
end component;
848
 
849 8 wfjm
constant c_lunit_func_asr  : slv4 := "0000"; -- ASR/ASRB ??? recheck coding !!
850
constant c_lunit_func_asl  : slv4 := "0001"; -- ASL/ASLB
851
constant c_lunit_func_ror  : slv4 := "0010"; -- ROR/RORB
852
constant c_lunit_func_rol  : slv4 := "0011"; -- ROL/ROLB
853
constant c_lunit_func_bis  : slv4 := "0100"; -- BIS/BISB
854
constant c_lunit_func_bic  : slv4 := "0101"; -- BIC/BICB
855
constant c_lunit_func_bit  : slv4 := "0110"; -- BIT/BITB
856
constant c_lunit_func_mov  : slv4 := "0111"; -- MOV/MOVB
857
constant c_lunit_func_sxt  : slv4 := "1000"; -- SXT
858
constant c_lunit_func_swap : slv4 := "1001"; -- SWAB
859
constant c_lunit_func_xor  : slv4 := "1010"; -- XOR
860 2 wfjm
 
861 8 wfjm
component pdp11_munit is                -- mul/div unit for data (munit)
862 2 wfjm
  port (
863
    CLK : in slbit;                     -- clock
864
    DSRC : in slv16;                    -- 'src' data in
865
    DDST : in slv16;                    -- 'dst' data in
866
    DTMP : in slv16;                    -- 'tmp' data in
867
    GPR_DSRC : in slv16;                -- 'src' data from GPR
868
    FUNC : in slv2;                     -- function
869 25 wfjm
    S_DIV : in slbit;                   -- s_opg_div state    (load dd_low)
870
    S_DIV_CN : in slbit;                -- s_opg_div_cn state (1st..16th cycle)
871
    S_DIV_CR : in slbit;                -- s_opg_div_cr state (remainder corr.)
872
    S_DIV_SR : in slbit;                -- s_opg_div_sr state (store remainder)
873 2 wfjm
    S_ASH : in slbit;                   -- s_opg_ash state
874
    S_ASH_CN : in slbit;                -- s_opg_ash_cn state
875
    S_ASHC : in slbit;                  -- s_opg_ashc state
876
    S_ASHC_CN : in slbit;               -- s_opg_ashc_cn state
877
    SHC_TC : out slbit;                 -- last shc cycle (shc==0)
878 25 wfjm
    DIV_CR : out slbit;                 -- division: remainder correction needed
879 2 wfjm
    DIV_CQ : out slbit;                 -- division: quotient correction needed
880 25 wfjm
    DIV_QUIT : out slbit;               -- division: abort (0/ or /0 or V=1)
881 2 wfjm
    DOUT : out slv16;                   -- data output
882
    DOUTE : out slv16;                  -- data output extra
883
    CCOUT : out slv4                    -- condition codes out
884
  );
885
end component;
886
 
887 8 wfjm
constant c_munit_func_mul  : slv2 := "00"; -- MUL
888
constant c_munit_func_div  : slv2 := "01"; -- DIV
889
constant c_munit_func_ash  : slv2 := "10"; -- ASH
890
constant c_munit_func_ashc : slv2 := "11"; -- ASHC
891 2 wfjm
 
892
component pdp11_mmu_sadr is             -- mmu SAR/SDR register set
893
  port (
894
    CLK : in slbit;                     -- clock
895
    MODE : in slv2;                     -- mode
896
    ASN : in slv4;                      -- augmented segment number (1+3 bit)
897
    AIB_WE : in slbit;                  -- update AIB
898
    AIB_SETA : in slbit;                -- set access AIB
899
    AIB_SETW : in slbit;                -- set write AIB
900
    SARSDR : out sarsdr_type;           -- combined SAR/SDR
901
    IB_MREQ : in ib_mreq_type;          -- ibus request
902
    IB_SRES : out ib_sres_type          -- ibus response
903
  );
904
end component;
905
 
906
component pdp11_mmu_ssr12 is            -- mmu register ssr1 and ssr2
907
  port (
908
    CLK : in slbit;                     -- clock
909 30 wfjm
    CRESET : in slbit;                  -- cpu reset
910 2 wfjm
    TRACE : in slbit;                   -- trace enable
911
    MONI : in mmu_moni_type;            -- MMU monitor port data
912
    IB_MREQ : in ib_mreq_type;          -- ibus request
913
    IB_SRES : out ib_sres_type          -- ibus response
914
  );
915
end component;
916
 
917
component pdp11_mmu is                  -- mmu - memory management unit
918
  port (
919
    CLK : in slbit;                     -- clock
920 30 wfjm
    CRESET : in slbit;                  -- cpu reset
921
    BRESET : in slbit;                  -- bus reset
922 2 wfjm
    CNTL : in mmu_cntl_type;            -- control port
923
    VADDR : in slv16;                   -- virtual address
924
    MONI : in mmu_moni_type;            -- monitor port
925
    STAT : out mmu_stat_type;           -- status port
926
    PADDRH : out slv16;                 -- physical address (upper 16 bit)
927
    IB_MREQ : in ib_mreq_type;          -- ibus request
928
    IB_SRES : out ib_sres_type          -- ibus response
929
  );
930
end component;
931
 
932
component pdp11_vmbox is                -- virtual memory
933
  port (
934
    CLK : in slbit;                     -- clock
935 30 wfjm
    GRESET : in slbit;                  -- general reset
936
    CRESET : in slbit;                  -- cpu reset
937
    BRESET : in slbit;                  -- bus reset
938 2 wfjm
    CP_ADDR : in cp_addr_type;          -- console port address
939
    VM_CNTL : in vm_cntl_type;          -- vm control port
940
    VM_ADDR : in slv16;                 -- vm address
941
    VM_DIN : in slv16;                  -- vm data in
942
    VM_STAT : out vm_stat_type;         -- vm status port
943
    VM_DOUT : out slv16;                -- vm data out
944
    EM_MREQ : out em_mreq_type;         -- external memory: request
945
    EM_SRES : in em_sres_type;          -- external memory: response
946
    MMU_MONI : in mmu_moni_type;        -- mmu monitor port
947
    IB_MREQ_M : out ib_mreq_type;       -- ibus request  (master)
948
    IB_SRES_CPU : in ib_sres_type;      -- ibus response (CPU registers)
949
    IB_SRES_EXT : in ib_sres_type;      -- ibus response (external devices)
950
    DM_STAT_VM : out dm_stat_vm_type    -- debug and monitor status
951
  );
952
end component;
953
 
954
component pdp11_dpath is                -- CPU datapath
955
  port (
956
    CLK : in slbit;                     -- clock
957 30 wfjm
    CRESET : in slbit;                  -- cpu reset
958 2 wfjm
    CNTL : in dpath_cntl_type;          -- control interface
959
    STAT : out dpath_stat_type;         -- status interface
960
    CP_DIN : in slv16;                  -- console port data in
961
    CP_DOUT : out slv16;                -- console port data out
962
    PSWOUT : out psw_type;              -- current psw
963
    PCOUT : out slv16;                  -- current pc
964
    IREG : out slv16;                   -- ireg out
965
    VM_ADDR : out slv16;                -- virt. memory address
966
    VM_DOUT : in slv16;                 -- virt. memory data out
967
    VM_DIN : out slv16;                 -- virt. memory data in
968
    IB_MREQ : in ib_mreq_type;          -- ibus request
969
    IB_SRES : out ib_sres_type;         -- ibus response
970 30 wfjm
    DM_STAT_DP : out dm_stat_dp_type    -- debug and monitor status - dpath
971 2 wfjm
  );
972
end component;
973
 
974
component pdp11_decode is             -- instruction decoder
975
  port (
976
    IREG : in slv16;                  -- input instruction word
977
    STAT : out decode_stat_type       -- status output
978
  );
979
end component;
980
 
981
component pdp11_sequencer is            -- cpu sequencer
982
  port (
983
    CLK : in slbit;                     -- clock
984 30 wfjm
    GRESET : in slbit;                  -- general reset
985 2 wfjm
    PSW : in psw_type;                  -- processor status
986
    PC : in slv16;                      -- program counter
987
    IREG : in slv16;                    -- IREG
988
    ID_STAT : in decode_stat_type;      -- instr. decoder status
989
    DP_STAT : in dpath_stat_type;       -- data path status
990
    CP_CNTL : in cp_cntl_type;          -- console port control
991
    VM_STAT : in vm_stat_type;          -- virtual memory status port
992
    INT_PRI : in slv3;                  -- interrupt priority
993
    INT_VECT : in slv9_2;               -- interrupt vector
994 30 wfjm
    INT_ACK : out slbit;                -- interrupt acknowledge
995
    CRESET : out slbit;                 -- cpu reset
996
    BRESET : out slbit;                 -- bus reset
997 2 wfjm
    MMU_MONI : out mmu_moni_type;       -- mmu monitor port
998
    DP_CNTL : out dpath_cntl_type;      -- data path control
999
    VM_CNTL : out vm_cntl_type;         -- virtual memory control port
1000
    CP_STAT : out cp_stat_type;         -- console port status
1001 30 wfjm
    ESUSP_O : out slbit;                -- external suspend output
1002
    ESUSP_I : in slbit;                 -- external suspend input
1003
    ITIMER : out slbit;                 -- instruction timer
1004 34 wfjm
    HBPT : in slbit;                    -- hardware bpt
1005 2 wfjm
    IB_MREQ : in ib_mreq_type;          -- ibus request
1006 34 wfjm
    IB_SRES : out ib_sres_type;         -- ibus response    
1007
    DM_STAT_SE : out dm_stat_se_type    -- debug and monitor status - sequencer
1008 2 wfjm
  );
1009
end component;
1010
 
1011
component pdp11_irq is                  -- interrupt requester
1012
  port (
1013
    CLK : in slbit;                     -- clock
1014 30 wfjm
    BRESET : in slbit;                  -- bus reset
1015 2 wfjm
    INT_ACK : in slbit;                 -- interrupt acknowledge from CPU
1016
    EI_PRI : in slv3;                   -- external interrupt priority
1017
    EI_VECT : in slv9_2;                -- external interrupt vector
1018
    EI_ACKM : out slbit;                -- external interrupt acknowledge
1019
    PRI : out slv3;                     -- interrupt priority
1020
    VECT : out slv9_2;                  -- interrupt vector
1021
    IB_MREQ : in ib_mreq_type;          -- ibus request
1022
    IB_SRES : out ib_sres_type          -- ibus response
1023
  );
1024
end component;
1025
 
1026
component pdp11_ubmap is                -- 11/70 unibus mapper
1027
  port (
1028
    CLK : in slbit;                     -- clock
1029
    MREQ : in slbit;                    -- request mapping
1030
    ADDR_UB : in slv18_1;               -- UNIBUS address (in)
1031
    ADDR_PM : out slv22_1;              -- physical memory address (out)
1032
    IB_MREQ : in ib_mreq_type;          -- ibus request
1033
    IB_SRES : out ib_sres_type          -- ibus response
1034
  );
1035
end component;
1036
 
1037 30 wfjm
component pdp11_reg70 is                -- 11/70 memory system registers
1038 2 wfjm
  port (
1039
    CLK : in slbit;                     -- clock
1040 30 wfjm
    CRESET : in slbit;                  -- cpu reset
1041 2 wfjm
    IB_MREQ : in ib_mreq_type;          -- ibus request
1042
    IB_SRES : out ib_sres_type          -- ibus response
1043
  );
1044
end component;
1045
 
1046
component pdp11_mem70 is                -- 11/70 memory system registers
1047
  port (
1048
    CLK : in slbit;                     -- clock
1049 30 wfjm
    CRESET : in slbit;                  -- cpu reset
1050 2 wfjm
    HM_ENA : in slbit;                  -- hit/miss enable
1051
    HM_VAL : in slbit;                  -- hit/miss value
1052
    CACHE_FMISS : out slbit;            -- cache force miss
1053
    IB_MREQ : in ib_mreq_type;          -- ibus request
1054
    IB_SRES : out ib_sres_type          -- ibus response
1055
  );
1056
end component;
1057
 
1058
component pdp11_cache is                -- cache
1059 36 wfjm
  generic (
1060
    TWIDTH : positive := 9);            -- tag width (5 to 9)
1061 2 wfjm
  port (
1062
    CLK : in slbit;                     -- clock
1063 30 wfjm
    GRESET : in slbit;                  -- general reset
1064 2 wfjm
    EM_MREQ : in em_mreq_type;          -- em request
1065
    EM_SRES : out em_sres_type;         -- em response
1066
    FMISS : in slbit;                   -- force miss
1067
    CHIT : out slbit;                   -- cache hit flag
1068
    MEM_REQ : out slbit;                -- memory: request
1069
    MEM_WE : out slbit;                 -- memory: write enable
1070
    MEM_BUSY : in slbit;                -- memory: controller busy
1071
    MEM_ACK_R : in slbit;               -- memory: acknowledge read
1072
    MEM_ADDR : out slv20;               -- memory: address
1073
    MEM_BE : out slv4;                  -- memory: byte enable
1074
    MEM_DI : out slv32;                 -- memory: data in  (memory view)
1075
    MEM_DO : in slv32                   -- memory: data out (memory view)
1076
  );
1077
end component;
1078
 
1079
component pdp11_core is                 -- full processor core
1080
  port (
1081
    CLK : in slbit;                     -- clock
1082
    RESET : in slbit;                   -- reset
1083
    CP_CNTL : in cp_cntl_type;          -- console control port
1084
    CP_ADDR : in cp_addr_type;          -- console address port
1085
    CP_DIN : in slv16;                  -- console data in
1086
    CP_STAT : out cp_stat_type;         -- console status port
1087
    CP_DOUT : out slv16;                -- console data out
1088 30 wfjm
    ESUSP_O : out slbit;                -- external suspend output
1089
    ESUSP_I : in slbit;                 -- external suspend input
1090
    ITIMER : out slbit;                 -- instruction timer
1091 34 wfjm
    HBPT : in slbit;                    -- hardware bpt
1092 2 wfjm
    EI_PRI : in slv3;                   -- external interrupt priority
1093
    EI_VECT : in slv9_2;                -- external interrupt vector
1094
    EI_ACKM : out slbit;                -- external interrupt acknowledge
1095
    EM_MREQ : out em_mreq_type;         -- external memory: request
1096
    EM_SRES : in em_sres_type;          -- external memory: response
1097 30 wfjm
    CRESET : out slbit;                 -- cpu reset
1098
    BRESET : out slbit;                 -- bus reset
1099 2 wfjm
    IB_MREQ_M : out ib_mreq_type;       -- ibus master request (master)
1100
    IB_SRES_M : in ib_sres_type;        -- ibus slave response (master)
1101 34 wfjm
    DM_STAT_SE : out dm_stat_se_type;   -- debug and monitor status - sequencer
1102 2 wfjm
    DM_STAT_DP : out dm_stat_dp_type;   -- debug and monitor status - dpath
1103
    DM_STAT_VM : out dm_stat_vm_type;   -- debug and monitor status - vmbox
1104
    DM_STAT_CO : out dm_stat_co_type    -- debug and monitor status - core
1105
  );
1106
end component;
1107
 
1108
component pdp11_tmu is                  -- trace and monitor unit
1109
  port (
1110
    CLK : in slbit;                     -- clock
1111
    ENA : in slbit := '0';              -- enable trace output
1112 30 wfjm
    DM_STAT_DP : in dm_stat_dp_type;    -- debug and monitor status - dpath
1113
    DM_STAT_VM : in dm_stat_vm_type;    -- debug and monitor status - vmbox
1114
    DM_STAT_CO : in dm_stat_co_type;    -- debug and monitor status - core
1115
    DM_STAT_SY : in dm_stat_sy_type     -- debug and monitor status - system
1116 2 wfjm
  );
1117
end component;
1118
 
1119 34 wfjm
-- this definition logically belongs into a 'for test benches' section'
1120
-- it is here for convenience to simplify instantiations.
1121
constant sbcntl_sbf_tmu  : integer := 12;
1122
 
1123 2 wfjm
component pdp11_tmu_sb is               -- trace and mon. unit; simbus wrapper
1124
  generic (
1125 34 wfjm
    ENAPIN : integer := sbcntl_sbf_tmu); -- SB_CNTL for tmu
1126 2 wfjm
   port (
1127
    CLK : in slbit;                     -- clock
1128 30 wfjm
    DM_STAT_DP : in dm_stat_dp_type;    -- debug and monitor status - dpath
1129
    DM_STAT_VM : in dm_stat_vm_type;    -- debug and monitor status - vmbox
1130
    DM_STAT_CO : in dm_stat_co_type;    -- debug and monitor status - core
1131
    DM_STAT_SY : in dm_stat_sy_type     -- debug and monitor status - system
1132 2 wfjm
  );
1133
end component;
1134
 
1135
component pdp11_du_drv is               -- display unit low level driver
1136
  generic (
1137
    CDWIDTH : positive :=  3);          -- clock divider width
1138
  port (
1139
    CLK : in slbit;                     -- clock
1140 30 wfjm
    GRESET : in slbit;                  -- general reset
1141 2 wfjm
    ROW0 : in slv22;                    -- led row 0 (22 leds, top)
1142
    ROW1 : in slv16;                    -- led row 1 (16 leds)
1143
    ROW2 : in slv16;                    -- led row 2 (16 leds)
1144
    ROW3 : in slv10;                    -- led row 3 (10 leds, bottom)
1145
    SWOPT : out slv8;                   -- option pattern from du
1146
    SWOPT_RDY : out slbit;              -- marks update of swopt
1147 8 wfjm
    DU_SCLK : out slbit;                -- DU: sclk
1148
    DU_SS_N : out slbit;                -- DU: ss_n
1149 2 wfjm
    DU_MOSI : out slbit;                -- DU: mosi (master out, slave in)
1150
    DU_MISO : in slbit                  -- DU: miso (master in, slave out)
1151
  );
1152
end component;
1153
 
1154
component pdp11_bram is                 -- BRAM based ext. memory dummy
1155
  generic (
1156
    AWIDTH : positive := 14);           -- address width
1157
  port (
1158
    CLK : in slbit;                     -- clock
1159 30 wfjm
    GRESET : in slbit;                  -- general reset
1160 2 wfjm
    EM_MREQ : in em_mreq_type;          -- em request
1161
    EM_SRES : out em_sres_type          -- em response
1162
  );
1163
end component;
1164
 
1165 29 wfjm
component pdp11_bram_memctl is          -- BRAM based memctl
1166
  generic (
1167
    MAWIDTH : positive := 4;            -- mux address width
1168 36 wfjm
    NBLOCK : positive := 11);           -- number of 16 kByte blocks
1169 29 wfjm
  port (
1170
    CLK : in slbit;                     -- clock
1171
    RESET : in slbit;                   -- reset
1172
    REQ   : in slbit;                   -- request
1173
    WE    : in slbit;                   -- write enable
1174
    BUSY : out slbit;                   -- controller busy
1175
    ACK_R : out slbit;                  -- acknowledge read
1176
    ACK_W : out slbit;                  -- acknowledge write
1177
    ACT_R : out slbit;                  -- signal active read
1178
    ACT_W : out slbit;                  -- signal active write
1179
    ADDR : in slv20;                    -- address
1180
    BE : in slv4;                       -- byte enable
1181
    DI : in slv32;                      -- data in  (memory view)
1182
    DO : out slv32                      -- data out (memory view)
1183
  );
1184
end component;
1185
 
1186
component pdp11_statleds is             -- status leds
1187
  port (
1188
    MEM_ACT_R : in slbit;               -- memory active read
1189
    MEM_ACT_W : in slbit;               -- memory active write
1190
    CP_STAT : in cp_stat_type;          -- console port status
1191 30 wfjm
    DM_STAT_DP : in dm_stat_dp_type;    -- debug and monitor status - dpath
1192 29 wfjm
    STATLEDS : out slv8                 -- 8 bit CPU status 
1193
  );
1194
end component;
1195
 
1196
component pdp11_ledmux is               -- hio led mux
1197
  generic (
1198
    LWIDTH : positive := 8);            -- led width
1199
  port (
1200
    SEL : in slbit;                     -- select (0=stat;1=dr)
1201
    STATLEDS : in slv8;                 -- 8 bit CPU status
1202 30 wfjm
    DM_STAT_DP : in dm_stat_dp_type;    -- debug and monitor status - dpath
1203 29 wfjm
    LED : out slv(LWIDTH-1 downto 0)    -- hio leds
1204
  );
1205
end component;
1206
 
1207
component pdp11_dspmux is               -- hio dsp mux
1208
  generic (
1209
    DCWIDTH : positive := 2);           -- digit counter width (2 or 3)
1210
  port (
1211
    SEL : in slv2;                      -- select
1212
    ABCLKDIV : in slv16;                -- serport clock divider
1213 30 wfjm
    DM_STAT_DP : in dm_stat_dp_type;    -- debug and monitor status - dpath
1214 29 wfjm
    DISPREG : in slv16;                 -- display register
1215
    DSP_DAT : out slv(4*(2**DCWIDTH)-1 downto 0)  -- display data
1216
  );
1217
end component;
1218
 
1219 9 wfjm
component pdp11_core_rbus is            -- core to rbus interface
1220 2 wfjm
  generic (
1221 28 wfjm
    RB_ADDR_CORE : slv16 := slv(to_unsigned(16#0000#,16));
1222
    RB_ADDR_IBUS : slv16 := slv(to_unsigned(16#4000#,16)));
1223 2 wfjm
  port (
1224
    CLK : in slbit;                     -- clock
1225
    RESET : in slbit;                   -- reset
1226
    RB_MREQ : in rb_mreq_type;          -- rbus: request
1227
    RB_SRES : out rb_sres_type;         -- rbus: response
1228 27 wfjm
    RB_STAT : out slv4;                 -- rbus: status flags
1229 8 wfjm
    RB_LAM : out slbit;                 -- remote attention
1230 30 wfjm
    GRESET : out slbit;                 -- general reset
1231 2 wfjm
    CP_CNTL : out cp_cntl_type;         -- console control port
1232
    CP_ADDR : out cp_addr_type;         -- console address port
1233
    CP_DIN : out slv16;                 -- console data in
1234
    CP_STAT : in cp_stat_type;          -- console status port
1235
    CP_DOUT : in slv16                  -- console data out
1236
  );
1237
end component;
1238
 
1239 30 wfjm
component pdp11_sys70 is                -- 11/70 system 1 core +rbus,debug,cache
1240
  port (
1241
    CLK : in slbit;                     -- clock
1242
    RESET : in slbit;                   -- reset
1243
    RB_MREQ : in rb_mreq_type;          -- rbus request  (slave)
1244
    RB_SRES : out rb_sres_type;         -- rbus response
1245
    RB_STAT : out slv4;                 -- rbus status flags
1246
    RB_LAM_CPU : out slbit;             -- rbus lam (cpu)
1247
    GRESET : out slbit;                 -- general reset (from rbus)
1248
    CRESET : out slbit;                 -- cpu reset     (from cp)
1249
    BRESET : out slbit;                 -- bus reset     (from cp or cpu)
1250
    CP_STAT : out cp_stat_type;         -- console port status
1251
    EI_PRI  : in slv3;                  -- external interrupt priority
1252
    EI_VECT : in slv9_2;                -- external interrupt vector
1253
    EI_ACKM : out slbit;                -- external interrupt acknowledge
1254
    ITIMER : out slbit;                 -- instruction timer
1255
    IB_MREQ : out ib_mreq_type;         -- ibus request  (master)
1256
    IB_SRES : in ib_sres_type;          -- ibus response (from IO system)
1257
    MEM_REQ : out slbit;                -- memory: request
1258
    MEM_WE : out slbit;                 -- memory: write enable
1259
    MEM_BUSY : in slbit;                -- memory: controller busy
1260
    MEM_ACK_R : in slbit;               -- memory: acknowledge read
1261
    MEM_ADDR : out slv20;               -- memory: address
1262
    MEM_BE : out slv4;                  -- memory: byte enable
1263
    MEM_DI : out slv32;                 -- memory: data in  (memory view)
1264
    MEM_DO : in slv32;                  -- memory: data out (memory view)
1265
    DM_STAT_DP : out dm_stat_dp_type    -- debug and monitor status - dpath
1266
  );
1267
end component;
1268
 
1269
component pdp11_hio70 is                -- hio led and dsp for sys70
1270
  generic (
1271
    LWIDTH : positive := 8;             -- led width
1272
    DCWIDTH : positive := 2);           -- digit counter width (2 or 3)
1273
  port (
1274
    SEL_LED : in slbit;                 -- led select (0=stat;1=dr)
1275
    SEL_DSP : in slv2;                  -- dsp select
1276
    MEM_ACT_R : in slbit;               -- memory active read
1277
    MEM_ACT_W : in slbit;               -- memory active write
1278
    CP_STAT : in cp_stat_type;          -- console port status
1279
    DM_STAT_DP : in dm_stat_dp_type;    -- debug and monitor status
1280
    ABCLKDIV : in slv16;                -- serport clock divider
1281
    DISPREG : in slv16;                 -- display register
1282
    LED : out slv(LWIDTH-1 downto 0);   -- hio leds
1283
    DSP_DAT : out slv(4*(2**DCWIDTH)-1 downto 0)  -- display data
1284
  );
1285
end component;
1286
 
1287 34 wfjm
component pdp11_dmscnt is               -- debug&moni: state counter
1288
  generic (
1289
    RB_ADDR : slv16 := slv(to_unsigned(16#0040#,16)));
1290
  port (
1291
    CLK : in slbit;                     -- clock
1292
    RESET : in slbit;                   -- reset
1293
    RB_MREQ : in rb_mreq_type;          -- rbus: request
1294
    RB_SRES : out rb_sres_type;         -- rbus: response
1295
    DM_STAT_SE : in dm_stat_se_type;    -- debug and monitor status - sequencer
1296
    DM_STAT_DP : in dm_stat_dp_type;    -- debug and monitor status - data path
1297
    DM_STAT_CO : in dm_stat_co_type     -- debug and monitor status - core
1298
  );
1299
end component;
1300
 
1301
component pdp11_dmcmon is               -- debug&moni: cpu monitor
1302
  generic (
1303
    RB_ADDR : slv16 := slv(to_unsigned(16#0048#,16));
1304
    AWIDTH : natural := 8);
1305
  port (
1306
    CLK : in slbit;                     -- clock
1307
    RESET : in slbit;                   -- reset
1308
    RB_MREQ : in rb_mreq_type;          -- rbus: request
1309
    RB_SRES : out rb_sres_type;         -- rbus: response
1310
    DM_STAT_SE : in dm_stat_se_type;    -- debug and monitor status - sequencer
1311
    DM_STAT_DP : in dm_stat_dp_type;    -- debug and monitor status - data path
1312
    DM_STAT_VM : in dm_stat_vm_type;    -- debug and monitor status - vmbox
1313
    DM_STAT_CO : in dm_stat_co_type     -- debug and monitor status - core
1314
  );
1315
end component;
1316
 
1317
component pdp11_dmhbpt is               -- debug&moni: hardware breakpoint
1318
  generic (
1319
    RB_ADDR : slv16 := slv(to_unsigned(16#0050#,16));
1320
    NUNIT : natural := 2);
1321
  port (
1322
    CLK : in slbit;                     -- clock
1323
    RESET : in slbit;                   -- reset
1324
    RB_MREQ : in rb_mreq_type;          -- rbus: request
1325
    RB_SRES : out rb_sres_type;         -- rbus: response
1326
    DM_STAT_SE : in dm_stat_se_type;    -- debug and monitor status - sequencer
1327
    DM_STAT_DP : in dm_stat_dp_type;    -- debug and monitor status - data path
1328
    DM_STAT_VM : in dm_stat_vm_type;    -- debug and monitor status - vmbox
1329
    DM_STAT_CO : in dm_stat_co_type;    -- debug and monitor status - core
1330
    HBPT : out slbit                    -- hw break flag
1331
  );
1332
end component;
1333
 
1334
component pdp11_dmhbpt_unit is          -- dmhbpt - indivitial unit
1335
  generic (
1336
    RB_ADDR : slv16 := slv(to_unsigned(16#0050#,16));
1337
    INDEX : natural := 0);
1338
  port (
1339
    CLK : in slbit;                     -- clock
1340
    RESET : in slbit;                   -- reset
1341
    RB_MREQ : in rb_mreq_type;          -- rbus: request
1342
    RB_SRES : out rb_sres_type;         -- rbus: response
1343
    DM_STAT_SE : in dm_stat_se_type;    -- debug and monitor status - sequencer
1344
    DM_STAT_DP : in dm_stat_dp_type;    -- debug and monitor status - data path
1345
    DM_STAT_VM : in dm_stat_vm_type;    -- debug and monitor status - vmbox
1346
    DM_STAT_CO : in dm_stat_co_type;    -- debug and monitor status - core
1347
    HBPT : out slbit                    -- hw break flag
1348
  );
1349
end component;
1350
 
1351 2 wfjm
-- ----- move later to pdp11_conf --------------------------------------------
1352
 
1353
constant conf_vect_pirq : integer := 8#240#;
1354
constant conf_pri_pirq_1 : integer := 1;
1355
constant conf_pri_pirq_2 : integer := 2;
1356
constant conf_pri_pirq_3 : integer := 3;
1357
constant conf_pri_pirq_4 : integer := 4;
1358
constant conf_pri_pirq_5 : integer := 5;
1359
constant conf_pri_pirq_6 : integer := 6;
1360
constant conf_pri_pirq_7 : integer := 7;
1361
 
1362
end package pdp11;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.