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-- $Id: pdp11_cache.vhd 784 2016-07-09 22:17:01Z mueller $
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--
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-- Copyright 2008-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: pdp11_cache - syn
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-- Description: pdp11: cache
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--
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-- Dependencies: memlib/ram_2swsr_rfirst_gen
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-- Test bench: -
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-- Target Devices: generic
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-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.1; ghdl 0.18-0.33
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--
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-- Synthesis results
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-- clw = cache line width (tag+data)
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-- eff = efficiency (fraction of used BRAM colums)
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-- - 2016-03-22 (r750) with viv 2015.4 for xc7a100t-1
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-- TWIDTH flop lutl lutm RAMB36 RAMB18 bram clw eff
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-- 9 43 106 0 0 5 2.5 45 100%
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-- 8 43 109 0 5 0 5.0 44 97%
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-- 7 43 107 0 10 4 12.0 43 89%
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-- 6 43 106 0 19 4 21.0 42 100%
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-- 5 58! 106 0 41 0 41.0 41 100%
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2016-05-22 767 1.1.1 don't init N_REGS (vivado fix for fsm inference)
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-- 2016-03-22 751 1.1 now configurable size (8,16,32,64,128 kB)
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-- 2011-11-18 427 1.0.3 now numeric_std clean
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-- 2008-02-23 118 1.0.2 ce cache in s_idle to avoid U's in sim
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-- factor invariants out of if's; fix tag rmiss logic
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-- 2008-02-17 117 1.0.1 use em_(mreq|sres) interface; use req,we for mem
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-- recode, ghdl doesn't like partial vector port maps
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-- 2008-02-16 116 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.memlib.all;
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use work.pdp11.all;
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entity pdp11_cache is -- cache
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generic (
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TWIDTH : positive := 9); -- tag width (5 to 9)
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port (
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CLK : in slbit; -- clock
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GRESET : in slbit; -- general reset
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EM_MREQ : in em_mreq_type; -- em request
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EM_SRES : out em_sres_type; -- em response
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FMISS : in slbit; -- force miss
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CHIT : out slbit; -- cache hit flag
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MEM_REQ : out slbit; -- memory: request
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MEM_WE : out slbit; -- memory: write enable
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MEM_BUSY : in slbit; -- memory: controller busy
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MEM_ACK_R : in slbit; -- memory: acknowledge read
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MEM_ADDR : out slv20; -- memory: address
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MEM_BE : out slv4; -- memory: byte enable
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MEM_DI : out slv32; -- memory: data in (memory view)
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MEM_DO : in slv32 -- memory: data out (memory view)
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);
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end pdp11_cache;
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architecture syn of pdp11_cache is
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constant lwidth: positive := 22-2-TWIDTH; -- line address width
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subtype t_range is integer range TWIDTH-1 downto 0; -- tag value regs
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subtype l_range is integer range lwidth-1 downto 0; -- line addr regs
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subtype af_tag is integer range 22-1 downto 22-TWIDTH; -- tag address
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subtype af_line is integer range 22-TWIDTH-1 downto 2; -- line address
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subtype df_byte3 is integer range 31 downto 24;
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subtype df_byte2 is integer range 23 downto 16;
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subtype df_byte1 is integer range 15 downto 8;
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subtype df_byte0 is integer range 7 downto 0;
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subtype df_word1 is integer range 31 downto 16;
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subtype df_word0 is integer range 15 downto 0;
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type state_type is (
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s_idle, -- s_idle: wait for req
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s_read, -- s_read: read cycle
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s_rmiss, -- s_rmiss: read miss
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s_write -- s_write: write cycle
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);
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type regs_type is record
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state : state_type; -- state
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addr_w : slbit; -- address - word select
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addr_l : slv(l_range); -- address - cache line address
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addr_t : slv(t_range); -- address - cache tag part
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be : slv4; -- byte enables (at 4 byte level)
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di : slv16; -- data
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end record regs_type;
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constant regs_init : regs_type := (
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s_idle, -- state
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'0', -- addr_w
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slv(to_unsigned(0,lwidth)), -- addr_l
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slv(to_unsigned(0,TWIDTH)), -- addr_t
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(others=>'0'), -- be
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(others=>'0') -- di
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);
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signal R_REGS : regs_type := regs_init;
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signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
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signal CMEM_TAG_CEA : slbit := '0';
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signal CMEM_TAG_CEB : slbit := '0';
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signal CMEM_TAG_WEA : slbit := '0';
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signal CMEM_TAG_WEB : slbit := '0';
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signal CMEM_TAG_DIB : slv(t_range) := (others=>'0');
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signal CMEM_TAG_DOA : slv(t_range) := (others=>'0');
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signal CMEM_DAT_CEA : slbit := '0';
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signal CMEM_DAT_CEB : slbit := '0';
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signal CMEM_DAT_WEA : slv4 := "0000";
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signal CMEM_DAT_WEB : slv4 := "0000";
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signal CMEM_DIA_0 : slv9 := (others=>'0');
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signal CMEM_DIA_1 : slv9 := (others=>'0');
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signal CMEM_DIA_2 : slv9 := (others=>'0');
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signal CMEM_DIA_3 : slv9 := (others=>'0');
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signal CMEM_DIB_0 : slv9 := (others=>'0');
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signal CMEM_DIB_1 : slv9 := (others=>'0');
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signal CMEM_DIB_2 : slv9 := (others=>'0');
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signal CMEM_DIB_3 : slv9 := (others=>'0');
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signal CMEM_DOA_0 : slv9 := (others=>'0');
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signal CMEM_DOA_1 : slv9 := (others=>'0');
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signal CMEM_DOA_2 : slv9 := (others=>'0');
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signal CMEM_DOA_3 : slv9 := (others=>'0');
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begin
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assert TWIDTH>=5 and TWIDTH<=9
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report "assert(TWIDTH>=5 and TWIDTH<=9): unsupported TWIDTH"
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severity failure;
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2 |
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CMEM_TAG : ram_2swsr_rfirst_gen
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generic map (
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AWIDTH => lwidth,
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DWIDTH => twidth)
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port map (
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CLKA => CLK,
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CLKB => CLK,
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ENA => CMEM_TAG_CEA,
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ENB => CMEM_TAG_CEB,
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WEA => CMEM_TAG_WEA,
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WEB => CMEM_TAG_WEB,
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ADDRA => EM_MREQ.addr(af_line),
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ADDRB => R_REGS.addr_l,
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DIA => EM_MREQ.addr(af_tag),
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DIB => CMEM_TAG_DIB,
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DOA => CMEM_TAG_DOA,
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DOB => open
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);
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CMEM_DAT0 : ram_2swsr_rfirst_gen
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generic map (
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AWIDTH => lwidth,
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DWIDTH => 9)
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port map (
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CLKA => CLK,
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CLKB => CLK,
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ENA => CMEM_DAT_CEA,
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ENB => CMEM_DAT_CEB,
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WEA => CMEM_DAT_WEA(0),
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WEB => CMEM_DAT_WEB(0),
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ADDRA => EM_MREQ.addr(af_line),
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ADDRB => R_REGS.addr_l,
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DIA => CMEM_DIA_0,
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DIB => CMEM_DIB_0,
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DOA => CMEM_DOA_0,
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DOB => open
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);
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CMEM_DAT1 : ram_2swsr_rfirst_gen
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generic map (
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AWIDTH => lwidth,
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DWIDTH => 9)
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port map (
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CLKA => CLK,
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CLKB => CLK,
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ENA => CMEM_DAT_CEA,
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ENB => CMEM_DAT_CEB,
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WEA => CMEM_DAT_WEA(1),
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WEB => CMEM_DAT_WEB(1),
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ADDRA => EM_MREQ.addr(af_line),
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ADDRB => R_REGS.addr_l,
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DIA => CMEM_DIA_1,
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DIB => CMEM_DIB_1,
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DOA => CMEM_DOA_1,
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DOB => open
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);
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CMEM_DAT2 : ram_2swsr_rfirst_gen
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generic map (
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AWIDTH => lwidth,
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DWIDTH => 9)
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port map (
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CLKA => CLK,
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CLKB => CLK,
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ENA => CMEM_DAT_CEA,
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ENB => CMEM_DAT_CEB,
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WEA => CMEM_DAT_WEA(2),
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WEB => CMEM_DAT_WEB(2),
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ADDRA => EM_MREQ.addr(af_line),
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ADDRB => R_REGS.addr_l,
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DIA => CMEM_DIA_2,
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DIB => CMEM_DIB_2,
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DOA => CMEM_DOA_2,
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DOB => open
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);
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CMEM_DAT3 : ram_2swsr_rfirst_gen
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generic map (
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AWIDTH => lwidth,
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DWIDTH => 9)
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port map (
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CLKA => CLK,
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CLKB => CLK,
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ENA => CMEM_DAT_CEA,
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ENB => CMEM_DAT_CEB,
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WEA => CMEM_DAT_WEA(3),
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WEB => CMEM_DAT_WEB(3),
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ADDRA => EM_MREQ.addr(af_line),
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wfjm |
ADDRB => R_REGS.addr_l,
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DIA => CMEM_DIA_3,
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DIB => CMEM_DIB_3,
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DOA => CMEM_DOA_3,
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DOB => open
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);
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proc_regs: process (CLK)
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begin
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if rising_edge(CLK) then
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if GRESET = '1' then
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R_REGS <= regs_init;
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else
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R_REGS <= N_REGS;
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end if;
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end if;
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end process proc_regs;
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259 |
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proc_next: process (R_REGS, EM_MREQ, FMISS,
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CMEM_TAG_DOA,
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CMEM_DOA_0, CMEM_DOA_1, CMEM_DOA_2, CMEM_DOA_3,
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MEM_BUSY, MEM_ACK_R, MEM_DO)
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263 |
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264 |
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variable r : regs_type := regs_init;
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variable n : regs_type := regs_init;
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266 |
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267 |
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variable iaddr_w : slbit := '0';
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268 |
36 |
wfjm |
variable iaddr_l : slv(l_range) := (others=>'0');
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variable iaddr_t : slv(t_range) := (others=>'0');
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2 |
wfjm |
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variable itagok : slbit := '0';
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272 |
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variable ivalok : slbit := '0';
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273 |
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274 |
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variable icmem_tag_cea : slbit := '0';
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275 |
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variable icmem_tag_ceb : slbit := '0';
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276 |
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variable icmem_tag_wea : slbit := '0';
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277 |
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variable icmem_tag_web : slbit := '0';
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278 |
36 |
wfjm |
variable icmem_tag_dib : slv(t_range) := (others=>'0');
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279 |
2 |
wfjm |
variable icmem_dat_cea : slbit := '0';
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280 |
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variable icmem_dat_ceb : slbit := '0';
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281 |
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variable icmem_dat_wea : slv4 := "0000";
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282 |
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variable icmem_dat_web : slv4 := "0000";
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283 |
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variable icmem_val_doa : slv4 := "0000";
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284 |
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variable icmem_dat_doa : slv32 := (others=>'0');
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285 |
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variable icmem_val_dib : slv4 := "0000";
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286 |
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variable icmem_dat_dib : slv32 := (others=>'0');
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287 |
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288 |
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variable iackr : slbit := '0';
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289 |
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variable iackw : slbit := '0';
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290 |
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variable ichit : slbit := '0';
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291 |
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variable iosel : slv2 := "11";
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292 |
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293 |
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variable imem_reqr : slbit := '0';
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294 |
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variable imem_reqw : slbit := '0';
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295 |
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variable imem_be : slv4 := "0000";
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296 |
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|
297 |
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begin
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298 |
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|
299 |
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r := R_REGS;
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300 |
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n := R_REGS;
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301 |
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|
302 |
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iaddr_w := EM_MREQ.addr(1); -- get word select
|
303 |
36 |
wfjm |
iaddr_l := EM_MREQ.addr(af_line); -- get cache line addr
|
304 |
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iaddr_t := EM_MREQ.addr(af_tag); -- get cache tag part
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305 |
2 |
wfjm |
|
306 |
|
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icmem_tag_cea := '0';
|
307 |
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icmem_tag_ceb := '0';
|
308 |
|
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icmem_tag_wea := '0';
|
309 |
|
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icmem_tag_web := '0';
|
310 |
|
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icmem_tag_dib := r.addr_t; -- default, local define whenver used
|
311 |
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icmem_dat_cea := '0';
|
312 |
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icmem_dat_ceb := '0';
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313 |
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icmem_dat_wea := "0000";
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314 |
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icmem_dat_web := "0000";
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315 |
|
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icmem_val_dib := "0000";
|
316 |
|
|
icmem_dat_dib := MEM_DO; -- default, local define whenver used
|
317 |
|
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|
318 |
36 |
wfjm |
icmem_val_doa(0) := CMEM_DOA_0(8);
|
319 |
|
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icmem_dat_doa(df_byte0) := CMEM_DOA_0(df_byte0);
|
320 |
|
|
icmem_val_doa(1) := CMEM_DOA_1(8);
|
321 |
|
|
icmem_dat_doa(df_byte1) := CMEM_DOA_1(df_byte0);
|
322 |
|
|
icmem_val_doa(2) := CMEM_DOA_2(8);
|
323 |
|
|
icmem_dat_doa(df_byte2) := CMEM_DOA_2(df_byte0);
|
324 |
|
|
icmem_val_doa(3) := CMEM_DOA_3(8);
|
325 |
|
|
icmem_dat_doa(df_byte3) := CMEM_DOA_3(df_byte0);
|
326 |
2 |
wfjm |
|
327 |
|
|
itagok := '0';
|
328 |
|
|
if CMEM_TAG_DOA = r.addr_t then -- cache tag hit
|
329 |
|
|
itagok := '1';
|
330 |
|
|
end if;
|
331 |
|
|
ivalok := '0';
|
332 |
|
|
if (icmem_val_doa and r.be) = r.be then
|
333 |
|
|
ivalok := '1';
|
334 |
|
|
end if;
|
335 |
|
|
|
336 |
|
|
iackr := '0';
|
337 |
|
|
iackw := '0';
|
338 |
|
|
ichit := '0';
|
339 |
|
|
iosel := "11"; -- default to ext. mem data
|
340 |
|
|
-- this prevents U's from cache bram's
|
341 |
|
|
-- to propagate to dout in beginning...
|
342 |
|
|
|
343 |
|
|
imem_reqr := '0';
|
344 |
|
|
imem_reqw := '0';
|
345 |
|
|
imem_be := r.be;
|
346 |
|
|
|
347 |
|
|
case r.state is
|
348 |
|
|
when s_idle => -- s_idle: wait for req
|
349 |
|
|
n.addr_w := iaddr_w; -- capture address: word select
|
350 |
|
|
n.addr_l := iaddr_l; -- capture address: cache line addr
|
351 |
|
|
n.addr_t := iaddr_t; -- capture address: cache tag part
|
352 |
|
|
n.be := "0000";
|
353 |
|
|
icmem_tag_cea := '1'; -- access cache tag port A
|
354 |
|
|
icmem_dat_cea := '1'; -- access cache data port A
|
355 |
|
|
if iaddr_w = '0' then -- capture byte enables at 4 byte lvl
|
356 |
|
|
n.be(1 downto 0) := EM_MREQ.be;
|
357 |
|
|
else
|
358 |
|
|
n.be(3 downto 2) := EM_MREQ.be;
|
359 |
|
|
end if;
|
360 |
|
|
n.di := EM_MREQ.din; -- capture data
|
361 |
|
|
|
362 |
|
|
if EM_MREQ.req = '1' then -- if access requested
|
363 |
|
|
if EM_MREQ.we = '0' then -- if READ requested
|
364 |
|
|
n.state := s_read; -- next: read
|
365 |
|
|
|
366 |
|
|
else -- if WRITE requested
|
367 |
|
|
icmem_tag_wea := '1'; -- write tag
|
368 |
|
|
icmem_dat_wea := n.be; -- write cache data
|
369 |
|
|
n.state := s_write; -- next: write
|
370 |
|
|
end if;
|
371 |
|
|
end if;
|
372 |
|
|
|
373 |
|
|
when s_read => -- s_read: read cycle
|
374 |
|
|
iosel := '0' & r.addr_w; -- output select: cache
|
375 |
|
|
imem_be := "1111"; -- mem read: all 4 bytes
|
376 |
|
|
if EM_MREQ.cancel = '0' then
|
377 |
|
|
if FMISS='0' and itagok='1' and ivalok='1' then -- read tag&val hit
|
378 |
|
|
iackr := '1'; -- signal read acknowledge
|
379 |
|
|
ichit := '1'; -- signal cache hit
|
380 |
|
|
n.state := s_idle; -- next: back to idle
|
381 |
|
|
else -- read miss
|
382 |
|
|
if MEM_BUSY = '0' then -- if mem not busy
|
383 |
|
|
imem_reqr :='1'; -- request mem read
|
384 |
|
|
n.state := s_rmiss; -- next: rmiss, wait for mem data
|
385 |
|
|
end if;
|
386 |
|
|
end if;
|
387 |
|
|
else
|
388 |
|
|
n.state := s_idle; -- next: back to idle
|
389 |
|
|
end if;
|
390 |
|
|
|
391 |
|
|
when s_rmiss => -- s_rmiss: read cycle
|
392 |
|
|
iosel := '1' & r.addr_w; -- output select: memory
|
393 |
|
|
icmem_tag_web := '1'; -- cache update: write tag
|
394 |
|
|
icmem_tag_dib := r.addr_t; -- cache update: new tag
|
395 |
|
|
icmem_val_dib := "1111"; -- cache update: all valid
|
396 |
|
|
icmem_dat_dib := MEM_DO; -- cache update: data from mem
|
397 |
|
|
icmem_dat_web := "1111"; -- cache update: write all 4 bytes
|
398 |
|
|
if MEM_ACK_R = '1' then -- mem data valid
|
399 |
|
|
iackr := '1'; -- signal read acknowledge
|
400 |
|
|
icmem_tag_ceb := '1'; -- access cache tag port B
|
401 |
|
|
icmem_dat_ceb := '1'; -- access cache data port B
|
402 |
|
|
n.state := s_idle; -- next: back to idle
|
403 |
|
|
end if;
|
404 |
|
|
|
405 |
|
|
when s_write => -- s_write: write cycle
|
406 |
|
|
icmem_tag_dib := CMEM_TAG_DOA; -- cache restore: last state
|
407 |
|
|
icmem_dat_dib := icmem_dat_doa; -- cache restore: last state
|
408 |
|
|
if EM_MREQ.cancel = '0' then -- request ok
|
409 |
|
|
if MEM_BUSY = '0' then -- if mem not busy
|
410 |
|
|
if itagok = '0' then -- if write tag miss
|
411 |
|
|
icmem_dat_ceb := '1'; -- access cache (invalidate)
|
412 |
|
|
icmem_dat_web := not r.be; -- write missed bytes
|
413 |
|
|
icmem_val_dib := "0000"; -- invalidate missed bytes
|
414 |
|
|
end if;
|
415 |
|
|
imem_reqw := '1'; -- write back to main memory
|
416 |
|
|
iackw := '1'; -- and done
|
417 |
|
|
n.state := s_idle; -- next: back to idle
|
418 |
|
|
end if;
|
419 |
|
|
|
420 |
|
|
else -- request canceled -> restore
|
421 |
|
|
icmem_tag_ceb := '1'; -- access cache line
|
422 |
|
|
icmem_tag_web := '1'; -- write tag
|
423 |
|
|
icmem_dat_ceb := '1'; -- access cache line
|
424 |
|
|
icmem_dat_web := "1111"; -- restore cache line
|
425 |
|
|
icmem_val_dib := icmem_val_doa; -- cache restore: last state
|
426 |
|
|
n.state := s_idle; -- next: back to idle
|
427 |
|
|
end if;
|
428 |
|
|
|
429 |
|
|
when others => null;
|
430 |
|
|
end case;
|
431 |
|
|
|
432 |
|
|
N_REGS <= n;
|
433 |
|
|
|
434 |
|
|
CMEM_TAG_CEA <= icmem_tag_cea;
|
435 |
|
|
CMEM_TAG_CEB <= icmem_tag_ceb;
|
436 |
|
|
CMEM_TAG_WEA <= icmem_tag_wea;
|
437 |
|
|
CMEM_TAG_WEB <= icmem_tag_web;
|
438 |
|
|
CMEM_TAG_DIB <= icmem_tag_dib;
|
439 |
|
|
CMEM_DAT_CEA <= icmem_dat_cea;
|
440 |
|
|
CMEM_DAT_CEB <= icmem_dat_ceb;
|
441 |
|
|
CMEM_DAT_WEA <= icmem_dat_wea;
|
442 |
|
|
CMEM_DAT_WEB <= icmem_dat_web;
|
443 |
|
|
|
444 |
36 |
wfjm |
CMEM_DIA_0(8) <= '1';
|
445 |
|
|
CMEM_DIA_0(df_byte0) <= EM_MREQ.din(df_byte0);
|
446 |
|
|
CMEM_DIA_1(8) <= '1';
|
447 |
|
|
CMEM_DIA_1(df_byte0) <= EM_MREQ.din(df_byte1);
|
448 |
|
|
CMEM_DIA_2(8) <= '1';
|
449 |
|
|
CMEM_DIA_2(df_byte0) <= EM_MREQ.din(df_byte0);
|
450 |
|
|
CMEM_DIA_3(8) <= '1';
|
451 |
|
|
CMEM_DIA_3(df_byte0) <= EM_MREQ.din(df_byte1);
|
452 |
2 |
wfjm |
|
453 |
36 |
wfjm |
CMEM_DIB_0(8) <= icmem_val_dib(0);
|
454 |
|
|
CMEM_DIB_0(df_byte0) <= icmem_dat_dib(df_byte0);
|
455 |
|
|
CMEM_DIB_1(8) <= icmem_val_dib(1);
|
456 |
|
|
CMEM_DIB_1(df_byte0) <= icmem_dat_dib(df_byte1);
|
457 |
|
|
CMEM_DIB_2(8) <= icmem_val_dib(2);
|
458 |
|
|
CMEM_DIB_2(df_byte0) <= icmem_dat_dib(df_byte2);
|
459 |
|
|
CMEM_DIB_3(8) <= icmem_val_dib(3);
|
460 |
|
|
CMEM_DIB_3(df_byte0) <= icmem_dat_dib(df_byte3);
|
461 |
2 |
wfjm |
|
462 |
|
|
EM_SRES <= em_sres_init;
|
463 |
|
|
EM_SRES.ack_r <= iackr;
|
464 |
|
|
EM_SRES.ack_w <= iackw;
|
465 |
|
|
case iosel is
|
466 |
36 |
wfjm |
when "00" => EM_SRES.dout <= icmem_dat_doa(df_word0);
|
467 |
|
|
when "01" => EM_SRES.dout <= icmem_dat_doa(df_word1);
|
468 |
|
|
when "10" => EM_SRES.dout <= MEM_DO(df_word0);
|
469 |
|
|
when "11" => EM_SRES.dout <= MEM_DO(df_word1);
|
470 |
2 |
wfjm |
when others => null;
|
471 |
|
|
end case;
|
472 |
|
|
|
473 |
|
|
CHIT <= ichit;
|
474 |
|
|
|
475 |
|
|
MEM_REQ <= imem_reqr or imem_reqw;
|
476 |
|
|
MEM_WE <= imem_reqw;
|
477 |
|
|
MEM_ADDR <= r.addr_t & r.addr_l;
|
478 |
|
|
MEM_BE <= imem_be;
|
479 |
|
|
MEM_DI <= r.di & r.di;
|
480 |
|
|
|
481 |
|
|
end process proc_next;
|
482 |
|
|
|
483 |
|
|
end syn;
|