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-- $Id: pdp11_core_rri.vhd 314 2010-07-09 17:38:41Z mueller $
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--
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-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: pdp11_core_rri - syn
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-- Description: pdp11: core to rri register port interface
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--
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-- Dependencies: -
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-- Test bench: tb/tb_rritba_pdp11core
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-- tb/tb_rripdp_pdp11core
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-- tb/tb_rriext_pdp11core
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--
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-- Target Devices: generic
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
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-- Revision History: -
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-- Date Rev Version Comment
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-- 2010-06-20 308 1.2.2 use c_ibrb_ibf_ def's
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-- 2010-06-18 306 1.2.1 rename RB_ADDR->RB_ADDR_CORE, add RB_ADDR_IBUS;
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-- add ibrb register and ibr window logic
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-- 2010-06-13 305 1.2 add CP_ADDR in port; mostly rewritten for new
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-- rri <-> cp mapping
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-- 2010-06-03 299 1.1.2 correct rbus init logic (use we, din, RB_ADDR)
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-- 2010-05-02 287 1.1.1 rename RP_STAT->RB_STAT; remove unneeded unsigned()
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-- 2010-05-01 285 1.1 port to rri V2 interface, add RB_ADDR generic;
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-- rename c_rp_addr_* -> c_rb_addr_*
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-- 2008-05-03 143 1.0.8 rename _cpursta->_cpurust
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-- 2008-04-27 140 1.0.7 use cpursta interface, remove cpufail
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-- 2008-03-02 121 1.0.6 set RP_ERR when cmderr or cmdmerr status seen
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-- 2008-02-24 119 1.0.5 support lah,rps,wps cp commands
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-- 2008-01-20 113 1.0.4 use single LAM; change to RRI_LAM interface
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-- 2007-10-12 88 1.0.3 avoid ieee.std_logic_unsigned, use cast to unsigned
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-- 2007-08-16 74 1.0.2 add AP_LAM interface to pdp11_core_rri
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-- 2007-08-12 73 1.0.1 use def's; add stat command; wait for step complete
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-- 2007-07-08 65 1.0 Initial version
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------------------------------------------------------------------------------
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--
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-- rbus registers:
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--
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-- Address Bits Name r/w/i Function
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--
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-- bbb00000 conf r/w/- cpu configuration (e.g. cpu type)
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-- (currently unused, all bits MBZ)
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-- bbb00001 cntl -/f/- cpu control
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-- 3:0 func function code
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-- 0000: noop
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-- 0001: start
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-- 0010: stop
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-- 0011: continue
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-- 0100: step
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-- 1111: reset (soft)
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-- bbb00010 stat r/-/- cpu status
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-- 7:04 cpurust r/-/- cp_stat: cpurust
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-- 3 cpuhalt r/-/- cp_stat: cpuhalt
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-- 2 cpugo r/-/- cp_stat: cpugo
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-- 1 cmdmerr r/-/- cp_stat: cmdmerr
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-- 0 cmderr r/-/- cp_stat: cmderr
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-- bbb00011 psw r/w/- processor status word access
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-- bbb00100 al r/w/- address register, low
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-- bbb00101 ah r/w/- address register, high
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-- bbb00110 mem r/w/- memory access
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-- bbb00111 memi r/w/- memory access, inc address
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-- bbb01rrr gpr[] r/w/- general purpose regs
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-- bbb10000 ibrb r/w/- ibr base address
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-- 12:06 base r/w/- ibr window base address
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-- 1:00 we r/w/- byte enables (00 equivalent to 11)
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-- www----- ibr[] r/w/- ibr window (32 words)
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use work.slvtypes.all;
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use work.rrilib.all;
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use work.pdp11.all;
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-- ----------------------------------------------------------------------------
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entity pdp11_core_rri is -- core to rri reg port interface
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generic (
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RB_ADDR_CORE : slv8 := conv_std_logic_vector(2#00000000#,8);
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RB_ADDR_IBUS : slv8 := conv_std_logic_vector(2#10000000#,8));
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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RB_MREQ : in rb_mreq_type; -- rbus: request
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RB_SRES : out rb_sres_type; -- rbus: response
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RB_STAT : out slv3; -- rbus: status flags
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RRI_LAM : out slbit; -- remote attention
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CPU_RESET : out slbit; -- cpu master reset
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CP_CNTL : out cp_cntl_type; -- console control port
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CP_ADDR : out cp_addr_type; -- console address port
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CP_DIN : out slv16; -- console data in
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CP_STAT : in cp_stat_type; -- console status port
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CP_DOUT : in slv16 -- console data out
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);
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end pdp11_core_rri;
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architecture syn of pdp11_core_rri is
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type state_type is (
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s_idle, -- s_idle: wait for rp access
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s_cpwait, -- s_cpwait: wait for cp port ack
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s_cpstep -- s_cpstep: wait for cpustep done
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);
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type regs_type is record
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state : state_type; -- state
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cpreq : slbit; -- cp request flag
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cpfunc : slv5; -- cp function
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cpugo_1 : slbit; -- prev cycle cpugo
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addr : slv22_1; -- address register
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ena_22bit : slbit; -- 22bit enable
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ena_ubmap : slbit; -- ubmap enable
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ibrbase : slv(c_ibrb_ibf_base); -- ibr base address
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ibrbe : slv2; -- ibr byte enables
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ibrberet : slv2; -- ibr byte enables (for readback)
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doinc : slbit; -- at cmdack: do addr reg inc
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waitstep : slbit; -- at cmdack: wait for cpu step complete
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end record regs_type;
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constant regs_init : regs_type := (
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s_idle, -- state
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'0', -- cpreq
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(others=>'0'), -- cpfunc
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'0', -- cpugo_1
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(others=>'0'), -- addr
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'0','0', -- ena_22bit, ena_ubmap
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(others=>'0'),"00","00", -- ibrbase, ibrbe, ibrberet
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'0','0' -- doinc, waitstep
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);
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signal R_REGS : regs_type := regs_init; -- state registers
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signal N_REGS : regs_type := regs_init; -- next value state regs
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begin
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proc_regs: process (CLK)
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begin
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if CLK'event and CLK='1' then
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if RESET = '1' then
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R_REGS <= regs_init;
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else
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R_REGS <= N_REGS;
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end if;
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end if;
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end process proc_regs;
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proc_next: process (R_REGS, RB_MREQ, CP_STAT, CP_DOUT)
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variable r : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable irb_selc : slbit := '0';
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variable irb_seli : slbit := '0';
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variable irb_ack : slbit := '0';
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variable irb_busy : slbit := '0';
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variable irb_err : slbit := '0';
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variable irb_dout : slv16 := (others=>'0');
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variable irb_lam : slbit := '0';
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variable icpreq : slbit := '0';
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variable icpureset : slbit := '0';
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variable icpaddr : cp_addr_type := cp_addr_init;
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begin
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r := R_REGS;
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n := R_REGS;
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irb_selc := '0';
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irb_seli := '0';
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irb_ack := '0';
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irb_busy := '0';
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irb_err := '0';
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irb_dout := (others=>'0');
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irb_lam := '0';
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icpreq := '0';
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icpureset := '0';
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if RB_MREQ.req='1' then
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if RB_MREQ.addr(7 downto 5)=RB_ADDR_CORE(7 downto 5) then
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irb_selc := '1';
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irb_ack := '1'; -- ack all, unless reject or busy
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end if;
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if RB_MREQ.addr(7 downto 5)=RB_ADDR_IBUS(7 downto 5) then
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irb_seli := '1';
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irb_ack := '1'; -- ack all, unless reject or busy
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end if;
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end if;
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-- look for init's against the rbus base address, generate subsystem resets
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if RB_MREQ.init='1' and RB_MREQ.we='1' and RB_MREQ.addr=RB_ADDR_CORE then
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icpureset := RB_MREQ.din(0);
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end if;
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case r.state is
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when s_idle => -- s_idle: wait for rbus access ------
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n.doinc := '0';
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n.waitstep := '0';
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if irb_seli = '1' then
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n.cpfunc := c_cpfunc_rmem;
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n.cpfunc(0) := RB_MREQ.we;
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icpreq := '1';
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elsif irb_selc = '1' then
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case RB_MREQ.addr(4 downto 0) is
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when c_rbaddr_conf => -- conf -------------------------
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null; -- currently no action
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when c_rbaddr_cntl => -- cntl -------------------------
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n.cpfunc := RB_MREQ.din(n.cpfunc'range);
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if RB_MREQ.we = '1' then
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icpreq := '1';
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if RB_MREQ.din(3 downto 0) = c_cpfunc_step(3 downto 0) then
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n.waitstep := '1';
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end if;
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end if;
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when c_rbaddr_stat => -- stat -------------------------
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irb_dout(c_stat_rbf_cmderr) := CP_STAT.cmderr;
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irb_dout(c_stat_rbf_cmdmerr) := CP_STAT.cmdmerr;
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irb_dout(c_stat_rbf_cpugo) := CP_STAT.cpugo;
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irb_dout(c_stat_rbf_cpuhalt) := CP_STAT.cpuhalt;
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irb_dout(c_stat_rbf_cpurust) := CP_STAT.cpurust;
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when c_rbaddr_psw => -- psw --------------------------
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n.cpfunc := c_cpfunc_rpsw;
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n.cpfunc(0) := RB_MREQ.we;
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icpreq := '1';
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when c_rbaddr_al => -- al ---------------------------
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irb_dout(c_al_rbf_addr) := r.addr(c_al_rbf_addr);
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if RB_MREQ.we = '1' then
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n.addr := (others=>'0'); -- write to al clears ah !!
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n.ena_22bit := '0';
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n.ena_ubmap := '0';
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n.addr(c_al_rbf_addr) := RB_MREQ.din(c_al_rbf_addr);
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end if;
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when c_rbaddr_ah => -- ah ---------------------------
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irb_dout(c_ah_rbf_ena_ubmap) := r.ena_ubmap;
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irb_dout(c_ah_rbf_ena_22bit) := r.ena_22bit;
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irb_dout(c_ah_rbf_addr) := r.addr(21 downto 16);
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if RB_MREQ.we = '1' then
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n.addr(21 downto 16) := RB_MREQ.din(c_ah_rbf_addr);
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n.ena_22bit := RB_MREQ.din(c_ah_rbf_ena_22bit);
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n.ena_ubmap := RB_MREQ.din(c_ah_rbf_ena_ubmap);
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end if;
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when c_rbaddr_mem => -- mem -----------------
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n.cpfunc := c_cpfunc_rmem;
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n.cpfunc(0) := RB_MREQ.we;
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icpreq := '1';
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when c_rbaddr_memi => -- memi ----------------
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n.cpfunc := c_cpfunc_rmem;
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n.cpfunc(0) := RB_MREQ.we;
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n.doinc := '1';
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icpreq := '1';
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when c_rbaddr_r0 | c_rbaddr_r1 |
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c_rbaddr_r2 | c_rbaddr_r3 |
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c_rbaddr_r4 | c_rbaddr_r5 |
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c_rbaddr_sp | c_rbaddr_pc => -- r* ------------------
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n.cpfunc := c_cpfunc_rreg;
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n.cpfunc(0) := RB_MREQ.we;
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icpreq := '1';
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when c_rbaddr_ibrb => -- ibrb ----------------
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irb_dout(c_ibrb_ibf_base) := r.ibrbase;
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irb_dout(c_ibrb_ibf_be) := r.ibrberet;
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if RB_MREQ.we = '1' then
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n.ibrbase := RB_MREQ.din(c_ibrb_ibf_base);
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n.ibrberet := RB_MREQ.din(c_ibrb_ibf_be);
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if RB_MREQ.din(c_ibrb_ibf_be) = "00" then -- both be=0 ?
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n.ibrbe := "11";
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else -- otherwise take 2 LSB's
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n.ibrbe := RB_MREQ.din(c_ibrb_ibf_be);
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end if;
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end if;
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when others =>
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irb_ack := '0';
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end case;
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end if;
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if icpreq = '1' then
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irb_busy := '1';
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n.cpreq := '1';
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n.state := s_cpwait;
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end if;
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when s_cpwait => -- s_cpwait: wait for cp port ack ----
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n.cpreq := '0'; -- cpreq only for 1 cycle
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if (irb_selc or irb_seli) = '0' then -- rbus cycle abort
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n.state := s_idle; -- quit
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else
|
321 |
|
|
irb_dout := CP_DOUT;
|
322 |
|
|
irb_err := CP_STAT.cmderr or CP_STAT.cmdmerr;
|
323 |
|
|
if CP_STAT.cmdack = '1' then -- normal cycle end
|
324 |
|
|
if r.doinc = '1' then
|
325 |
|
|
n.addr := unsigned(r.addr) + 1;
|
326 |
|
|
end if;
|
327 |
|
|
if r.waitstep = '1' then
|
328 |
|
|
irb_busy := '1';
|
329 |
|
|
n.state := s_cpstep;
|
330 |
|
|
else
|
331 |
|
|
n.state := s_idle;
|
332 |
|
|
end if;
|
333 |
|
|
else
|
334 |
|
|
irb_busy := '1';
|
335 |
|
|
end if;
|
336 |
|
|
end if;
|
337 |
|
|
|
338 |
|
|
when s_cpstep => -- s_cpstep: wait for cpustep done ---
|
339 |
|
|
if irb_selc = '0' then -- rbus cycle abort
|
340 |
|
|
n.state := s_idle; -- quit
|
341 |
|
|
else
|
342 |
|
|
if CP_STAT.cpustep = '0' then -- cpustep done
|
343 |
|
|
n.state := s_idle;
|
344 |
|
|
else
|
345 |
|
|
irb_busy := '1';
|
346 |
|
|
end if;
|
347 |
|
|
end if;
|
348 |
|
|
|
349 |
|
|
when others => null;
|
350 |
|
|
end case;
|
351 |
|
|
|
352 |
|
|
icpaddr := cp_addr_init;
|
353 |
|
|
icpaddr.addr := r.addr;
|
354 |
|
|
icpaddr.racc := '0';
|
355 |
|
|
icpaddr.be := "11";
|
356 |
|
|
icpaddr.ena_22bit := r.ena_22bit;
|
357 |
|
|
icpaddr.ena_ubmap := r.ena_ubmap;
|
358 |
|
|
|
359 |
|
|
if irb_seli = '1' then
|
360 |
|
|
icpaddr.addr(15 downto 13) := "111";
|
361 |
|
|
icpaddr.addr(c_ibrb_ibf_base) := r.ibrbase;
|
362 |
|
|
icpaddr.addr(5 downto 1) := RB_MREQ.addr(4 downto 0);
|
363 |
|
|
icpaddr.racc := '1';
|
364 |
|
|
icpaddr.be := r.ibrbe;
|
365 |
|
|
icpaddr.ena_22bit := '0';
|
366 |
|
|
icpaddr.ena_ubmap := '0';
|
367 |
|
|
end if;
|
368 |
|
|
|
369 |
|
|
n.cpugo_1 := CP_STAT.cpugo; -- delay cpugo
|
370 |
|
|
if CP_STAT.cpugo='0' and r.cpugo_1='1' then -- cpugo 1 -> 0 transition ?
|
371 |
|
|
irb_lam := '1';
|
372 |
|
|
end if;
|
373 |
|
|
|
374 |
|
|
N_REGS <= n;
|
375 |
|
|
|
376 |
|
|
RB_SRES.ack <= irb_ack;
|
377 |
|
|
RB_SRES.err <= irb_err;
|
378 |
|
|
RB_SRES.busy <= irb_busy;
|
379 |
|
|
RB_SRES.dout <= irb_dout;
|
380 |
|
|
|
381 |
|
|
RB_STAT(0) <= CP_STAT.cpugo;
|
382 |
|
|
RB_STAT(1) <= CP_STAT.cpuhalt or CP_STAT.cpurust(CP_STAT.cpurust'left);
|
383 |
|
|
RB_STAT(2) <= CP_STAT.cmderr or CP_STAT.cmdmerr;
|
384 |
|
|
|
385 |
|
|
RRI_LAM <= irb_lam;
|
386 |
|
|
|
387 |
|
|
CPU_RESET <= icpureset;
|
388 |
|
|
|
389 |
|
|
CP_CNTL.req <= r.cpreq;
|
390 |
|
|
CP_CNTL.func <= r.cpfunc;
|
391 |
|
|
CP_CNTL.rnum <= RB_MREQ.addr(2 downto 0);
|
392 |
|
|
|
393 |
|
|
CP_ADDR <= icpaddr;
|
394 |
|
|
CP_DIN <= RB_MREQ.din;
|
395 |
|
|
|
396 |
|
|
end process proc_next;
|
397 |
|
|
|
398 |
|
|
end syn;
|