URL https://opencores.org/ocsvn/w11/w11/trunk

Subversion Repositories w11

[/] [w11/] [tags/] [w11a_V0.74/] [rtl/] [w11a/] [pdp11_dmcmon.vbom] - Blame information for rev 36

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# libs
../vlib/slvtypes.vhd
../vlib/memlib/memlib.vhd
../vlib/rbus/rblib.vhd
pdp11.vbom
# components
[sim]../vlib/memlib/ram_2swsr_rfirst_gen.vbom
[xst]../vlib/memlib/ram_2swsr_rfirst_gen_unisim.vbom
[vsyn]../vlib/memlib/ram_2swsr_rfirst_gen.vbom
[sim]../vlib/memlib/ram_1swar_1ar_gen.vbom
[xst]../vlib/memlib/ram_1swar_1ar_gen_unisim.vbom
[vsyn]../vlib/memlib/ram_1swar_1ar_gen.vbom
# design
pdp11_dmcmon.vhd

Line No.	Rev	Author	Line
1	34	wfjm	`# libs`
2			`../vlib/slvtypes.vhd`
3			`../vlib/memlib/memlib.vhd`
4			`../vlib/rbus/rblib.vhd`
5			`pdp11.vbom`
6			`# components`
7			`[sim]../vlib/memlib/ram_2swsr_rfirst_gen.vbom`
8	36	wfjm	`[xst]../vlib/memlib/ram_2swsr_rfirst_gen_unisim.vbom`
9			`[vsyn]../vlib/memlib/ram_2swsr_rfirst_gen.vbom`
10	34	wfjm	`[sim]../vlib/memlib/ram_1swar_1ar_gen.vbom`
11	36	wfjm	`[xst]../vlib/memlib/ram_1swar_1ar_gen_unisim.vbom`
12			`[vsyn]../vlib/memlib/ram_1swar_1ar_gen.vbom`
13	34	wfjm	`# design`
14			`pdp11_dmcmon.vhd`

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Subversion Repositories w11

[/] [w11/] [tags/] [w11a_V0.74/] [rtl/] [w11a/] [pdp11_dmcmon.vbom] - Blame information for rev 36