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-- $Id: pdp11_dmcmon.vhd 709 2015-08-06 18:08:49Z mueller $
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--
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-- Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: pdp11_dmcmon- syn
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-- Description: pdp11: debug&moni: cpu monitor
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--
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-- Dependencies: memlib/ram_2swsr_rfirst_gen
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-- memlib/ram_1swar_1ar_gen
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-- Test bench: -
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--
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-- Target Devices: generic
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-- Tool versions: ise 14.7; viv 2014.4; ghdl 0.31
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--
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2015-08-02 707 14.7 131013 xc6slx16-2 213 233 16 151 s 5.9
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--
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-- Revision History: -
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-- Date Rev Version Comment
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-- 2015-08-03 709 1.0 Initial version
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-- 2015-07-05 697 0.1 First draft
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------------------------------------------------------------------------------
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--
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-- rbus registers:
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--
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-- Addr Bits Name r/w/f Function
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-- 000 cntl r/w/f Control register
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-- 04 mwsup r/w/- mem wait suppress (used when start=1)
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-- 03 imode r/w/- instruction mode (used when start=1)
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-- 02 wena r/w/- wrap enabled (")
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-- 01 stop r/w/f writing 1 stops moni
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-- 00 start r/w/f writing 1 starts moni and clears addr
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-- 001 stat r/-/- Status register
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-- 15:13 bsize r/-/- buffer size (AWIDTH-8)
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-- 12:09 malcnt r/-/- valid entries in memory access log
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-- 00 wrap r/-/- line address wrapped (cleared on go)
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-- 010 addr r/w/- Address register (writable when stopped)
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-- *:04 laddr r/w/- line address
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-- 03:00 waddr r/w/- word address (0000 to 1000)
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-- 011 data r/w/- Data register
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-- 100 iaddr r/-/- Last instruction cmon address
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-- *:04 laddr r/-/- line address
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-- 03:00 r/-/- -always zero-
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-- 101 ipc r/-/- Last instruction pc
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-- 110 ireg r/-/- Last instruction
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-- 111 imal r/-/- Last instruction memory access log
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--
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-- data format:
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-- word 8 15 : vm.vmcntl.req
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-- if req = 1
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-- 14 : vm.vmcntl.wacc
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-- 13 : vm.vmcntl.macc
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-- 12 : vm.vmcntl.cacc
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-- 11 : vm.vmcntl.bytop
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-- 10 : vm.vmcntl.dspace
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-- if req = 0
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-- 14 : vm.vmcntl.ack
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-- 13 : vm.vmcntl.err
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-- if ack = 1 and err = 0
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-- 12 : vm.vmcntl.trap_ysv
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-- 11 : vm.vmcntl.trap_mmu
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-- 10 : mwdrop (signals memwait suppress when mwsup=1)
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-- if ack = 0 and err = 1
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-- 12:10 : vm error code (priority encoded, but only one anyone)
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-- 000 err_odd = 1
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-- 001 err_mmu = 1
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-- 010 err_nxm = 1
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-- 011 err_iobto = 1
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-- 100 err_rsv = 1
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--
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-- 09 : se.istart
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-- 08 : se.idone
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--
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-- if imode = 0
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-- 07:00 : se.snum
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-- if imode = 1
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-- 07:00 : cnum
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--
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-- word 7 15:01 : dp.pc (captured at se.istart)
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-- 00 : idecode (is dp.ireg_we delayed by 1 cycle)
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-- word 6 15:00 : dp.ireg
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-- word 5 15:14 : dp.psw.cmode
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-- 13:12 : dp.psw.pmode
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-- 11 : dp.psw.rset
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-- if imode = 0
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-- 10 : dp.dres valid
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-- 09 : dp.ddst_we
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-- 08 : dp.dsrc_we
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-- if imode = 1
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-- 10 : -- unused --
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-- 09 : -- unused --
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-- 08 : se.vfetch
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-- always
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-- 07:05 : dp.psw.pri
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-- 04 : dp.psw.tflag
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-- 03:00 : dp.psw.cc
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-- word 4 15:00 : dp.dsrc
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-- word 3 15:00 : dp.ddst
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-- word 2 15:00 : dp.dres (reged)
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-- word 1 15:00 : vm.vmaddr (captured at vm.vmcntl.req)
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-- word 0 15:00 : vm.vmdin or vm.vmdout (captured at req or ack)
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.memlib.all;
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use work.rblib.all;
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use work.pdp11.all;
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-- ----------------------------------------------------------------------------
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-- Note: AWIDTH has type natural to allow AWIDTH=0 can be used in if generates
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-- to control the instantiation. ghdl checks even for not instantiated
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-- entities the validity of generics, that's why natural needed here ....
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entity pdp11_dmcmon is -- debug&moni: cpu monitor
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generic (
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RB_ADDR : slv16 := slv(to_unsigned(16#0048#,16));
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AWIDTH : natural := 8);
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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RB_MREQ : in rb_mreq_type; -- rbus: request
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RB_SRES : out rb_sres_type; -- rbus: response
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DM_STAT_SE : in dm_stat_se_type; -- debug and monitor status - sequencer
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DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - data path
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DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox
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DM_STAT_CO : in dm_stat_co_type -- debug and monitor status - core
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);
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end pdp11_dmcmon;
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architecture syn of pdp11_dmcmon is
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constant rbaddr_cntl : slv3 := "000"; -- cntl address offset
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constant rbaddr_stat : slv3 := "001"; -- stat address offset
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constant rbaddr_addr : slv3 := "010"; -- addr address offset
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constant rbaddr_data : slv3 := "011"; -- data address offset
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constant rbaddr_iaddr : slv3 := "100"; -- iaddr address offset
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constant rbaddr_ipc : slv3 := "101"; -- ipc address offset
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constant rbaddr_ireg : slv3 := "110"; -- ireg address offset
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constant rbaddr_imal : slv3 := "111"; -- imal address offset
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constant cntl_rbf_mwsup : integer := 4;
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constant cntl_rbf_imode : integer := 3;
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constant cntl_rbf_wena : integer := 2;
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constant cntl_rbf_stop : integer := 1;
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constant cntl_rbf_start : integer := 0;
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subtype stat_rbf_bsize is integer range 15 downto 13;
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subtype stat_rbf_malcnt is integer range 12 downto 09;
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constant stat_rbf_wrap : integer := 0;
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subtype addr_rbf_laddr is integer range 4+AWIDTH-1 downto 4;
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subtype addr_rbf_waddr is integer range 3 downto 0;
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subtype bram_mf_port11 is integer range 143 downto 108;
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subtype bram_mf_port10 is integer range 107 downto 72;
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subtype bram_mf_port01 is integer range 71 downto 36;
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subtype bram_mf_port00 is integer range 35 downto 0;
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subtype bram_df_word8 is integer range 143 downto 128;
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subtype bram_df_word7 is integer range 127 downto 112;
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subtype bram_df_word6 is integer range 111 downto 96;
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subtype bram_df_word5 is integer range 95 downto 80;
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subtype bram_df_word4 is integer range 79 downto 64;
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subtype bram_df_word3 is integer range 63 downto 48;
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subtype bram_df_word2 is integer range 47 downto 32;
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subtype bram_df_word1 is integer range 31 downto 16;
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subtype bram_df_word0 is integer range 15 downto 0;
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constant dat8_ibf_req : integer := 15;
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constant dat8_ibf_wacc : integer := 14; -- if req=1
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constant dat8_ibf_macc : integer := 13; -- "
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constant dat8_ibf_cacc : integer := 12; -- "
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constant dat8_ibf_bytop : integer := 11; -- "
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constant dat8_ibf_dspace : integer := 10; -- "
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constant dat8_ibf_ack : integer := 14; -- if req=0
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constant dat8_ibf_err : integer := 13; -- "
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constant dat8_ibf_trap_ysv : integer := 12; -- if req=0 ack=1 err=0
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constant dat8_ibf_trap_mmu : integer := 11; -- "
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constant dat8_ibf_mwdrop : integer := 10; -- "
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subtype dat8_ibf_vmerr is integer range 12 downto 10;-- if req=0 ack=0 err=1
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constant dat8_ibf_istart : integer := 9; -- always
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constant dat8_ibf_idone : integer := 8; -- "
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constant vmerr_odd : slv3 := "001"; -- vm error code: err_odd
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constant vmerr_mmu : slv3 := "010"; -- vm error code: err_mmu
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constant vmerr_nxm : slv3 := "011"; -- vm error code: err_nxm
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constant vmerr_iobto : slv3 := "100"; -- vm error code: err_iobto
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constant vmerr_rsv : slv3 := "101"; -- vm error code: err_rsv
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subtype dat8_ibf_snum is integer range 7 downto 0;
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subtype dat8_ibf_cnum is integer range 7 downto 0;
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subtype dat7_ibf_pc is integer range 15 downto 1;
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constant dat7_ibf_idecode : integer := 0;
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subtype dat5_ibf_cmode is integer range 15 downto 14;
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subtype dat5_ibf_pmode is integer range 13 downto 12;
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constant dat5_ibf_rset : integer := 11;
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constant dat5_ibf_dres_val : integer := 10; -- if imode=0
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constant dat5_ibf_ddst_we : integer := 9;
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constant dat5_ibf_dsrc_we : integer := 8;
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constant dat5_ibf_vfetch : integer := 8; -- if imode=1
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subtype dat5_ibf_pri is integer range 7 downto 5;
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constant dat5_ibf_tflag : integer := 4;
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subtype dat5_ibf_cc is integer range 3 downto 0;
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constant laddrzero : slv(AWIDTH-1 downto 0) := (others=>'0');
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constant laddrlast : slv(AWIDTH-1 downto 0) := (others=>'1');
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type regs_type is record
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rbsel : slbit; -- rbus select
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mwsup : slbit; -- mwsup flag (mem wait suppress)
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imode : slbit; -- imode flag
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wena : slbit; -- wena flag (wrap enable)
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go : slbit; -- go flag
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active : slbit; -- active flag
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wrap : slbit; -- laddr wrap flag
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laddr : slv(AWIDTH-1 downto 0); -- line address
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waddr : slv4; -- word address
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cnum : slv8; -- clk counter
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mal_waddr : slv4; -- mem acc log: write address
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mal_raddr : slv4; -- mem acc log: read address
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dp_pc_fet : slv16_1; -- dp.pc_fet (capture on se.istart)
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dp_pc_dec : slv16_1; -- dp.pc_dec (capture on dp.ireg_we + 1)
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dp_ireg : slv16; -- dp.ireg
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dp_ireg_we : slbit; -- dp.ireg_we
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dp_ireg_we_1 : slbit; -- dp.ireg_we last cycle
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dp_dres : slv16; -- dp.dres
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dp_dsrc_we : slbit; -- dp.dsrc_we
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dp_ddst_we : slbit; -- dp.ddst_we
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dp_dres_val : slbit; -- dp.dres valid
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vm_addr : slv16; -- vm.vmaddr
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vm_din : slv16; -- vm.vmdin
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vm_dout : slv16; -- vm.vmdout
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vm_req : slbit; -- vm.vmcntl.req
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vm_wacc : slbit; -- vm.vmcntl.wacc
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vm_macc : slbit; -- vm.vmcntl.macc
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vm_cacc : slbit; -- vm.vmcntl.cacc
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vm_bytop : slbit; -- vm.vmcntl.bytop
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vm_dspace : slbit; -- vm.vmcntl.dspace
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vm_addr_1 : slv16; -- vm.vmaddr last request
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vm_dout_1 : slv16; -- vm.vmdout last request
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vm_wacc_1 : slbit; -- vm.vmcntl.wacc last request
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vm_macc_1 : slbit; -- vm.vmcntl.macc last request
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vm_cacc_1 : slbit; -- vm.vmcntl.cacc last request
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vm_bytop_1 : slbit; -- vm.vmcntl.bytop last request
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vm_dspace_1 : slbit; -- vm.vmcntl.dspace last request
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vm_ack : slbit; -- vm.vmstat.ack
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vm_err : slbit; -- vm.vmstat.err
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vm_err_odd : slbit; -- vm.vmstat.err_odd
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vm_err_mmu : slbit; -- vm.vmstat.err_mmu
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vm_err_nxm : slbit; -- vm.vmstat.err_nxm
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vm_err_iobto : slbit; -- vm.vmstat.err_iobto
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vm_err_rsv : slbit; -- vm.vmstat.err_rsv
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vm_trap_ysv : slbit; -- vm.vmstat.trap_ysv
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vm_trap_mmu : slbit; -- vm.vmstat.trap_mmu
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vm_pend : slbit; -- vm req pending
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se_istart : slbit; -- se.istart
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se_istart_1 : slbit; -- se.istart last cycle
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se_idone : slbit; -- se.idone
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se_vfetch : slbit; -- se.vfetch
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se_snum : slv8; -- se.snum
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mwdrop : slbit; -- mem wait drop flag
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end record regs_type;
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287 |
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constant regs_init : regs_type := (
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'0', -- rbsel
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'0','1', -- mwsup,imode
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'1','1','0', -- wena,go,active
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'0', -- wrap
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laddrzero, -- laddr
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"0000", -- waddr
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(others=>'0'), -- cnum
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295 |
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(others=>'0'), -- macwaddr
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296 |
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(others=>'0'), -- macraddr
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297 |
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(others=>'0'), -- dp_pc_fet
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298 |
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(others=>'0'), -- dp_pc_dec
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(others=>'0'), -- dp_ireq
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'0','0', -- dp_ireq_we,dp_ireq_we_1
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301 |
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(others=>'0'), -- dp_dres
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|
|
'0','0','0', -- dp_dsrc_we,dp_ddst_we,dp_dres_val
|
303 |
|
|
(others=>'0'), -- vm_addr
|
304 |
|
|
(others=>'0'), -- vm_din
|
305 |
|
|
(others=>'0'), -- vm_dout
|
306 |
|
|
'0','0','0','0','0','0', -- vm_req,..,vm_dspace
|
307 |
|
|
(others=>'0'), -- vm_addr_1
|
308 |
|
|
(others=>'0'), -- vm_dout_1
|
309 |
|
|
'0','0','0','0','0', -- vm_wacc_1,..,vm_dspace_1
|
310 |
|
|
'0','0', -- vm_ack,vm_err
|
311 |
|
|
'0','0','0','0','0', -- vm_err_*
|
312 |
|
|
'0','0', -- vm_trap_*
|
313 |
|
|
'0', -- vm_pend
|
314 |
|
|
'0','0','0','0', -- se_istart(_1),se_idone,se_vfetch
|
315 |
|
|
(others=>'0'), -- se_snum
|
316 |
|
|
'0' -- mwdrop
|
317 |
|
|
);
|
318 |
|
|
|
319 |
|
|
signal R_REGS : regs_type := regs_init; -- state registers
|
320 |
|
|
signal N_REGS : regs_type := regs_init; -- next value state regs
|
321 |
|
|
|
322 |
|
|
signal BRAM_EN : slbit := '0';
|
323 |
|
|
signal BRAM_WE : slbit := '0';
|
324 |
|
|
signal BRAM_ADDRA : slv(AWIDTH downto 0) := (others=>'0');
|
325 |
|
|
signal BRAM_ADDRB : slv(AWIDTH downto 0) := (others=>'0');
|
326 |
|
|
signal BRAM_DI : slv(143 downto 0) := (others=>'0');
|
327 |
|
|
signal BRAM_DO : slv(143 downto 0) := (others=>'0');
|
328 |
|
|
|
329 |
|
|
signal MAL_WE : slbit := '0';
|
330 |
|
|
signal MAL_DI : slv16 := (others=>'0');
|
331 |
|
|
signal MAL_DO : slv16 := (others=>'0');
|
332 |
|
|
|
333 |
|
|
begin
|
334 |
|
|
|
335 |
|
|
assert AWIDTH>=8 and AWIDTH<=11
|
336 |
|
|
report "assert(AWIDTH>=8 and AWIDTH<=11): unsupported AWIDTH"
|
337 |
|
|
severity failure;
|
338 |
|
|
|
339 |
|
|
BRAM0 : ram_2swsr_rfirst_gen
|
340 |
|
|
generic map (
|
341 |
|
|
AWIDTH => AWIDTH+1,
|
342 |
|
|
DWIDTH => 36)
|
343 |
|
|
port map (
|
344 |
|
|
CLKA => CLK,
|
345 |
|
|
CLKB => CLK,
|
346 |
|
|
ENA => BRAM_EN,
|
347 |
|
|
ENB => BRAM_EN,
|
348 |
|
|
WEA => BRAM_WE,
|
349 |
|
|
WEB => BRAM_WE,
|
350 |
|
|
ADDRA => BRAM_ADDRA,
|
351 |
|
|
ADDRB => BRAM_ADDRB,
|
352 |
|
|
DIA => BRAM_DI(bram_mf_port00),
|
353 |
|
|
DIB => BRAM_DI(bram_mf_port01),
|
354 |
|
|
DOA => BRAM_DO(bram_mf_port00),
|
355 |
|
|
DOB => BRAM_DO(bram_mf_port01)
|
356 |
|
|
);
|
357 |
|
|
|
358 |
|
|
BRAM1 : ram_2swsr_rfirst_gen
|
359 |
|
|
generic map (
|
360 |
|
|
AWIDTH => AWIDTH+1,
|
361 |
|
|
DWIDTH => 36)
|
362 |
|
|
port map (
|
363 |
|
|
CLKA => CLK,
|
364 |
|
|
CLKB => CLK,
|
365 |
|
|
ENA => BRAM_EN,
|
366 |
|
|
ENB => BRAM_EN,
|
367 |
|
|
WEA => BRAM_WE,
|
368 |
|
|
WEB => BRAM_WE,
|
369 |
|
|
ADDRA => BRAM_ADDRA,
|
370 |
|
|
ADDRB => BRAM_ADDRB,
|
371 |
|
|
DIA => BRAM_DI(bram_mf_port10),
|
372 |
|
|
DIB => BRAM_DI(bram_mf_port11),
|
373 |
|
|
DOA => BRAM_DO(bram_mf_port10),
|
374 |
|
|
DOB => BRAM_DO(bram_mf_port11)
|
375 |
|
|
);
|
376 |
|
|
|
377 |
|
|
MAL : ram_1swar_1ar_gen
|
378 |
|
|
generic map (
|
379 |
|
|
AWIDTH => 4,
|
380 |
|
|
DWIDTH => 16)
|
381 |
|
|
port map (
|
382 |
|
|
CLK => CLK,
|
383 |
|
|
WE => MAL_WE,
|
384 |
|
|
ADDRA => R_REGS.mal_waddr,
|
385 |
|
|
ADDRB => R_REGS.mal_raddr,
|
386 |
|
|
DI => MAL_DI,
|
387 |
|
|
DOA => open,
|
388 |
|
|
DOB => MAL_DO);
|
389 |
|
|
|
390 |
|
|
proc_regs: process (CLK)
|
391 |
|
|
begin
|
392 |
|
|
|
393 |
|
|
if rising_edge(CLK) then
|
394 |
|
|
if RESET = '1' then
|
395 |
|
|
R_REGS <= regs_init;
|
396 |
|
|
else
|
397 |
|
|
R_REGS <= N_REGS;
|
398 |
|
|
end if;
|
399 |
|
|
end if;
|
400 |
|
|
|
401 |
|
|
end process proc_regs;
|
402 |
|
|
|
403 |
|
|
proc_next: process (R_REGS, RB_MREQ, DM_STAT_SE,
|
404 |
|
|
DM_STAT_DP, DM_STAT_DP.psw, -- xst needs sub-records
|
405 |
|
|
DM_STAT_VM, DM_STAT_VM.vmcntl, DM_STAT_VM.vmstat,
|
406 |
|
|
DM_STAT_CO, BRAM_DO, MAL_DO)
|
407 |
|
|
|
408 |
|
|
variable r : regs_type := regs_init;
|
409 |
|
|
variable n : regs_type := regs_init;
|
410 |
|
|
variable irb_ack : slbit := '0';
|
411 |
|
|
variable irb_err : slbit := '0'; -- FIXME: needed ??
|
412 |
|
|
variable irb_busy : slbit := '0'; -- FIXME: needed ??
|
413 |
|
|
variable irb_dout : slv16 := (others=>'0');
|
414 |
|
|
variable irbena : slbit := '0';
|
415 |
|
|
variable ibramen : slbit := '0'; -- BRAM enable
|
416 |
|
|
variable ibramwe : slbit := '0'; -- BRAN we
|
417 |
|
|
variable igoeff : slbit := '0';
|
418 |
|
|
variable iactive : slbit := '0';
|
419 |
|
|
variable itake : slbit := '0';
|
420 |
|
|
variable laddr_inc : slbit := '0';
|
421 |
|
|
variable idat : slv(143 downto 0) := (others=>'0');
|
422 |
|
|
variable idat8 : slv16 := (others=>'0');
|
423 |
|
|
variable idat7 : slv16 := (others=>'0');
|
424 |
|
|
variable idat5 : slv16 := (others=>'0');
|
425 |
|
|
variable ivmerr : slv3 := (others=>'0');
|
426 |
|
|
|
427 |
|
|
variable imal_we : slbit := '0';
|
428 |
|
|
variable imal_re : slbit := '0';
|
429 |
|
|
variable imal_di : slv16 := (others=>'0');
|
430 |
|
|
variable imal_waddr_clr : slbit := '0';
|
431 |
|
|
variable imal_raddr_clr : slbit := '0';
|
432 |
|
|
|
433 |
|
|
begin
|
434 |
|
|
|
435 |
|
|
r := R_REGS;
|
436 |
|
|
n := R_REGS;
|
437 |
|
|
|
438 |
|
|
irb_ack := '0';
|
439 |
|
|
irb_err := '0';
|
440 |
|
|
irb_busy := '0';
|
441 |
|
|
irb_dout := (others=>'0');
|
442 |
|
|
irbena := RB_MREQ.re or RB_MREQ.we;
|
443 |
|
|
|
444 |
|
|
ibramen := '0';
|
445 |
|
|
ibramwe := '0';
|
446 |
|
|
|
447 |
|
|
igoeff := '0';
|
448 |
|
|
iactive := '0';
|
449 |
|
|
itake := '0';
|
450 |
|
|
|
451 |
|
|
laddr_inc := '0';
|
452 |
|
|
|
453 |
|
|
imal_we := '0';
|
454 |
|
|
imal_re := '0';
|
455 |
|
|
imal_di := r.vm_addr;
|
456 |
|
|
imal_waddr_clr := '0';
|
457 |
|
|
imal_raddr_clr := '0';
|
458 |
|
|
|
459 |
|
|
-- rbus address decoder
|
460 |
|
|
n.rbsel := '0';
|
461 |
|
|
if RB_MREQ.aval='1' and RB_MREQ.addr(12 downto 3)=RB_ADDR(12 downto 3) then
|
462 |
|
|
n.rbsel := '1';
|
463 |
|
|
ibramen := '1'; -- ensure bram read before rbus read
|
464 |
|
|
end if;
|
465 |
|
|
|
466 |
|
|
-- rbus transactions
|
467 |
|
|
if r.rbsel = '1' then
|
468 |
|
|
irb_ack := irbena; -- ack all accesses
|
469 |
|
|
case RB_MREQ.addr(2 downto 0) is
|
470 |
|
|
when rbaddr_cntl => -- cntl ------------------
|
471 |
|
|
if RB_MREQ.we = '1' then
|
472 |
|
|
if RB_MREQ.din(cntl_rbf_start) = '1' then
|
473 |
|
|
n.mwsup := RB_MREQ.din(cntl_rbf_mwsup);
|
474 |
|
|
n.imode := RB_MREQ.din(cntl_rbf_imode);
|
475 |
|
|
n.wena := RB_MREQ.din(cntl_rbf_wena);
|
476 |
|
|
n.go := '1';
|
477 |
|
|
n.wrap := '0';
|
478 |
|
|
n.laddr := laddrzero;
|
479 |
|
|
n.waddr := "0000";
|
480 |
|
|
end if;
|
481 |
|
|
if RB_MREQ.din(cntl_rbf_stop) = '1' then
|
482 |
|
|
n.go := '0';
|
483 |
|
|
end if;
|
484 |
|
|
end if;
|
485 |
|
|
|
486 |
|
|
when rbaddr_stat => -- stat ------------------
|
487 |
|
|
irb_err := RB_MREQ.we;
|
488 |
|
|
|
489 |
|
|
when rbaddr_addr => -- addr ------------------
|
490 |
|
|
if RB_MREQ.we = '1' then
|
491 |
|
|
if r.go='0' then
|
492 |
|
|
n.laddr := RB_MREQ.din(addr_rbf_laddr);
|
493 |
|
|
n.waddr := RB_MREQ.din(addr_rbf_waddr);
|
494 |
|
|
else
|
495 |
|
|
irb_err := '1'; -- error
|
496 |
|
|
end if;
|
497 |
|
|
end if;
|
498 |
|
|
|
499 |
|
|
when rbaddr_data => -- data ------------------
|
500 |
|
|
if r.go='1' or RB_MREQ.we='1' then
|
501 |
|
|
irb_err := '1'; -- error
|
502 |
|
|
elsif RB_MREQ.re = '1' then
|
503 |
|
|
if r.waddr(3) = '1' then -- equivalent waddr>=1000
|
504 |
|
|
n.waddr := (others=>'0');
|
505 |
|
|
laddr_inc := '1';
|
506 |
|
|
else
|
507 |
|
|
n.waddr := slv(unsigned(r.waddr) + 1);
|
508 |
|
|
end if;
|
509 |
|
|
end if;
|
510 |
|
|
|
511 |
|
|
when rbaddr_iaddr => -- iaddr -----------------
|
512 |
|
|
irb_err := RB_MREQ.we;
|
513 |
|
|
|
514 |
|
|
when rbaddr_ipc => -- ipc -------------------
|
515 |
|
|
irb_err := RB_MREQ.we;
|
516 |
|
|
|
517 |
|
|
when rbaddr_ireg => -- ireg ------------------
|
518 |
|
|
irb_err := RB_MREQ.we;
|
519 |
|
|
|
520 |
|
|
when rbaddr_imal => -- imal ------------------
|
521 |
|
|
irb_err := RB_MREQ.we;
|
522 |
|
|
imal_re := RB_MREQ.re;
|
523 |
|
|
|
524 |
|
|
when others => null; -- <> --------------------
|
525 |
|
|
end case;
|
526 |
|
|
end if;
|
527 |
|
|
|
528 |
|
|
-- rbus output driver
|
529 |
|
|
if r.rbsel = '1' then
|
530 |
|
|
case RB_MREQ.addr(2 downto 0) is
|
531 |
|
|
|
532 |
|
|
when rbaddr_cntl => -- cntl ------------------
|
533 |
|
|
irb_dout(cntl_rbf_mwsup) := r.mwsup;
|
534 |
|
|
irb_dout(cntl_rbf_imode) := r.imode;
|
535 |
|
|
irb_dout(cntl_rbf_wena) := r.wena;
|
536 |
|
|
irb_dout(cntl_rbf_start) := r.go;
|
537 |
|
|
|
538 |
|
|
when rbaddr_stat => -- stat ------------------
|
539 |
|
|
irb_dout(stat_rbf_bsize) := slv(to_unsigned(AWIDTH-8,3));
|
540 |
|
|
irb_dout(stat_rbf_malcnt) := r.mal_waddr;
|
541 |
|
|
irb_dout(stat_rbf_wrap) := r.wrap;
|
542 |
|
|
|
543 |
|
|
when rbaddr_addr => -- addr ------------------
|
544 |
|
|
irb_dout(addr_rbf_laddr) := r.laddr;
|
545 |
|
|
irb_dout(addr_rbf_waddr) := r.waddr;
|
546 |
|
|
|
547 |
|
|
when rbaddr_data => -- data ------------------
|
548 |
|
|
case r.waddr is
|
549 |
|
|
when "1000" => irb_dout := BRAM_DO(bram_df_word8);
|
550 |
|
|
when "0111" => irb_dout := BRAM_DO(bram_df_word7);
|
551 |
|
|
when "0110" => irb_dout := BRAM_DO(bram_df_word6);
|
552 |
|
|
when "0101" => irb_dout := BRAM_DO(bram_df_word5);
|
553 |
|
|
when "0100" => irb_dout := BRAM_DO(bram_df_word4);
|
554 |
|
|
when "0011" => irb_dout := BRAM_DO(bram_df_word3);
|
555 |
|
|
when "0010" => irb_dout := BRAM_DO(bram_df_word2);
|
556 |
|
|
when "0001" => irb_dout := BRAM_DO(bram_df_word1);
|
557 |
|
|
when "0000" => irb_dout := BRAM_DO(bram_df_word0);
|
558 |
|
|
when others => irb_dout := (others=>'0');
|
559 |
|
|
end case;
|
560 |
|
|
|
561 |
|
|
when rbaddr_iaddr => -- iaddr -----------------
|
562 |
|
|
null; -- FIXME_code: implement
|
563 |
|
|
|
564 |
|
|
when rbaddr_ipc => -- ipc -------------------
|
565 |
|
|
irb_dout(r.dp_pc_dec'range) := r.dp_pc_dec;
|
566 |
|
|
n.mal_raddr := (others=>'0');
|
567 |
|
|
|
568 |
|
|
when rbaddr_ireg => -- ireg ------------------
|
569 |
|
|
irb_dout := r.dp_ireg;
|
570 |
|
|
|
571 |
|
|
when rbaddr_imal => -- imal ------------------
|
572 |
|
|
irb_dout := MAL_DO;
|
573 |
|
|
|
574 |
|
|
when others => null;
|
575 |
|
|
end case;
|
576 |
|
|
end if;
|
577 |
|
|
|
578 |
|
|
-- cpu monitor
|
579 |
|
|
|
580 |
|
|
-- capture CPU state signals which are combinatorial logic
|
581 |
|
|
if DM_STAT_SE.istart = '1' then
|
582 |
|
|
n.dp_pc_fet := DM_STAT_DP.pc(15 downto 1);
|
583 |
|
|
end if;
|
584 |
|
|
n.dp_ireg := DM_STAT_DP.ireg;
|
585 |
|
|
n.dp_ireg_we := DM_STAT_DP.ireg_we;
|
586 |
|
|
n.dp_ireg_we_1 := r.dp_ireg_we;
|
587 |
|
|
if r.dp_ireg_we = '1' then -- dp_pc_dec update when dp_ireg changes
|
588 |
|
|
n.dp_pc_dec := r.dp_pc_fet;
|
589 |
|
|
end if;
|
590 |
|
|
|
591 |
|
|
n.dp_dsrc_we := DM_STAT_DP.dsrc_we;
|
592 |
|
|
n.dp_ddst_we := DM_STAT_DP.ddst_we;
|
593 |
|
|
n.dp_dres_val := '0';
|
594 |
|
|
if ((DM_STAT_DP.gpr_we or DM_STAT_DP.psr_we or -- capture dres only when
|
595 |
|
|
DM_STAT_DP.dsrc_we or DM_STAT_DP.ddst_we or -- actually used
|
596 |
|
|
DM_STAT_DP.dtmp_we or DM_STAT_DP.cpdout_we or
|
597 |
|
|
DM_STAT_VM.vmcntl.req) = '1') then
|
598 |
|
|
n.dp_dres := DM_STAT_DP.dres;
|
599 |
|
|
n.dp_dres_val := '1';
|
600 |
|
|
end if;
|
601 |
|
|
|
602 |
|
|
n.vm_req := DM_STAT_VM.vmcntl.req;
|
603 |
|
|
-- capture vm request data when vm_req asserted, need them in later cycles
|
604 |
|
|
-- don't update vmaddr for write part of rmw sequence
|
605 |
|
|
-- no valid address vmaddr given, address is kept in vmbox
|
606 |
|
|
if DM_STAT_VM.vmcntl.req = '1' then
|
607 |
|
|
n.vm_wacc_1 := r.vm_wacc;
|
608 |
|
|
n.vm_macc_1 := r.vm_macc;
|
609 |
|
|
n.vm_cacc_1 := r.vm_cacc;
|
610 |
|
|
n.vm_bytop_1 := r.vm_bytop;
|
611 |
|
|
n.vm_dspace_1 := r.vm_dspace;
|
612 |
|
|
n.vm_wacc := DM_STAT_VM.vmcntl.wacc;
|
613 |
|
|
n.vm_macc := DM_STAT_VM.vmcntl.macc;
|
614 |
|
|
n.vm_cacc := DM_STAT_VM.vmcntl.cacc;
|
615 |
|
|
n.vm_bytop := DM_STAT_VM.vmcntl.bytop;
|
616 |
|
|
n.vm_dspace := DM_STAT_VM.vmcntl.dspace;
|
617 |
|
|
if (DM_STAT_VM.vmcntl.macc and DM_STAT_VM.vmcntl.wacc) = '0' then
|
618 |
|
|
n.vm_addr_1 := r.vm_addr;
|
619 |
|
|
n.vm_addr := DM_STAT_VM.vmaddr;
|
620 |
|
|
end if;
|
621 |
|
|
n.vm_din := DM_STAT_VM.vmdin;
|
622 |
|
|
end if;
|
623 |
|
|
n.vm_ack := DM_STAT_VM.vmstat.ack;
|
624 |
|
|
n.vm_err := DM_STAT_VM.vmstat.err;
|
625 |
|
|
if DM_STAT_VM.vmstat.ack = '1' then
|
626 |
|
|
n.vm_dout_1 := r.vm_dout;
|
627 |
|
|
n.vm_dout := DM_STAT_VM.vmdout;
|
628 |
|
|
n.vm_trap_ysv := DM_STAT_VM.vmstat.trap_ysv;
|
629 |
|
|
n.vm_trap_mmu := DM_STAT_VM.vmstat.trap_mmu;
|
630 |
|
|
end if;
|
631 |
|
|
if DM_STAT_VM.vmstat.err = '1' then
|
632 |
|
|
n.vm_err_odd := DM_STAT_VM.vmstat.err_odd;
|
633 |
|
|
n.vm_err_mmu := DM_STAT_VM.vmstat.err_mmu;
|
634 |
|
|
n.vm_err_nxm := DM_STAT_VM.vmstat.err_nxm;
|
635 |
|
|
n.vm_err_iobto := DM_STAT_VM.vmstat.err_iobto;
|
636 |
|
|
n.vm_err_rsv := DM_STAT_VM.vmstat.err_rsv;
|
637 |
|
|
end if;
|
638 |
|
|
|
639 |
|
|
n.se_istart_1 := r.se_istart;
|
640 |
|
|
n.se_istart := DM_STAT_SE.istart;
|
641 |
|
|
n.se_idone := DM_STAT_SE.idone;
|
642 |
|
|
n.se_vfetch := DM_STAT_SE.vfetch;
|
643 |
|
|
n.se_snum := DM_STAT_SE.snum;
|
644 |
|
|
|
645 |
|
|
-- active state logic
|
646 |
|
|
igoeff := '0';
|
647 |
|
|
if r.go = '1' then
|
648 |
|
|
if DM_STAT_CO.cpugo='1' and DM_STAT_CO.cpususp='0' then
|
649 |
|
|
igoeff := '1';
|
650 |
|
|
end if;
|
651 |
|
|
if DM_STAT_CO.cpustep = '1' then
|
652 |
|
|
igoeff := '1';
|
653 |
|
|
end if;
|
654 |
|
|
end if;
|
655 |
|
|
|
656 |
|
|
iactive := r.active;
|
657 |
|
|
if unsigned(r.se_snum) = 0 then -- in idle state
|
658 |
|
|
if igoeff = '0' then -- if goeff=0 stop running
|
659 |
|
|
n.active := '0';
|
660 |
|
|
end if;
|
661 |
|
|
else -- in non-idle state
|
662 |
|
|
if igoeff = '1' then -- if goerr=1 start running
|
663 |
|
|
iactive := '1';
|
664 |
|
|
n.active := '1';
|
665 |
|
|
end if;
|
666 |
|
|
end if;
|
667 |
|
|
|
668 |
|
|
if r.vm_req = '1' then
|
669 |
|
|
n.mwdrop := '0';
|
670 |
|
|
n.vm_pend := '1';
|
671 |
|
|
elsif (r.vm_ack or r.vm_err) = '1' then
|
672 |
|
|
n.vm_pend := '0';
|
673 |
|
|
end if;
|
674 |
|
|
|
675 |
|
|
itake := '0';
|
676 |
|
|
if r.imode = '0' then -- imode=0
|
677 |
|
|
itake := '1'; -- take all
|
678 |
|
|
if r.mwsup = '1' then -- if mem wait suppress
|
679 |
|
|
if (r.vm_pend and not (r.vm_ack or r.vm_err)) = '1' then
|
680 |
|
|
itake := '0';
|
681 |
|
|
n.mwdrop := '1';
|
682 |
|
|
end if;
|
683 |
|
|
end if;
|
684 |
|
|
else -- imode=1
|
685 |
|
|
itake := r.se_idone or r.se_vfetch or r.vm_err;
|
686 |
|
|
end if;
|
687 |
|
|
|
688 |
|
|
if iactive='1' and itake='1' then -- active and enabled
|
689 |
|
|
ibramen := '1';
|
690 |
|
|
ibramwe := '1';
|
691 |
|
|
laddr_inc := '1';
|
692 |
|
|
end if;
|
693 |
|
|
|
694 |
|
|
if laddr_inc = '1' then
|
695 |
|
|
n.laddr := slv(unsigned(r.laddr) + 1);
|
696 |
|
|
if r.go='1' and r.laddr=laddrlast then
|
697 |
|
|
if r.wena = '1' then
|
698 |
|
|
n.wrap := '1';
|
699 |
|
|
else
|
700 |
|
|
n.go := '0';
|
701 |
|
|
end if;
|
702 |
|
|
end if;
|
703 |
|
|
end if;
|
704 |
|
|
|
705 |
|
|
-- last but not least: the clock cycle counter
|
706 |
|
|
n.cnum := slv(unsigned(r.cnum) + 1);
|
707 |
|
|
|
708 |
|
|
-- now build memory data word
|
709 |
|
|
idat := (others=>'0');
|
710 |
|
|
|
711 |
|
|
-- encode vm errors
|
712 |
|
|
ivmerr := (others=>'0');
|
713 |
|
|
if r.vm_err_odd = '1' then
|
714 |
|
|
ivmerr := vmerr_odd;
|
715 |
|
|
elsif r.vm_err_mmu = '1' then
|
716 |
|
|
ivmerr := vmerr_mmu;
|
717 |
|
|
elsif r.vm_err_nxm = '1' then
|
718 |
|
|
ivmerr := vmerr_nxm;
|
719 |
|
|
elsif r.vm_err_iobto = '1' then
|
720 |
|
|
ivmerr := vmerr_iobto;
|
721 |
|
|
elsif r.vm_err_rsv = '1' then
|
722 |
|
|
ivmerr := vmerr_rsv;
|
723 |
|
|
end if;
|
724 |
|
|
|
725 |
|
|
-- Note for imode=1
|
726 |
|
|
-- Write vm request data unless there is an error.
|
727 |
|
|
-- If in current or last cycle a ifetch (istart=1) was done use
|
728 |
|
|
-- attributes of previous request. If last cycle was an ifetch
|
729 |
|
|
-- and vm_ack set use also previous data. That ensures that the
|
730 |
|
|
-- values of current instruction are shown, and not of pre-fetch
|
731 |
|
|
|
732 |
|
|
-- build word8
|
733 |
|
|
idat8 := (others=>'0');
|
734 |
|
|
if r.vm_req = '1' or (r.imode='1' and r.vm_err='0') then
|
735 |
|
|
idat8(dat8_ibf_req) := '1';
|
736 |
|
|
if r.imode = '1' and (r.se_istart='1' or r.se_istart_1='1') then
|
737 |
|
|
idat8(dat8_ibf_wacc) := R_REGS.vm_wacc_1;
|
738 |
|
|
idat8(dat8_ibf_macc) := R_REGS.vm_macc_1;
|
739 |
|
|
idat8(dat8_ibf_cacc) := R_REGS.vm_cacc_1;
|
740 |
|
|
idat8(dat8_ibf_bytop) := R_REGS.vm_bytop_1;
|
741 |
|
|
idat8(dat8_ibf_dspace) := R_REGS.vm_dspace_1;
|
742 |
|
|
else
|
743 |
|
|
idat8(dat8_ibf_wacc) := R_REGS.vm_wacc;
|
744 |
|
|
idat8(dat8_ibf_macc) := R_REGS.vm_macc;
|
745 |
|
|
idat8(dat8_ibf_cacc) := R_REGS.vm_cacc;
|
746 |
|
|
idat8(dat8_ibf_bytop) := R_REGS.vm_bytop;
|
747 |
|
|
idat8(dat8_ibf_dspace) := R_REGS.vm_dspace;
|
748 |
|
|
end if;
|
749 |
|
|
else
|
750 |
|
|
idat8(dat8_ibf_ack) := R_REGS.vm_ack;
|
751 |
|
|
idat8(dat8_ibf_err) := R_REGS.vm_err;
|
752 |
|
|
if r.vm_ack = '1' then
|
753 |
|
|
idat8(dat8_ibf_trap_ysv) := R_REGS.vm_trap_ysv;
|
754 |
|
|
idat8(dat8_ibf_trap_mmu) := R_REGS.vm_trap_mmu;
|
755 |
|
|
idat8(dat8_ibf_mwdrop) := R_REGS.mwdrop;
|
756 |
|
|
elsif r.vm_err = '1' then
|
757 |
|
|
idat8(dat8_ibf_vmerr) := ivmerr;
|
758 |
|
|
end if;
|
759 |
|
|
end if;
|
760 |
|
|
idat8(dat8_ibf_istart) := R_REGS.se_istart;
|
761 |
|
|
idat8(dat8_ibf_idone) := R_REGS.se_idone;
|
762 |
|
|
|
763 |
|
|
if r.imode = '0' then
|
764 |
|
|
idat8(dat8_ibf_snum) := R_REGS.se_snum;
|
765 |
|
|
else
|
766 |
|
|
idat8(dat8_ibf_cnum) := R_REGS.cnum;
|
767 |
|
|
end if;
|
768 |
|
|
idat(bram_df_word8) := idat8;
|
769 |
|
|
|
770 |
|
|
-- build word7
|
771 |
|
|
idat7 := (others=>'0');
|
772 |
|
|
idat7(dat7_ibf_pc) := R_REGS.dp_pc_dec;
|
773 |
|
|
idat7(dat7_ibf_idecode):= R_REGS.dp_ireg_we_1;
|
774 |
|
|
idat(bram_df_word7) := idat7;
|
775 |
|
|
|
776 |
|
|
-- build word6
|
777 |
|
|
idat(bram_df_word6) := R_REGS.dp_ireg;
|
778 |
|
|
|
779 |
|
|
-- build word5
|
780 |
|
|
idat5 := (others=>'0');
|
781 |
|
|
idat5(dat5_ibf_cmode) := DM_STAT_DP.psw.cmode;
|
782 |
|
|
idat5(dat5_ibf_pmode) := DM_STAT_DP.psw.pmode;
|
783 |
|
|
idat5(dat5_ibf_rset) := DM_STAT_DP.psw.rset;
|
784 |
|
|
if r.imode = '0' then
|
785 |
|
|
idat5(dat5_ibf_dres_val) := R_REGS.dp_dres_val;
|
786 |
|
|
idat5(dat5_ibf_ddst_we) := R_REGS.dp_ddst_we;
|
787 |
|
|
idat5(dat5_ibf_dsrc_we) := R_REGS.dp_dsrc_we;
|
788 |
|
|
else
|
789 |
|
|
idat5(dat5_ibf_vfetch) := R_REGS.se_vfetch;
|
790 |
|
|
end if;
|
791 |
|
|
idat5(dat5_ibf_pri) := DM_STAT_DP.psw.pri;
|
792 |
|
|
idat5(dat5_ibf_tflag) := DM_STAT_DP.psw.tflag;
|
793 |
|
|
idat5(dat5_ibf_cc) := DM_STAT_DP.psw.cc;
|
794 |
|
|
idat(bram_df_word5) := idat5;
|
795 |
|
|
|
796 |
|
|
-- build word4 to word2
|
797 |
|
|
idat(bram_df_word4) := DM_STAT_DP.dsrc;
|
798 |
|
|
idat(bram_df_word3) := DM_STAT_DP.ddst;
|
799 |
|
|
idat(bram_df_word2) := R_REGS.dp_dres;
|
800 |
|
|
|
801 |
|
|
-- build word1
|
802 |
|
|
if r.imode = '1' and (r.se_istart='1' or r.se_istart_1='1') then
|
803 |
|
|
idat(bram_df_word1) := R_REGS.vm_addr_1;
|
804 |
|
|
else
|
805 |
|
|
idat(bram_df_word1) := R_REGS.vm_addr;
|
806 |
|
|
end if;
|
807 |
|
|
|
808 |
|
|
-- build word0
|
809 |
|
|
if r.vm_wacc = '1' then
|
810 |
|
|
idat(bram_df_word0) := R_REGS.vm_din;
|
811 |
|
|
else
|
812 |
|
|
if r.imode = '1' and r.se_istart_1 = '1' and r.vm_ack = '1' then
|
813 |
|
|
idat(bram_df_word0) := R_REGS.vm_dout_1;
|
814 |
|
|
else
|
815 |
|
|
idat(bram_df_word0) := R_REGS.vm_dout;
|
816 |
|
|
end if;
|
817 |
|
|
end if;
|
818 |
|
|
|
819 |
|
|
-- finally memory access log buffer logic
|
820 |
|
|
if r.vm_cacc = '0' then
|
821 |
|
|
if r.vm_req = '1' then
|
822 |
|
|
imal_we := '1';
|
823 |
|
|
imal_di := r.vm_addr;
|
824 |
|
|
elsif r.vm_ack='1' then
|
825 |
|
|
imal_we := '1';
|
826 |
|
|
if r.vm_wacc='1' then
|
827 |
|
|
imal_di := r.vm_din;
|
828 |
|
|
else
|
829 |
|
|
imal_di := r.vm_dout;
|
830 |
|
|
end if;
|
831 |
|
|
if r.vm_bytop = '1' then -- for byte read/write data
|
832 |
|
|
imal_di(15 downto 8) := (others=>'0'); -- zero msb (is undefined)
|
833 |
|
|
end if;
|
834 |
|
|
end if;
|
835 |
|
|
end if;
|
836 |
|
|
|
837 |
|
|
imal_waddr_clr := r.dp_ireg_we; -- FIXME: very preliminary !!!
|
838 |
|
|
|
839 |
|
|
if imal_waddr_clr = '1' then
|
840 |
|
|
n.mal_waddr := (others=>'0');
|
841 |
|
|
elsif imal_we = '1' then
|
842 |
|
|
n.mal_waddr := slv(unsigned(r.mal_waddr) + 1);
|
843 |
|
|
end if;
|
844 |
|
|
|
845 |
|
|
if imal_raddr_clr = '1' then
|
846 |
|
|
n.mal_raddr := (others=>'0');
|
847 |
|
|
elsif imal_re = '1' then
|
848 |
|
|
n.mal_raddr := slv(unsigned(r.mal_raddr) + 1);
|
849 |
|
|
end if;
|
850 |
|
|
|
851 |
|
|
N_REGS <= n;
|
852 |
|
|
|
853 |
|
|
BRAM_EN <= ibramen;
|
854 |
|
|
BRAM_WE <= ibramwe;
|
855 |
|
|
BRAM_ADDRA <= '0' & R_REGS.laddr;
|
856 |
|
|
BRAM_ADDRB <= '1' & R_REGS.laddr;
|
857 |
|
|
BRAM_DI <= idat;
|
858 |
|
|
|
859 |
|
|
MAL_WE <= imal_we;
|
860 |
|
|
MAL_DI <= imal_di;
|
861 |
|
|
|
862 |
|
|
RB_SRES.ack <= irb_ack;
|
863 |
|
|
RB_SRES.err <= irb_err;
|
864 |
|
|
RB_SRES.busy <= irb_busy;
|
865 |
|
|
RB_SRES.dout <= irb_dout;
|
866 |
|
|
|
867 |
|
|
end process proc_next;
|
868 |
|
|
|
869 |
|
|
end syn;
|